Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1339687526	175703	0	0
RunThenComplete_M	1339687526	1960829	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1339687526	175703	0	0
T1	270498	286	0	0
T2	66244	22	0	0
T3	1744	0	0	0
T4	93223	11	0	0
T7	845171	203	0	0
T15	15286	4	0	0
T19	516731	166	0	0
T20	969106	97	0	0
T30	105478	246	0	0
T31	191607	130	0	0
T35	0	246	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1339687526	1960829	0	0
T1	270498	4434	0	0
T2	66244	118	0	0
T3	1744	0	0	0
T4	93223	33	0	0
T7	845171	1937	0	0
T15	15286	29	0	0
T19	516731	935	0	0
T20	969106	560	0	0
T30	105478	5427	0	0
T31	191607	5073	0	0
T35	0	5427	0	0