Unified Coverage Report :: Module :: keccak_round

Module : keccak_round

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.81	94.55	100.00		73.33	91.18	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak	91.81	94.55	100.00		73.33	91.18	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.81	94.55	100.00		73.33	91.18	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	98.83	98.84	100.00	73.33	97.76	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	97.56	88.89		100.00	93.33	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak_p	99.42	100.00	98.75			98.93	100.00
u_prim_sec_anchor_buf	100.00	100.00
u_round_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
TOTAL		110	104	94.55
CONT_ASSIGN	177	0	0
ALWAYS	180	3	3	100.00
ALWAYS	186	70	65	92.86
CONT_ASSIGN	407	1	1	100.00
ALWAYS	411	7	7	100.00
ALWAYS	424	3	3	100.00
CONT_ASSIGN	450	1	1	100.00
ALWAYS	468	6	6	100.00
CONT_ASSIGN	477	1	1	100.00
ALWAYS	485	7	7	100.00
ALWAYS	507	4	3	75.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
ALWAYS	575	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
177		unreachable
180	3	3
186	1	1
188	1	1
189	1	1
190	1	1
192	1	1
193	1	1
195	1	1
196	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
206	1	1
208	1	1
210	1	1
212	1	1
214	1	1
215	1	1
216	1	1
221	1	1
223	1	1
224	1	1
226	1	1
229	1	1
230	1	1
231	1	1
233		unreachable
235	1	1
241	0	1
243	0	1
244		unreachable
246		unreachable
247		unreachable
249	0	1
251	0	1
260	1	1
261	1	1
272	1	1
273	1	1
274	1	1
275	1	1
278	1	1
281	1	1
282	1	1
284	1	1
292	1	1
293	1	1
301	1	1
304	1	1
307	1	1
308	1	1
317	1	1
318	1	1
327	1	1
333	1	1
336	1	1
339	1	1
342	1	1
343	1	1
352	1	1
353	1	1
361	1	1
363	1	1
365		unreachable
367		unreachable
368		unreachable
371	1	1
373	1	1
376	1	1
377	1	1
382	0	1
387	1	1
388	1	1
400	1	1
401	1	1
			MISSING_ELSE
407	1	1
411	1	1
412	1	1
413	1	1
414	1	1
416	1	1
417	1	1
418	1	1
424	1	1
425	1	1
427	1	1
450	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
			MISSING_ELSE
477	1	1
485	1	1
486	1	1
487	1	1
488	1	1
492	1	1
493	1	1
496	1	1
			MISSING_ELSE
507	1	1
509	1	1
511	1	1
513	0	1
			MISSING_ELSE
			MISSING_ELSE
518	1	1
548	1	1
549	1	1
551	1	1
575	1	1
576	1	1
578	1	1

---

Cond Coverage for Module : keccak_round

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       177
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T2,T3,T17

 LINE       224
 EXPRESSION (EnMasking && run_i)
             ----1----    --2--

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T2,T3,T17

 LINE       272
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T33
0	1	Covered	T2,T3,T17
1	0	Covered	T2,T17,T33

 LINE       450
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T2,T3

 LINE       450
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       492
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T2,T3,T17

---

FSM Coverage for Module : keccak_round

Summary for FSM :: keccak_st

	Total	Covered	Percent
States	8	6	75.00	(Not included in score)
Transitions	15	11	73.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: keccak_st

---

states	Line No.	Covered	Tests
KeccakStActive	233	Not Covered
KeccakStError	382	Not Covered
KeccakStIdle	212	Covered	T1,T2,T3
KeccakStPhase1	226	Covered	T2,T3,T17
KeccakStPhase2Cycle1	273	Covered	T2,T3,T17
KeccakStPhase2Cycle2	304	Covered	T2,T3,T17
KeccakStPhase2Cycle3	339	Covered	T2,T3,T17
KeccakStTerminalError	401	Covered	T7,T12,T13

transitions	Line No.	Covered	Tests
KeccakStActive->KeccakStIdle	244	Not Covered
KeccakStActive->KeccakStTerminalError	401	Not Covered
KeccakStError->KeccakStTerminalError	401	Not Covered
KeccakStIdle->KeccakStActive	233	Not Covered
KeccakStIdle->KeccakStPhase1	226	Covered	T2,T3,T17
KeccakStIdle->KeccakStTerminalError	401	Covered	T7,T12,T13
KeccakStPhase1->KeccakStPhase2Cycle1	273	Covered	T2,T3,T17
KeccakStPhase1->KeccakStTerminalError	401	Covered	T26,T40,T41
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2	304	Covered	T2,T3,T17
KeccakStPhase2Cycle1->KeccakStTerminalError	401	Covered	T42,T43,T44
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3	339	Covered	T2,T3,T17
KeccakStPhase2Cycle2->KeccakStTerminalError	401	Covered	T45,T46,T47
KeccakStPhase2Cycle3->KeccakStIdle	365	Covered	T2,T3,T17
KeccakStPhase2Cycle3->KeccakStPhase1	371	Covered	T2,T3,T17
KeccakStPhase2Cycle3->KeccakStTerminalError	401	Covered	T48,T49,T50

---

Branch Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
Branches		34	31	91.18
TERNARY	450	2	2	100.00
IF	180	2	2	100.00
CASE	208	13	11	84.62
IF	400	2	2	100.00
IF	468	4	4	100.00
IF	486	2	2	100.00
IF	509	3	2	66.67
IF	575	2	2	100.00
IF	411	2	2	100.00
IF	424	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	450	((keccak_st == KeccakStIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	180	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	208	case (keccak_st)
-2-:	210	if (valid_i)
-3-:	216	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))
-4-:	224	if ((EnMasking && run_i))
-5-:	231	if (((!EnMasking) && run_i))
-6-:	243	if (rnd_eq_end)
-7-:	272	if ((rand_early_i || rand_valid_i))
-8-:	363	if (rnd_eq_end)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
KeccakStIdle	1	-	-	-	-	-	-	Covered	T2,T3,T17
KeccakStIdle	0	1	-	-	-	-	-	Covered	T2,T3,T17
KeccakStIdle	0	0	1	-	-	-	-	Covered	T2,T3,T17
KeccakStIdle	0	0	0	1	-	-	-	Unreachable
KeccakStIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
KeccakStActive	-	-	-	-	1	-	-	Unreachable
KeccakStActive	-	-	-	-	0	-	-	Not Covered
KeccakStPhase1	-	-	-	-	-	1	-	Covered	T2,T3,T17
KeccakStPhase1	-	-	-	-	-	0	-	Covered	T2,T17,T33
KeccakStPhase2Cycle1	-	-	-	-	-	-	-	Covered	T2,T3,T17
KeccakStPhase2Cycle2	-	-	-	-	-	-	-	Covered	T2,T3,T17
KeccakStPhase2Cycle3	-	-	-	-	-	-	1	Unreachable	T2,T3,T17
KeccakStPhase2Cycle3	-	-	-	-	-	-	0	Covered	T2,T3,T17
KeccakStError	-	-	-	-	-	-	-	Not Covered
KeccakStTerminalError	-	-	-	-	-	-	-	Covered	T7,T12,T13
default	-	-	-	-	-	-	-	Covered	T28,T29,T32

	LineNo.	Expression
-1-:	400	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	468	if ((!rst_n))
-2-:	470	if (rst_storage)
-3-:	472	if (update_storage)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T17
0	0	1	Covered	T2,T3,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	486	if (xor_message)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	if (rst_storage)
-2-:	511	if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T2,T3,T17
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	575	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	411	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	424	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keccak_round

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClearAssertStIdle_A	1474723140	203709	0	0
OneHot0ValidAndRun_A	1474723140	1474522125	0	0
ValidRunAssertStIdle_A	1474723140	36421491	0	0
WidthDivisableByDInWidth_A	933	933	0	0
gen_mask_st_chk.EnMaskingValidStates_A	1474723140	1474522125	0	0
u_state_regs_A	1474723140	1474522125	0	0

ClearAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	203709	0	0
T2	15751	2	0	0
T3	362878	36	0	0
T7	60114	15	0	0
T8	321414	107	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	513	0	0
T17	195600	374	0	0
T21	0	176	0	0
T33	193415	374	0	0
T34	202556	390	0	0
T35	0	2265	0	0

OneHot0ValidAndRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

ValidRunAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	36421491	0	0
T2	15751	147	0	0
T3	362878	3823	0	0
T7	60114	1716	0	0
T8	321414	10970	0	0
T12	4078	0	0	0
T13	2702	26	0	0
T14	281236	122886	0	0
T17	195600	99468	0	0
T21	0	17477	0	0
T33	193415	99468	0	0
T34	202556	105298	0	0

WidthDivisableByDInWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

gen_mask_st_chk.EnMaskingValidStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0