Unified Coverage Report :: Module :: keccak_2share

Module : keccak_2share

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.37	100.00	98.75			98.73	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p	99.37	100.00	98.75			98.73	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.37	100.00	98.75			98.73	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.42	100.00	98.75			98.93	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.81	94.55	100.00		73.33	91.18	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_2share_chi.g_chi_w[0].u_dom	100.00	100.00				100.00	100.00
g_2share_chi.g_chi_w[1].u_dom	100.00	100.00				100.00	100.00
g_2share_chi.g_chi_w[2].u_dom	100.00	100.00				100.00	100.00
g_2share_chi.g_chi_w[3].u_dom	100.00	100.00				100.00	100.00
g_2share_chi.g_chi_w[4].u_dom	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
TOTAL		297	297	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	107	3	3	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ROUTINE	363	0	0
ROUTINE	363	5	5	100.00
ROUTINE	376	0	0
ROUTINE	376	5	5	100.00
ROUTINE	389	4	4	100.00
ROUTINE	409	0	0
ROUTINE	409	10	10	100.00
ROUTINE	478	0	0
ROUTINE	478	4	4	100.00
ROUTINE	547	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
98	2	2
99	2	2
103	1	1
104	1	1
107	1	1
108	1	1
109	1	1
125	2	2
129	2	2
136	1	1
140	1	1
141	1	1
165	5	5
166	5	5
168	5	5
169	5	5
176	5	5
181	5	5
187	5	5
192	5	5
198	5	5
203	5	5
209	5	5
214	5	5
221	5	5
222	5	5
223	5	5
224	5	5
231	5	5
265	5	5
266	5	5
267	5	5
268	5	5
269	5	5
271	5	5
272	5	5
273	5	5
274	5	5
275	5	5
278	5	5
279	5	5
286	25	25
289	25	25
314	2	2
315	2	2
322	2	2
324	48	48
344	1	1
363	1	1
364	1	1
365	1	1
366	1	1
370	1	1
376	1	1
377	1	1
378	1	1
379	1	1
383	1	1
389	1	1
390	1	1
392	1	1
394	1	1
409	1	1
410	1	1
412	1	1
413	1	1
415	1	1
416	1	1
419	1	1
420	1	1
421	1	1
424	1	1
478	1	1
479	1	1
480	1	1
483	1	1
547	1	1
548	1	1
550	1	1

---

Cond Coverage for Module : keccak_2share

	Total	Covered	Percent
Conditions	160	158	98.75
Logical	160	158	98.75
Non-Logical	0	0
Event	0	0

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[0].a0_l : g_2share_chi.g_chi_w[0].a0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[1].a0_l : g_2share_chi.g_chi_w[1].a0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[2].a0_l : g_2share_chi.g_chi_w[2].a0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[3].a0_l : g_2share_chi.g_chi_w[3].a0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[4].a0_l : g_2share_chi.g_chi_w[4].a0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[0].a1_l : g_2share_chi.g_chi_w[0].a1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[1].a1_l : g_2share_chi.g_chi_w[1].a1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[2].a1_l : g_2share_chi.g_chi_w[2].a1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[3].a1_l : g_2share_chi.g_chi_w[3].a1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[4].a1_l : g_2share_chi.g_chi_w[4].a1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[0].b0_l : g_2share_chi.g_chi_w[0].b0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[1].b0_l : g_2share_chi.g_chi_w[1].b0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[2].b0_l : g_2share_chi.g_chi_w[2].b0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[3].b0_l : g_2share_chi.g_chi_w[3].b0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[4].b0_l : g_2share_chi.g_chi_w[4].b0_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[0].b1_l : g_2share_chi.g_chi_w[0].b1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[1].b1_l : g_2share_chi.g_chi_w[1].b1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[2].b1_l : g_2share_chi.g_chi_w[2].b1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[3].b1_l : g_2share_chi.g_chi_w[3].b1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[4].b1_l : g_2share_chi.g_chi_w[4].b1_h)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(0 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(0, 5)])
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(1 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(1, 5)])
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(2 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(2, 5)])
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(3 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(3, 5)])
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(4 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(4, 5)])
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][0][(W - 1):(W / 2)], iota_data[0][0][0][((W / 2) - 1):0]}) : ({iota_data[0][0][0][(W - 1):(W / 2)], state_in[0][0][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][1][(W - 1):(W / 2)], iota_data[0][0][1][((W / 2) - 1):0]}) : ({iota_data[0][0][1][(W - 1):(W / 2)], state_in[0][0][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][2][(W - 1):(W / 2)], iota_data[0][0][2][((W / 2) - 1):0]}) : ({iota_data[0][0][2][(W - 1):(W / 2)], state_in[0][0][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][3][(W - 1):(W / 2)], iota_data[0][0][3][((W / 2) - 1):0]}) : ({iota_data[0][0][3][(W - 1):(W / 2)], state_in[0][0][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][4][(W - 1):(W / 2)], iota_data[0][0][4][((W / 2) - 1):0]}) : ({iota_data[0][0][4][(W - 1):(W / 2)], state_in[0][0][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][0][(W - 1):(W / 2)], iota_data[0][1][0][((W / 2) - 1):0]}) : ({iota_data[0][1][0][(W - 1):(W / 2)], state_in[0][1][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][1][(W - 1):(W / 2)], iota_data[0][1][1][((W / 2) - 1):0]}) : ({iota_data[0][1][1][(W - 1):(W / 2)], state_in[0][1][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][2][(W - 1):(W / 2)], iota_data[0][1][2][((W / 2) - 1):0]}) : ({iota_data[0][1][2][(W - 1):(W / 2)], state_in[0][1][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][3][(W - 1):(W / 2)], iota_data[0][1][3][((W / 2) - 1):0]}) : ({iota_data[0][1][3][(W - 1):(W / 2)], state_in[0][1][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][4][(W - 1):(W / 2)], iota_data[0][1][4][((W / 2) - 1):0]}) : ({iota_data[0][1][4][(W - 1):(W / 2)], state_in[0][1][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][0][(W - 1):(W / 2)], iota_data[0][2][0][((W / 2) - 1):0]}) : ({iota_data[0][2][0][(W - 1):(W / 2)], state_in[0][2][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][1][(W - 1):(W / 2)], iota_data[0][2][1][((W / 2) - 1):0]}) : ({iota_data[0][2][1][(W - 1):(W / 2)], state_in[0][2][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][2][(W - 1):(W / 2)], iota_data[0][2][2][((W / 2) - 1):0]}) : ({iota_data[0][2][2][(W - 1):(W / 2)], state_in[0][2][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][3][(W - 1):(W / 2)], iota_data[0][2][3][((W / 2) - 1):0]}) : ({iota_data[0][2][3][(W - 1):(W / 2)], state_in[0][2][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][4][(W - 1):(W / 2)], iota_data[0][2][4][((W / 2) - 1):0]}) : ({iota_data[0][2][4][(W - 1):(W / 2)], state_in[0][2][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][0][(W - 1):(W / 2)], iota_data[0][3][0][((W / 2) - 1):0]}) : ({iota_data[0][3][0][(W - 1):(W / 2)], state_in[0][3][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][1][(W - 1):(W / 2)], iota_data[0][3][1][((W / 2) - 1):0]}) : ({iota_data[0][3][1][(W - 1):(W / 2)], state_in[0][3][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][2][(W - 1):(W / 2)], iota_data[0][3][2][((W / 2) - 1):0]}) : ({iota_data[0][3][2][(W - 1):(W / 2)], state_in[0][3][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][3][(W - 1):(W / 2)], iota_data[0][3][3][((W / 2) - 1):0]}) : ({iota_data[0][3][3][(W - 1):(W / 2)], state_in[0][3][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][4][(W - 1):(W / 2)], iota_data[0][3][4][((W / 2) - 1):0]}) : ({iota_data[0][3][4][(W - 1):(W / 2)], state_in[0][3][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][0][(W - 1):(W / 2)], iota_data[0][4][0][((W / 2) - 1):0]}) : ({iota_data[0][4][0][(W - 1):(W / 2)], state_in[0][4][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][1][(W - 1):(W / 2)], iota_data[0][4][1][((W / 2) - 1):0]}) : ({iota_data[0][4][1][(W - 1):(W / 2)], state_in[0][4][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][2][(W - 1):(W / 2)], iota_data[0][4][2][((W / 2) - 1):0]}) : ({iota_data[0][4][2][(W - 1):(W / 2)], state_in[0][4][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][3][(W - 1):(W / 2)], iota_data[0][4][3][((W / 2) - 1):0]}) : ({iota_data[0][4][3][(W - 1):(W / 2)], state_in[0][4][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][4][(W - 1):(W / 2)], iota_data[0][4][4][((W / 2) - 1):0]}) : ({iota_data[0][4][4][(W - 1):(W / 2)], state_in[0][4][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][0][(W - 1):(W / 2)], iota_data[1][0][0][((W / 2) - 1):0]}) : ({iota_data[1][0][0][(W - 1):(W / 2)], state_in[1][0][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][1][(W - 1):(W / 2)], iota_data[1][0][1][((W / 2) - 1):0]}) : ({iota_data[1][0][1][(W - 1):(W / 2)], state_in[1][0][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][2][(W - 1):(W / 2)], iota_data[1][0][2][((W / 2) - 1):0]}) : ({iota_data[1][0][2][(W - 1):(W / 2)], state_in[1][0][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][3][(W - 1):(W / 2)], iota_data[1][0][3][((W / 2) - 1):0]}) : ({iota_data[1][0][3][(W - 1):(W / 2)], state_in[1][0][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][4][(W - 1):(W / 2)], iota_data[1][0][4][((W / 2) - 1):0]}) : ({iota_data[1][0][4][(W - 1):(W / 2)], state_in[1][0][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][0][(W - 1):(W / 2)], iota_data[1][1][0][((W / 2) - 1):0]}) : ({iota_data[1][1][0][(W - 1):(W / 2)], state_in[1][1][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][1][(W - 1):(W / 2)], iota_data[1][1][1][((W / 2) - 1):0]}) : ({iota_data[1][1][1][(W - 1):(W / 2)], state_in[1][1][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][2][(W - 1):(W / 2)], iota_data[1][1][2][((W / 2) - 1):0]}) : ({iota_data[1][1][2][(W - 1):(W / 2)], state_in[1][1][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][3][(W - 1):(W / 2)], iota_data[1][1][3][((W / 2) - 1):0]}) : ({iota_data[1][1][3][(W - 1):(W / 2)], state_in[1][1][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][4][(W - 1):(W / 2)], iota_data[1][1][4][((W / 2) - 1):0]}) : ({iota_data[1][1][4][(W - 1):(W / 2)], state_in[1][1][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][0][(W - 1):(W / 2)], iota_data[1][2][0][((W / 2) - 1):0]}) : ({iota_data[1][2][0][(W - 1):(W / 2)], state_in[1][2][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][1][(W - 1):(W / 2)], iota_data[1][2][1][((W / 2) - 1):0]}) : ({iota_data[1][2][1][(W - 1):(W / 2)], state_in[1][2][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][2][(W - 1):(W / 2)], iota_data[1][2][2][((W / 2) - 1):0]}) : ({iota_data[1][2][2][(W - 1):(W / 2)], state_in[1][2][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][3][(W - 1):(W / 2)], iota_data[1][2][3][((W / 2) - 1):0]}) : ({iota_data[1][2][3][(W - 1):(W / 2)], state_in[1][2][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][4][(W - 1):(W / 2)], iota_data[1][2][4][((W / 2) - 1):0]}) : ({iota_data[1][2][4][(W - 1):(W / 2)], state_in[1][2][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][0][(W - 1):(W / 2)], iota_data[1][3][0][((W / 2) - 1):0]}) : ({iota_data[1][3][0][(W - 1):(W / 2)], state_in[1][3][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][1][(W - 1):(W / 2)], iota_data[1][3][1][((W / 2) - 1):0]}) : ({iota_data[1][3][1][(W - 1):(W / 2)], state_in[1][3][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][2][(W - 1):(W / 2)], iota_data[1][3][2][((W / 2) - 1):0]}) : ({iota_data[1][3][2][(W - 1):(W / 2)], state_in[1][3][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][3][(W - 1):(W / 2)], iota_data[1][3][3][((W / 2) - 1):0]}) : ({iota_data[1][3][3][(W - 1):(W / 2)], state_in[1][3][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][4][(W - 1):(W / 2)], iota_data[1][3][4][((W / 2) - 1):0]}) : ({iota_data[1][3][4][(W - 1):(W / 2)], state_in[1][3][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][0][(W - 1):(W / 2)], iota_data[1][4][0][((W / 2) - 1):0]}) : ({iota_data[1][4][0][(W - 1):(W / 2)], state_in[1][4][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][1][(W - 1):(W / 2)], iota_data[1][4][1][((W / 2) - 1):0]}) : ({iota_data[1][4][1][(W - 1):(W / 2)], state_in[1][4][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][2][(W - 1):(W / 2)], iota_data[1][4][2][((W / 2) - 1):0]}) : ({iota_data[1][4][2][(W - 1):(W / 2)], state_in[1][4][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][3][(W - 1):(W / 2)], iota_data[1][4][3][((W / 2) - 1):0]}) : ({iota_data[1][4][3][(W - 1):(W / 2)], state_in[1][4][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][4][(W - 1):(W / 2)], iota_data[1][4][4][((W / 2) - 1):0]}) : ({iota_data[1][4][4][(W - 1):(W / 2)], state_in[1][4][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       389
 EXPRESSION (in == 0)
            ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       415
 EXPRESSION ((z == 0) ? ((W - 1)) : ((z - 1)))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       415
 SUB-EXPRESSION (z == 0)
                ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       416
 EXPRESSION (c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z])
             ----------1----------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T17
1	0	Covered	T2,T3,T17
1	1	Covered	T2,T3,T17

---

Branch Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
Branches		157	155	98.73
TERNARY	221	2	2	100.00
TERNARY	222	2	2	100.00
TERNARY	223	2	2	100.00
TERNARY	224	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	221	2	2	100.00
TERNARY	222	2	2	100.00
TERNARY	223	2	2	100.00
TERNARY	224	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	221	2	2	100.00
TERNARY	222	2	2	100.00
TERNARY	223	2	2	100.00
TERNARY	224	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	221	2	2	100.00
TERNARY	222	2	2	100.00
TERNARY	223	2	2	100.00
TERNARY	224	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	221	2	2	100.00
TERNARY	222	2	2	100.00
TERNARY	223	2	2	100.00
TERNARY	224	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	289	2	2	100.00
CASE	107	3	2	66.67
IF	389	2	2	100.00
TERNARY	415	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	107	case (phase_sel_i)

Branches:

-1-	Status	Tests
MuBi4False	Covered	T1,T2,T3
MuBi4True	Covered	T2,T3,T17
default	Not Covered

	LineNo.	Expression
-1-:	389	if ((in == 0))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	415	((z == 0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keccak_2share

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidL_A	933	933	0	0
ValidRound_A	933	933	0	0
ValidW_A	933	933	0	0
ValidWidth_A	933	933	0	0
gen_selperiod_chk.SelStayTwoCycleIfTrue_A	1474723140	53160998	0	0

ValidL_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

ValidRound_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

ValidW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

gen_selperiod_chk.SelStayTwoCycleIfTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	53160998	0	0
T2	15751	264	0	0
T3	362878	7512	0	0
T7	60114	2904	0	0
T8	321414	19608	0	0
T12	4078	0	0	0
T13	2702	24	0	0
T14	281236	175512	0	0
T17	195600	132624	0	0
T21	0	30480	0	0
T33	193415	132624	0	0
T34	202556	133008	0	0