Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	98.68	92.86		100.00	91.07	88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	94.30	98.68	92.86		100.00	91.07	88.89

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	98.68	92.86		100.00	91.07	88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.80	98.88	92.86	100.00	100.00	91.38	91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
gen_key_slicer[1].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	153	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	166	30	30	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	268	6	5	83.33
CONT_ASSIGN	287	1	1	100.00
ALWAYS	307	6	6	100.00
ALWAYS	338	6	6	100.00
ALWAYS	338	6	6	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
ALWAYS	420	6	6	100.00
CONT_ASSIGN	431	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
161	3	3
166	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
176	1	1
178	1	1
180	1	1
181	1	1
183	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
199	1	1
201	1	1
207	1	1
208	1	1
210	1	1
212	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
240	1	1
241	1	1
			MISSING_ELSE
251	1	1
252	1	1
253	1	1
254	1	1
258	1	1
260	1	1
265	1	1
268	1	1
269	1	1
270	1	1
271	0	1
272	1	1
274	1	1
			MISSING_ELSE
287	1	1
307	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
372	1	1
375	1	1
394	1	1
420	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
431	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Not Covered
1	0	Covered	T3,T7,T8

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T17
1	1	Not Covered

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	181	Covered	T3,T7,T8
StKmacFlush	208	Covered	T3,T7,T8
StKmacIdle	183	Covered	T1,T2,T3
StKmacMsg	194	Covered	T3,T7,T8
StTerminalError	241	Covered	T7,T12,T13

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	194	Covered	T3,T7,T8
StKey->StTerminalError	241	Covered	T75,T45,T84
StKmacFlush->StKmacIdle	218	Covered	T3,T7,T8
StKmacFlush->StTerminalError	241	Covered	T71,T72,T73
StKmacIdle->StKey	181	Covered	T3,T7,T8
StKmacIdle->StTerminalError	241	Covered	T7,T12,T13
StKmacMsg->StKmacFlush	208	Covered	T3,T7,T8
StKmacMsg->StTerminalError	241	Covered	T42,T46,T47

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	253	2	2	100.00
TERNARY	254	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	2	2	100.00
TERNARY	265	2	2	100.00
IF	161	2	2	100.00
CASE	178	10	10	100.00
IF	240	2	2	100.00
IF	268	4	3	75.00
CASE	307	6	5	83.33
CASE	420	6	5	83.33
CASE	338	6	5	83.33
CASE	338	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st)
-2-:	180	if ((kmac_en_i && start_i))
-3-:	193	if (sent_blocksize)
-4-:	207	if ((process_i || process_latched))
-5-:	217	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T3,T7,T8
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T3,T7,T8
StKey	-	0	-	-	Covered	T3,T7,T8
StKmacMsg	-	-	1	-	Covered	T3,T7,T8
StKmacMsg	-	-	0	-	Covered	T3,T7,T8
StKmacFlush	-	-	-	1	Covered	T3,T7,T8
StKmacFlush	-	-	-	0	Covered	T3,T7,T8
StTerminalError	-	-	-	-	Covered	T7,T12,T13
default	-	-	-	-	Covered	T28,T29,T32

	LineNo.	Expression
-1-:	240	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if ((process_i && (!process_o)))
-3-:	272	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T2,T3,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T2,T17,T7
Key256	Covered	T2,T3,T17
Key384	Covered	T17,T7,T33
Key512	Covered	T17,T7,T33
default	Not Covered

	LineNo.	Expression
-1-:	420	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T14,T34,T36
L256	Covered	T1,T2,T3
L384	Covered	T8,T14,T21
L512	Covered	T14,T36,T57
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T2,T17,T7
Key256	Covered	T2,T3,T17
Key384	Covered	T17,T7,T33
Key512	Covered	T17,T7,T33
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T2,T17,T7
Key256	Covered	T2,T3,T17
Key384	Covered	T17,T7,T33
Key512	Covered	T17,T7,T33
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	1474723140	5879285	0	0
KeyDataStableWhenValid_M	1474723140	268122105	0	0
KeyLengthStableWhenValid_M	1474723140	268122105	0	0
KmacEnStable_M	1474723140	20954	0	0
MaxKeyLenMatchToKey512_A	933	933	0	0
ModeStable_M	1474723140	32572	0	0
ProcessLatchedCleared_A	1474723140	0	0	0
StrengthStable_M	1474723140	39138	0	0
u_state_regs_A	1474723140	1474522125	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	5879285	0	0
T3	362878	1325	0	0
T7	60114	342	0	0
T8	321414	3373	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	72234	0	0
T17	195600	0	0	0
T18	0	25467	0	0
T21	177774	5820	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	6435	0	0
T56	0	109	0	0
T83	0	6348	0	0
T85	0	109	0	0

KeyDataStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	268122105	0	0
T3	362878	189573	0	0
T7	60114	17137	0	0
T8	321414	152132	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	190425	0	0
T17	195600	0	0	0
T18	0	625023	0	0
T21	177774	885270	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	319200	0	0
T56	0	15222	0	0
T83	0	107733	0	0
T85	0	9288	0	0

KeyLengthStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	268122105	0	0
T3	362878	189573	0	0
T7	60114	17137	0	0
T8	321414	152132	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	190425	0	0
T17	195600	0	0	0
T18	0	625023	0	0
T21	177774	885270	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	319200	0	0
T56	0	15222	0	0
T83	0	107733	0	0
T85	0	9288	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	20954	0	0
T3	362878	14	0	0
T7	60114	6	0	0
T8	321414	58	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	243	0	0
T17	195600	0	0	0
T18	0	51	0	0
T21	177774	91	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	58	0	0
T56	0	1	0	0
T83	0	43	0	0
T85	0	1	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	32572	0	0
T2	15751	3	0	0
T3	362878	15	0	0
T7	60114	14	0	0
T8	321414	102	0	0
T12	4078	1	0	0
T13	2702	1	0	0
T14	281236	363	0	0
T17	195600	0	0	0
T21	0	197	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T35	0	1	0	0
T36	0	73	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	39138	0	0
T1	1477	1	0	0
T2	15751	4	0	0
T3	362878	20	0	0
T7	60114	14	0	0
T8	321414	90	0	0
T12	4078	2	0	0
T13	2702	2	0	0
T14	281236	393	0	0
T17	195600	2	0	0
T33	193415	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

Line Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	153	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	166	30	30	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	268	6	5	83.33
CONT_ASSIGN	287	1	1	100.00
ALWAYS	307	6	6	100.00
ALWAYS	338	6	6	100.00
ALWAYS	338	6	6	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
ALWAYS	420	6	6	100.00
CONT_ASSIGN	431	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
161	3	3
166	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
176	1	1
178	1	1
180	1	1
181	1	1
183	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
199	1	1
201	1	1
207	1	1
208	1	1
210	1	1
212	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
240	1	1
241	1	1
			MISSING_ELSE
251	1	1
252	1	1
253	1	1
254	1	1
258	1	1
260	1	1
265	1	1
268	1	1
269	1	1
270	1	1
271	0	1
272	1	1
274	1	1
			MISSING_ELSE
287	1	1
307	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
372	1	1
375	1	1
394	1	1
420	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
431	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Not Covered
1	0	Covered	T3,T7,T8

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T17
1	1	Not Covered

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

---

FSM Coverage for Instance : tb.dut.u_kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	181	Covered	T3,T7,T8
StKmacFlush	208	Covered	T3,T7,T8
StKmacIdle	183	Covered	T1,T2,T3
StKmacMsg	194	Covered	T3,T7,T8
StTerminalError	241	Covered	T7,T12,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
StKey->StKmacMsg	194	Covered	T3,T7,T8
StKey->StTerminalError	241	Covered	T75,T45,T84
StKmacFlush->StKmacIdle	218	Covered	T3,T7,T8
StKmacFlush->StTerminalError	241	Excluded	T71,T72,T73	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StKmacIdle->StKey	181	Covered	T3,T7,T8
StKmacIdle->StTerminalError	241	Covered	T7,T12,T13
StKmacMsg->StKmacFlush	208	Covered	T3,T7,T8
StKmacMsg->StTerminalError	241	Covered	T42,T46,T47

---

Branch Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	253	2	2	100.00
TERNARY	254	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	2	2	100.00
TERNARY	265	2	2	100.00
IF	161	2	2	100.00
CASE	178	10	10	100.00
IF	240	2	2	100.00
IF	268	4	3	75.00
CASE	307	6	5	83.33
CASE	420	6	5	83.33
CASE	338	6	5	83.33
CASE	338	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st)
-2-:	180	if ((kmac_en_i && start_i))
-3-:	193	if (sent_blocksize)
-4-:	207	if ((process_i || process_latched))
-5-:	217	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T3,T7,T8
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T3,T7,T8
StKey	-	0	-	-	Covered	T3,T7,T8
StKmacMsg	-	-	1	-	Covered	T3,T7,T8
StKmacMsg	-	-	0	-	Covered	T3,T7,T8
StKmacFlush	-	-	-	1	Covered	T3,T7,T8
StKmacFlush	-	-	-	0	Covered	T3,T7,T8
StTerminalError	-	-	-	-	Covered	T7,T12,T13
default	-	-	-	-	Covered	T28,T29,T32

	LineNo.	Expression
-1-:	240	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if ((process_i && (!process_o)))
-3-:	272	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T2,T3,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T2,T17,T7
Key256	Covered	T2,T3,T17
Key384	Covered	T17,T7,T33
Key512	Covered	T17,T7,T33
default	Not Covered

	LineNo.	Expression
-1-:	420	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T14,T34,T36
L256	Covered	T1,T2,T3
L384	Covered	T8,T14,T21
L512	Covered	T14,T36,T57
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T2,T17,T7
Key256	Covered	T2,T3,T17
Key384	Covered	T17,T7,T33
Key512	Covered	T17,T7,T33
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T2,T17,T7
Key256	Covered	T2,T3,T17
Key384	Covered	T17,T7,T33
Key512	Covered	T17,T7,T33
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	1474723140	5879285	0	0
KeyDataStableWhenValid_M	1474723140	268122105	0	0
KeyLengthStableWhenValid_M	1474723140	268122105	0	0
KmacEnStable_M	1474723140	20954	0	0
MaxKeyLenMatchToKey512_A	933	933	0	0
ModeStable_M	1474723140	32572	0	0
ProcessLatchedCleared_A	1474723140	0	0	0
StrengthStable_M	1474723140	39138	0	0
u_state_regs_A	1474723140	1474522125	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	5879285	0	0
T3	362878	1325	0	0
T7	60114	342	0	0
T8	321414	3373	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	72234	0	0
T17	195600	0	0	0
T18	0	25467	0	0
T21	177774	5820	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	6435	0	0
T56	0	109	0	0
T83	0	6348	0	0
T85	0	109	0	0

KeyDataStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	268122105	0	0
T3	362878	189573	0	0
T7	60114	17137	0	0
T8	321414	152132	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	190425	0	0
T17	195600	0	0	0
T18	0	625023	0	0
T21	177774	885270	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	319200	0	0
T56	0	15222	0	0
T83	0	107733	0	0
T85	0	9288	0	0

KeyLengthStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	268122105	0	0
T3	362878	189573	0	0
T7	60114	17137	0	0
T8	321414	152132	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	190425	0	0
T17	195600	0	0	0
T18	0	625023	0	0
T21	177774	885270	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	319200	0	0
T56	0	15222	0	0
T83	0	107733	0	0
T85	0	9288	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	20954	0	0
T3	362878	14	0	0
T7	60114	6	0	0
T8	321414	58	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	243	0	0
T17	195600	0	0	0
T18	0	51	0	0
T21	177774	91	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	58	0	0
T56	0	1	0	0
T83	0	43	0	0
T85	0	1	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	32572	0	0
T2	15751	3	0	0
T3	362878	15	0	0
T7	60114	14	0	0
T8	321414	102	0	0
T12	4078	1	0	0
T13	2702	1	0	0
T14	281236	363	0	0
T17	195600	0	0	0
T21	0	197	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T35	0	1	0	0
T36	0	73	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	39138	0	0
T1	1477	1	0	0
T2	15751	4	0	0
T3	362878	20	0	0
T7	60114	14	0	0
T8	321414	90	0	0
T12	4078	2	0	0
T13	2702	2	0	0
T14	281236	393	0	0
T17	195600	2	0	0
T33	193415	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0