Unified Coverage Report :: Module :: prim_slicer

Module : prim_slicer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer	100.00	100.00					100.00
tb.dut.u_sha3.u_pad.u_prefix_slicer	100.00	100.00					100.00
tb.dut.u_staterd.gen_slicer[0].u_state_slice	100.00	100.00					100.00
tb.dut.u_staterd.gen_slicer[1].u_state_slice	100.00	100.00					100.00

---

Module Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.30	98.68	92.86		100.00	91.07	88.89	u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.30	98.68	92.86		100.00	91.07	88.89	u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	99.41	88.37		100.00	95.70	100.00	u_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.00	100.00	70.00			100.00		u_staterd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.gen_slicer[1].u_state_slice

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.00	100.00	70.00			100.00		u_staterd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
27	1	1

---

Assert Coverage for Module : prim_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	4665	4665	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4665	4665	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T7	5	5	0	0
T8	5	5	0	0
T12	5	5	0	0
T13	5	5	0	0
T14	5	5	0	0
T17	5	5	0	0
T33	5	5	0	0

Line Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
27	1	1

---

Assert Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	933	933	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

Line Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
27	1	1

---

Assert Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	933	933	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
27	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	933	933	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

Line Coverage for Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
27	1	1

---

Assert Coverage for Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	933	933	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

Line Coverage for Instance : tb.dut.u_staterd.gen_slicer[1].u_state_slice

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
27	1	1

---

Assert Coverage for Instance : tb.dut.u_staterd.gen_slicer[1].u_state_slice

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	933	933	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0