Unified Coverage Report :: Module :: prim_dom_and_2share

Module : prim_dom_and_2share

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom	0.00	0.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom	0.00	0.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom	0.00	0.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom	0.00	0.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom	0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	0.00	0.00				0.00
u_prim_flop_t01	0.00	0.00				0.00
u_prim_xor_q01	0.00	0.00
u_prim_xor_t01	0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	0.00	0.00				0.00
u_prim_flop_t01	0.00	0.00				0.00
u_prim_xor_q01	0.00	0.00
u_prim_xor_t01	0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	0.00	0.00				0.00
u_prim_flop_t01	0.00	0.00				0.00
u_prim_xor_q01	0.00	0.00
u_prim_xor_t01	0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	0.00	0.00				0.00
u_prim_flop_t01	0.00	0.00				0.00
u_prim_xor_q01	0.00	0.00
u_prim_xor_t01	0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	0.00	0.00				0.00
u_prim_flop_t01	0.00	0.00				0.00
u_prim_xor_q01	0.00	0.00
u_prim_xor_t01	0.00	0.00

Line Coverage for Module : prim_dom_and_2share

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	142	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	1
57	0	1
60	0	1
61	0	1
110	0	1
111	0	1
142	0	1

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	142	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	1
57	0	1
60	0	1
61	0	1
110	0	1
111	0	1
142	0	1

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	142	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	1
57	0	1
60	0	1
61	0	1
110	0	1
111	0	1
142	0	1

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	142	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	1
57	0	1
60	0	1
61	0	1
110	0	1
111	0	1
142	0	1

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	142	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	1
57	0	1
60	0	1
61	0	1
110	0	1
111	0	1
142	0	1

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	142	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	1
57	0	1
60	0	1
61	0	1
110	0	1
111	0	1
142	0	1