Unified Coverage Report :: Module :: keccak_2share

Module : keccak_2share

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_2share_chi.g_chi_w[0].u_dom	0.00	0.00				0.00
g_2share_chi.g_chi_w[1].u_dom	0.00	0.00				0.00
g_2share_chi.g_chi_w[2].u_dom	0.00	0.00				0.00
g_2share_chi.g_chi_w[3].u_dom	0.00	0.00				0.00
g_2share_chi.g_chi_w[4].u_dom	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
TOTAL		297	0	0.00
CONT_ASSIGN	98	1	0	0.00
CONT_ASSIGN	98	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	104	1	0	0.00
ALWAYS	107	3	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
CONT_ASSIGN	166	1	0	0.00
CONT_ASSIGN	166	1	0	0.00
CONT_ASSIGN	166	1	0	0.00
CONT_ASSIGN	166	1	0	0.00
CONT_ASSIGN	166	1	0	0.00
CONT_ASSIGN	168	1	0	0.00
CONT_ASSIGN	168	1	0	0.00
CONT_ASSIGN	168	1	0	0.00
CONT_ASSIGN	168	1	0	0.00
CONT_ASSIGN	168	1	0	0.00
CONT_ASSIGN	169	1	0	0.00
CONT_ASSIGN	169	1	0	0.00
CONT_ASSIGN	169	1	0	0.00
CONT_ASSIGN	169	1	0	0.00
CONT_ASSIGN	169	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	181	1	0	0.00
CONT_ASSIGN	181	1	0	0.00
CONT_ASSIGN	181	1	0	0.00
CONT_ASSIGN	181	1	0	0.00
CONT_ASSIGN	181	1	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
CONT_ASSIGN	221	1	0	0.00
CONT_ASSIGN	221	1	0	0.00
CONT_ASSIGN	221	1	0	0.00
CONT_ASSIGN	221	1	0	0.00
CONT_ASSIGN	221	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	271	1	0	0.00
CONT_ASSIGN	271	1	0	0.00
CONT_ASSIGN	271	1	0	0.00
CONT_ASSIGN	271	1	0	0.00
CONT_ASSIGN	271	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	273	1	0	0.00
CONT_ASSIGN	273	1	0	0.00
CONT_ASSIGN	273	1	0	0.00
CONT_ASSIGN	273	1	0	0.00
CONT_ASSIGN	273	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	278	1	0	0.00
CONT_ASSIGN	278	1	0	0.00
CONT_ASSIGN	278	1	0	0.00
CONT_ASSIGN	278	1	0	0.00
CONT_ASSIGN	278	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	314	1	0	0.00
CONT_ASSIGN	314	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	322	1	0	0.00
CONT_ASSIGN	322	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
ROUTINE	363	0	0
ROUTINE	363	5	0	0.00
ROUTINE	376	0	0
ROUTINE	376	5	0	0.00
ROUTINE	389	4	0	0.00
ROUTINE	409	0	0
ROUTINE	409	10	0	0.00
ROUTINE	478	0	0
ROUTINE	478	4	0	0.00
ROUTINE	547	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
98	0	2
99	0	2
103	0	1
104	0	1
107	0	1
108	0	1
109	0	1
125	0	2
129	0	2
136	0	1
140	0	1
141	0	1
165	0	5
166	0	5
168	0	5
169	0	5
176	0	5
181	0	5
187	0	5
192	0	5
198	0	5
203	0	5
209	0	5
214	0	5
221	0	5
222	0	5
223	0	5
224	0	5
231	0	5
265	0	5
266	0	5
267	0	5
268	0	5
269	0	5
271	0	5
272	0	5
273	0	5
274	0	5
275	0	5
278	0	5
279	0	5
286	0	25
289	0	25
314	0	2
315	0	2
322	0	2
324	0	48
344	0	1
363	0	1
364	0	1
365	0	1
366	0	1
370	0	1
376	0	1
377	0	1
378	0	1
379	0	1
383	0	1
389	0	1
390	0	1
392	0	1
394	0	1
409	0	1
410	0	1
412	0	1
413	0	1
415	0	1
416	0	1
419	0	1
420	0	1
421	0	1
424	0	1
478	0	1
479	0	1
480	0	1
483	0	1
547	0	1
548	0	1
550	0	1

---

Cond Coverage for Module : keccak_2share

	Total	Covered	Percent
Conditions	160	0	0.00
Logical	160	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[0].a0_l : g_2share_chi.g_chi_w[0].a0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[1].a0_l : g_2share_chi.g_chi_w[1].a0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[2].a0_l : g_2share_chi.g_chi_w[2].a0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[3].a0_l : g_2share_chi.g_chi_w[3].a0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       221
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[4].a0_l : g_2share_chi.g_chi_w[4].a0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[0].a1_l : g_2share_chi.g_chi_w[0].a1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[1].a1_l : g_2share_chi.g_chi_w[1].a1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[2].a1_l : g_2share_chi.g_chi_w[2].a1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[3].a1_l : g_2share_chi.g_chi_w[3].a1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       222
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[4].a1_l : g_2share_chi.g_chi_w[4].a1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[0].b0_l : g_2share_chi.g_chi_w[0].b0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[1].b0_l : g_2share_chi.g_chi_w[1].b0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[2].b0_l : g_2share_chi.g_chi_w[2].b0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[3].b0_l : g_2share_chi.g_chi_w[3].b0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       223
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[4].b0_l : g_2share_chi.g_chi_w[4].b0_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[0].b1_l : g_2share_chi.g_chi_w[0].b1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[1].b1_l : g_2share_chi.g_chi_w[1].b1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[2].b1_l : g_2share_chi.g_chi_w[2].b1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[3].b1_l : g_2share_chi.g_chi_w[3].b1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 EXPRESSION (dom_in_low_i ? g_2share_chi.g_chi_w[4].b1_l : g_2share_chi.g_chi_w[4].b1_h)
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(0 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(0, 5)])
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(1 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(1, 5)])
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(2 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(2, 5)])
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(3 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(3, 5)])
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (dom_in_rand_ext_i ? rand_i[(4 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(4, 5)])
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][0][(W - 1):(W / 2)], iota_data[0][0][0][((W / 2) - 1):0]}) : ({iota_data[0][0][0][(W - 1):(W / 2)], state_in[0][0][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][1][(W - 1):(W / 2)], iota_data[0][0][1][((W / 2) - 1):0]}) : ({iota_data[0][0][1][(W - 1):(W / 2)], state_in[0][0][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][2][(W - 1):(W / 2)], iota_data[0][0][2][((W / 2) - 1):0]}) : ({iota_data[0][0][2][(W - 1):(W / 2)], state_in[0][0][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][3][(W - 1):(W / 2)], iota_data[0][0][3][((W / 2) - 1):0]}) : ({iota_data[0][0][3][(W - 1):(W / 2)], state_in[0][0][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][0][4][(W - 1):(W / 2)], iota_data[0][0][4][((W / 2) - 1):0]}) : ({iota_data[0][0][4][(W - 1):(W / 2)], state_in[0][0][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][0][(W - 1):(W / 2)], iota_data[0][1][0][((W / 2) - 1):0]}) : ({iota_data[0][1][0][(W - 1):(W / 2)], state_in[0][1][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][1][(W - 1):(W / 2)], iota_data[0][1][1][((W / 2) - 1):0]}) : ({iota_data[0][1][1][(W - 1):(W / 2)], state_in[0][1][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][2][(W - 1):(W / 2)], iota_data[0][1][2][((W / 2) - 1):0]}) : ({iota_data[0][1][2][(W - 1):(W / 2)], state_in[0][1][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][3][(W - 1):(W / 2)], iota_data[0][1][3][((W / 2) - 1):0]}) : ({iota_data[0][1][3][(W - 1):(W / 2)], state_in[0][1][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][1][4][(W - 1):(W / 2)], iota_data[0][1][4][((W / 2) - 1):0]}) : ({iota_data[0][1][4][(W - 1):(W / 2)], state_in[0][1][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][0][(W - 1):(W / 2)], iota_data[0][2][0][((W / 2) - 1):0]}) : ({iota_data[0][2][0][(W - 1):(W / 2)], state_in[0][2][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][1][(W - 1):(W / 2)], iota_data[0][2][1][((W / 2) - 1):0]}) : ({iota_data[0][2][1][(W - 1):(W / 2)], state_in[0][2][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][2][(W - 1):(W / 2)], iota_data[0][2][2][((W / 2) - 1):0]}) : ({iota_data[0][2][2][(W - 1):(W / 2)], state_in[0][2][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][3][(W - 1):(W / 2)], iota_data[0][2][3][((W / 2) - 1):0]}) : ({iota_data[0][2][3][(W - 1):(W / 2)], state_in[0][2][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][2][4][(W - 1):(W / 2)], iota_data[0][2][4][((W / 2) - 1):0]}) : ({iota_data[0][2][4][(W - 1):(W / 2)], state_in[0][2][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][0][(W - 1):(W / 2)], iota_data[0][3][0][((W / 2) - 1):0]}) : ({iota_data[0][3][0][(W - 1):(W / 2)], state_in[0][3][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][1][(W - 1):(W / 2)], iota_data[0][3][1][((W / 2) - 1):0]}) : ({iota_data[0][3][1][(W - 1):(W / 2)], state_in[0][3][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][2][(W - 1):(W / 2)], iota_data[0][3][2][((W / 2) - 1):0]}) : ({iota_data[0][3][2][(W - 1):(W / 2)], state_in[0][3][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][3][(W - 1):(W / 2)], iota_data[0][3][3][((W / 2) - 1):0]}) : ({iota_data[0][3][3][(W - 1):(W / 2)], state_in[0][3][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][3][4][(W - 1):(W / 2)], iota_data[0][3][4][((W / 2) - 1):0]}) : ({iota_data[0][3][4][(W - 1):(W / 2)], state_in[0][3][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][0][(W - 1):(W / 2)], iota_data[0][4][0][((W / 2) - 1):0]}) : ({iota_data[0][4][0][(W - 1):(W / 2)], state_in[0][4][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][1][(W - 1):(W / 2)], iota_data[0][4][1][((W / 2) - 1):0]}) : ({iota_data[0][4][1][(W - 1):(W / 2)], state_in[0][4][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][2][(W - 1):(W / 2)], iota_data[0][4][2][((W / 2) - 1):0]}) : ({iota_data[0][4][2][(W - 1):(W / 2)], state_in[0][4][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][3][(W - 1):(W / 2)], iota_data[0][4][3][((W / 2) - 1):0]}) : ({iota_data[0][4][3][(W - 1):(W / 2)], state_in[0][4][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[0][4][4][(W - 1):(W / 2)], iota_data[0][4][4][((W / 2) - 1):0]}) : ({iota_data[0][4][4][(W - 1):(W / 2)], state_in[0][4][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][0][(W - 1):(W / 2)], iota_data[1][0][0][((W / 2) - 1):0]}) : ({iota_data[1][0][0][(W - 1):(W / 2)], state_in[1][0][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][1][(W - 1):(W / 2)], iota_data[1][0][1][((W / 2) - 1):0]}) : ({iota_data[1][0][1][(W - 1):(W / 2)], state_in[1][0][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][2][(W - 1):(W / 2)], iota_data[1][0][2][((W / 2) - 1):0]}) : ({iota_data[1][0][2][(W - 1):(W / 2)], state_in[1][0][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][3][(W - 1):(W / 2)], iota_data[1][0][3][((W / 2) - 1):0]}) : ({iota_data[1][0][3][(W - 1):(W / 2)], state_in[1][0][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][0][4][(W - 1):(W / 2)], iota_data[1][0][4][((W / 2) - 1):0]}) : ({iota_data[1][0][4][(W - 1):(W / 2)], state_in[1][0][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][0][(W - 1):(W / 2)], iota_data[1][1][0][((W / 2) - 1):0]}) : ({iota_data[1][1][0][(W - 1):(W / 2)], state_in[1][1][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][1][(W - 1):(W / 2)], iota_data[1][1][1][((W / 2) - 1):0]}) : ({iota_data[1][1][1][(W - 1):(W / 2)], state_in[1][1][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][2][(W - 1):(W / 2)], iota_data[1][1][2][((W / 2) - 1):0]}) : ({iota_data[1][1][2][(W - 1):(W / 2)], state_in[1][1][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][3][(W - 1):(W / 2)], iota_data[1][1][3][((W / 2) - 1):0]}) : ({iota_data[1][1][3][(W - 1):(W / 2)], state_in[1][1][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][1][4][(W - 1):(W / 2)], iota_data[1][1][4][((W / 2) - 1):0]}) : ({iota_data[1][1][4][(W - 1):(W / 2)], state_in[1][1][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][0][(W - 1):(W / 2)], iota_data[1][2][0][((W / 2) - 1):0]}) : ({iota_data[1][2][0][(W - 1):(W / 2)], state_in[1][2][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][1][(W - 1):(W / 2)], iota_data[1][2][1][((W / 2) - 1):0]}) : ({iota_data[1][2][1][(W - 1):(W / 2)], state_in[1][2][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][2][(W - 1):(W / 2)], iota_data[1][2][2][((W / 2) - 1):0]}) : ({iota_data[1][2][2][(W - 1):(W / 2)], state_in[1][2][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][3][(W - 1):(W / 2)], iota_data[1][2][3][((W / 2) - 1):0]}) : ({iota_data[1][2][3][(W - 1):(W / 2)], state_in[1][2][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][2][4][(W - 1):(W / 2)], iota_data[1][2][4][((W / 2) - 1):0]}) : ({iota_data[1][2][4][(W - 1):(W / 2)], state_in[1][2][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][0][(W - 1):(W / 2)], iota_data[1][3][0][((W / 2) - 1):0]}) : ({iota_data[1][3][0][(W - 1):(W / 2)], state_in[1][3][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][1][(W - 1):(W / 2)], iota_data[1][3][1][((W / 2) - 1):0]}) : ({iota_data[1][3][1][(W - 1):(W / 2)], state_in[1][3][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][2][(W - 1):(W / 2)], iota_data[1][3][2][((W / 2) - 1):0]}) : ({iota_data[1][3][2][(W - 1):(W / 2)], state_in[1][3][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][3][(W - 1):(W / 2)], iota_data[1][3][3][((W / 2) - 1):0]}) : ({iota_data[1][3][3][(W - 1):(W / 2)], state_in[1][3][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][3][4][(W - 1):(W / 2)], iota_data[1][3][4][((W / 2) - 1):0]}) : ({iota_data[1][3][4][(W - 1):(W / 2)], state_in[1][3][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][0][(W - 1):(W / 2)], iota_data[1][4][0][((W / 2) - 1):0]}) : ({iota_data[1][4][0][(W - 1):(W / 2)], state_in[1][4][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][1][(W - 1):(W / 2)], iota_data[1][4][1][((W / 2) - 1):0]}) : ({iota_data[1][4][1][(W - 1):(W / 2)], state_in[1][4][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][2][(W - 1):(W / 2)], iota_data[1][4][2][((W / 2) - 1):0]}) : ({iota_data[1][4][2][(W - 1):(W / 2)], state_in[1][4][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][3][(W - 1):(W / 2)], iota_data[1][4][3][((W / 2) - 1):0]}) : ({iota_data[1][4][3][(W - 1):(W / 2)], state_in[1][4][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION 
 Number  Term
      1  dom_out_low_i ? ({state_in[1][4][4][(W - 1):(W / 2)], iota_data[1][4][4][((W / 2) - 1):0]}) : ({iota_data[1][4][4][(W - 1):(W / 2)], state_in[1][4][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       389
 EXPRESSION (in == 0)
            ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       415
 EXPRESSION ((z == 0) ? ((W - 1)) : ((z - 1)))
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       415
 SUB-EXPRESSION (z == 0)
                ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       416
 EXPRESSION (c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z])
             ----------1----------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
Branches		157	0	0.00
TERNARY	221	2	0	0.00
TERNARY	222	2	0	0.00
TERNARY	223	2	0	0.00
TERNARY	224	2	0	0.00
TERNARY	231	2	0	0.00
TERNARY	221	2	0	0.00
TERNARY	222	2	0	0.00
TERNARY	223	2	0	0.00
TERNARY	224	2	0	0.00
TERNARY	231	2	0	0.00
TERNARY	221	2	0	0.00
TERNARY	222	2	0	0.00
TERNARY	223	2	0	0.00
TERNARY	224	2	0	0.00
TERNARY	231	2	0	0.00
TERNARY	221	2	0	0.00
TERNARY	222	2	0	0.00
TERNARY	223	2	0	0.00
TERNARY	224	2	0	0.00
TERNARY	231	2	0	0.00
TERNARY	221	2	0	0.00
TERNARY	222	2	0	0.00
TERNARY	223	2	0	0.00
TERNARY	224	2	0	0.00
TERNARY	231	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	289	2	0	0.00
CASE	107	3	0	0.00
IF	389	2	0	0.00
TERNARY	415	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	221	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	222	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	223	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	224	(dom_in_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	231	(dom_in_rand_ext_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	289	(dom_out_low_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	107	case (phase_sel_i)

Branches:

-1-	Status	Tests
MuBi4False	Not Covered
MuBi4True	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	389	if ((in == 0))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	415	((z == 0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered