Unified Coverage Report :: Module :: keccak_round

Module : keccak_round

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_keccak

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak_p	0.00	0.00	0.00			0.00
u_prim_sec_anchor_buf	0.00	0.00
u_round_count	0.00			0.00
u_state_regs	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
TOTAL		110	0	0.00
CONT_ASSIGN	177	0	0
ALWAYS	180	3	0	0.00
ALWAYS	186	70	0	0.00
CONT_ASSIGN	407	1	0	0.00
ALWAYS	411	7	0	0.00
ALWAYS	424	3	0	0.00
CONT_ASSIGN	450	1	0	0.00
ALWAYS	468	6	0	0.00
CONT_ASSIGN	477	1	0	0.00
ALWAYS	485	7	0	0.00
ALWAYS	507	4	0	0.00
CONT_ASSIGN	518	1	0	0.00
CONT_ASSIGN	548	1	0	0.00
CONT_ASSIGN	549	1	0	0.00
CONT_ASSIGN	551	1	0	0.00
ALWAYS	575	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
177		unreachable
180	0	3
186	0	1
188	0	1
189	0	1
190	0	1
192	0	1
193	0	1
195	0	1
196	0	1
198	0	1
199	0	1
200	0	1
201	0	1
202	0	1
204	0	1
206	0	1
208	0	1
210	0	1
212	0	1
214	0	1
215	0	1
216	0	1
221	0	1
223	0	1
224	0	1
226	0	1
229	0	1
230	0	1
231	0	1
233		unreachable
235	0	1
241	0	1
243	0	1
244		unreachable
246		unreachable
247		unreachable
249	0	1
251	0	1
260	0	1
261	0	1
272	0	1
273	0	1
274	0	1
275	0	1
278	0	1
281	0	1
282	0	1
284	0	1
292	0	1
293	0	1
301	0	1
304	0	1
307	0	1
308	0	1
317	0	1
318	0	1
327	0	1
333	0	1
336	0	1
339	0	1
342	0	1
343	0	1
352	0	1
353	0	1
361	0	1
363	0	1
365		unreachable
367		unreachable
368		unreachable
371	0	1
373	0	1
376	0	1
377	0	1
382	0	1
387	0	1
388	0	1
400	0	1
401	0	1
			==> MISSING_ELSE
407	0	1
411	0	1
412	0	1
413	0	1
414	0	1
416	0	1
417	0	1
418	0	1
424	0	1
425	0	1
427	0	1
450	0	1
468	0	1
469	0	1
470	0	1
471	0	1
472	0	1
473	0	1
			==> MISSING_ELSE
477	0	1
485	0	1
486	0	1
487	0	1
488	0	1
492	0	1
493	0	1
496	0	1
			==> MISSING_ELSE
507	0	1
509	0	1
511	0	1
513	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
518	0	1
548	0	1
549	0	1
551	0	1
575	0	1
576	0	1
578	0	1

---

Cond Coverage for Module : keccak_round

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       177
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       224
 EXPRESSION (EnMasking && run_i)
             ----1----    --2--

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Not Covered

 LINE       272
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       450
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       450
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       492
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : keccak_round

Summary for FSM :: keccak_st

	Total	Covered	Percent
States	8	0	0.00	(Not included in score)
Transitions	15	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: keccak_st

---

states	Line No.	Covered	Tests
KeccakStActive	233	Not Covered
KeccakStError	382	Not Covered
KeccakStIdle	212	Not Covered
KeccakStPhase1	226	Not Covered
KeccakStPhase2Cycle1	273	Not Covered
KeccakStPhase2Cycle2	304	Not Covered
KeccakStPhase2Cycle3	339	Not Covered
KeccakStTerminalError	401	Not Covered

transitions	Line No.	Covered	Tests
KeccakStActive->KeccakStIdle	244	Not Covered
KeccakStActive->KeccakStTerminalError	401	Not Covered
KeccakStError->KeccakStTerminalError	401	Not Covered
KeccakStIdle->KeccakStActive	233	Not Covered
KeccakStIdle->KeccakStPhase1	226	Not Covered
KeccakStIdle->KeccakStTerminalError	401	Not Covered
KeccakStPhase1->KeccakStPhase2Cycle1	273	Not Covered
KeccakStPhase1->KeccakStTerminalError	401	Not Covered
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2	304	Not Covered
KeccakStPhase2Cycle1->KeccakStTerminalError	401	Not Covered
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3	339	Not Covered
KeccakStPhase2Cycle2->KeccakStTerminalError	401	Not Covered
KeccakStPhase2Cycle3->KeccakStIdle	365	Not Covered
KeccakStPhase2Cycle3->KeccakStPhase1	371	Not Covered
KeccakStPhase2Cycle3->KeccakStTerminalError	401	Not Covered

---

Branch Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
Branches		34	0	0.00
TERNARY	450	2	0	0.00
IF	180	2	0	0.00
CASE	208	13	0	0.00
IF	400	2	0	0.00
IF	468	4	0	0.00
IF	486	2	0	0.00
IF	509	3	0	0.00
IF	575	2	0	0.00
IF	411	2	0	0.00
IF	424	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	450	((keccak_st == KeccakStIdle)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	180	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	208	case (keccak_st)
-2-:	210	if (valid_i)
-3-:	216	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))
-4-:	224	if ((EnMasking && run_i))
-5-:	231	if (((!EnMasking) && run_i))
-6-:	243	if (rnd_eq_end)
-7-:	272	if ((rand_early_i || rand_valid_i))
-8-:	363	if (rnd_eq_end)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
KeccakStIdle	1	-	-	-	-	-	-	Not Covered
KeccakStIdle	0	1	-	-	-	-	-	Not Covered
KeccakStIdle	0	0	1	-	-	-	-	Not Covered
KeccakStIdle	0	0	0	1	-	-	-	Unreachable
KeccakStIdle	0	0	0	0	-	-	-	Not Covered
KeccakStActive	-	-	-	-	1	-	-	Unreachable
KeccakStActive	-	-	-	-	0	-	-	Not Covered
KeccakStPhase1	-	-	-	-	-	1	-	Not Covered
KeccakStPhase1	-	-	-	-	-	0	-	Not Covered
KeccakStPhase2Cycle1	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle3	-	-	-	-	-	-	1	Unreachable
KeccakStPhase2Cycle3	-	-	-	-	-	-	0	Not Covered
KeccakStError	-	-	-	-	-	-	-	Not Covered
KeccakStTerminalError	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	400	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	468	if ((!rst_n))
-2-:	470	if (rst_storage)
-3-:	472	if (update_storage)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	if (xor_message)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	509	if (rst_storage)
-2-:	511	if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	575	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	411	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	424	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered