Unified Coverage Report :: Module :: prim_slicer

Module : prim_slicer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer	0.00	0.00
tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer	0.00	0.00
tb.dut.u_sha3.u_pad.u_prefix_slicer	0.00	0.00
tb.dut.u_staterd.gen_slicer[0].u_state_slice	0.00	0.00
tb.dut.u_staterd.gen_slicer[1].u_state_slice	0.00	0.00

---

Module Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_staterd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.gen_slicer[1].u_state_slice

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_staterd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	27	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
27	0	1

Line Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	27	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
27	0	1

Line Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	27	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
27	0	1

Line Coverage for Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	27	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
27	0	1

Line Coverage for Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	27	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
27	0	1

Line Coverage for Instance : tb.dut.u_staterd.gen_slicer[1].u_state_slice

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	27	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
27	0	1