Module Definition
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Module : prim_trivium
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_entropy.u_entropy.u_prim_trivium 0.00 0.00 0.00 0.00


Module Instance : tb.dut.gen_entropy.u_entropy.u_prim_trivium

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 0.00 gen_entropy.u_entropy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_trivium
Line No.TotalCoveredPercent
TOTAL2800.00
CONT_ASSIGN119100.00
CONT_ASSIGN120100.00
CONT_ASSIGN121100.00
CONT_ASSIGN122100.00
ALWAYS131400.00
ALWAYS170400.00
CONT_ASSIGN188100.00
CONT_ASSIGN189100.00
ALWAYS194300.00
CONT_ASSIGN202100.00
ALWAYS204300.00
CONT_ASSIGN210100.00
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
ALWAYS288300.00
CONT_ASSIGN296100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' or '../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
119 0 1
120 0 1
121 0 1
122 0 1
131 0 1
132 0 1
133 0 1
134 0 1
170 0 1
172 0 1
173 0 1
175 0 1
188 0 1
189 0 1
194 0 1
195 0 1
197 0 1
202 0 1
204 0 1
205 0 1
207 0 1
210 0 1
284 0 1
285 0 1
288 0 1
289 0 1
291 0 1
296 0 1
300 unreachable

Cond Coverage for Module : prim_trivium
TotalCoveredPercent
Conditions4300.00
Logical4300.00
Non-Logical00
Event00

 LINE       119
 EXPRESSION (en_i | update_init)
             --1-   -----2-----
-1--2-StatusTests
00Not Covered
01Unreachable
10Not Covered 

 LINE       120
 EXPRESSION (seed_req_o & seed_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       170
 EXPRESSION (((!update)) ? state_q : state_update)
             -----1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       188
 EXPRESSION (lockup & ((StrictLockupProtection | (~allow_lockup_i))))
             ---1--   -----------------------2----------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered 

 LINE       189
 EXPRESSION (restore ? StateSeed : (wr_en_seed ? state_seed : (update ? state_update : state_q)))
             ---1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       189
 SUB-EXPRESSION (wr_en_seed ? state_seed : (update ? state_update : state_q))
                 -----1----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       189
 SUB-EXPRESSION (update ? state_update : state_q)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       202
 EXPRESSION ((seed_en_i | seed_req_q) & (((~seed_ack_i)) | ((~last_state_part))))
             ------------1-----------   --------------------2-------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       202
 SUB-EXPRESSION (seed_en_i | seed_req_q)
                 ----1----   -----2----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       202
 SUB-EXPRESSION (((~seed_ack_i)) | ((~last_state_part)))
                 -------1-------   ----------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       210
 EXPRESSION (seed_en_i | seed_req_q)
             ----1----   -----2----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       284
 EXPRESSION (state_idx_q == LastStatePart[(StateIdxWidth - 1):0])
            --------------------------1--------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       285
 EXPRESSION ((wr_en_seed & last_state_part) ? '0 : ((wr_en_seed & ((~last_state_part))) ? ((state_idx_q + 1'b1)) : state_idx_q))
             ---------------1--------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       285
 SUB-EXPRESSION (wr_en_seed & last_state_part)
                 -----1----   -------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       285
 SUB-EXPRESSION ((wr_en_seed & ((~last_state_part))) ? ((state_idx_q + 1'b1)) : state_idx_q)
                 -----------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       285
 SUB-EXPRESSION (wr_en_seed & ((~last_state_part)))
                 -----1----   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       296
 EXPRESSION (seed_req_o & seed_ack_i & last_state_part)
             -----1----   -----2----   -------3-------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered
Branch Coverage for Module : prim_trivium
Line No.TotalCoveredPercent
Branches 17 0 0.00
TERNARY 189 4 0 0.00
TERNARY 285 3 0 0.00
IF 194 2 0 0.00
IF 204 2 0 0.00
TERNARY 170 2 0 0.00
IF 172 2 0 0.00
IF 288 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' or '../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	189	(restore) ? 
-2-:	189	(wr_en_seed) ? 
-3-:	189	(update) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Not Covered 



	LineNo.	Expression
-1-:	285	((wr_en_seed & last_state_part)) ? 
-2-:	285	((wr_en_seed & (~last_state_part))) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	204	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	170	((!update)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	172	if (last_state_part)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

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