Unified Coverage Report :: Module :: kmac_entropy

Module : kmac_entropy

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.57	100.00	87.83		80.00	100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_entropy.u_entropy	97.57	100.00	87.83		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.57	100.00	87.83		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	87.97	100.00	100.00	98.98	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_entropy_configured	100.00	100.00				100.00	100.00
u_hash_count	100.00			100.00
u_prim_trivium	95.62	100.00	88.37			94.12	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
TOTAL		968	968	100.00
ALWAYS	241	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	259	8	8	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	6	6	100.00
ALWAYS	284	8	8	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
ALWAYS	340	6	6	100.00
ALWAYS	346	4	4	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
ALWAYS	391	4	4	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	3	3	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	422	3	3	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
ALWAYS	437	6	6	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
ALWAYS	468	3	3	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	487	3	3	100.00
ALWAYS	492	86	86	100.00
CONT_ASSIGN	742	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : kmac_entropy

	Total	Covered	Percent
Conditions	115	101	87.83
Logical	115	101	87.83
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T31,T9,T51
1	1	0	Covered	T1,T3,T43
1	1	1	Covered	T31,T44,T9

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T31,T44,T9
1	1	Covered	T1,T2,T3

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T31,T44,T9
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T30,T31
1	1	Covered	T1,T2,T3

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T30,T31
1	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T30,T31
1	1	Covered	T1,T2,T3

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T12,T79,T34
0	1	0	Covered	T79,T34,T80
1	0	0	Covered	T15,T12,T79

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T20
1	1	Covered	T30,T31,T20

 LINE       337
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T79,T34
1	1	Covered	T79,T34,T80

 LINE       353
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T43

 LINE       353
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T43

 LINE       364
 EXPRESSION (prng_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (data_update || msg_mask_en_i)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       404
 EXPRESSION (aux_update ? rand_data_q[(kmac_pkg::EntropyOutputW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       417
 EXPRESSION (aux_update ? rand_data_q[(kmac_pkg::EntropyOutputW - 2)-:4] : ({1'b0, prng_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T87,T81
1	0	Covered	T2,T30,T31

 LINE       466
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T30,T31
1	1	Covered	T2,T30,T31

 LINE       466
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T30,T31
1	0	Covered	T44,T87,T81

 LINE       572
 EXPRESSION ((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -----------------1----------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       572
 SUB-EXPRESSION (rand_update_i || rand_consumed_i)
                 ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       572
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T20

 LINE       572
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T20

 LINE       588
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T88,T89
1	0	Covered	T2,T30,T31
1	1	Covered	T79,T34,T80

 LINE       588
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T43
1	Covered	T2,T30,T31

 LINE       588
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T79,T34,T80
1	0	Covered	T12,T79,T34

 LINE       611
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T44,T9
1	0	Covered	T2,T30,T49
1	1	Covered	T44,T81,T82

 LINE       615
 EXPRESSION (entropy_req_o && entropy_ack_i)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T31
1	1	Covered	T2,T30,T31

 LINE       621
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T31,T9
0	1	Covered	T30,T49,T8
1	0	Covered	T85,T90,T91

 LINE       621
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T31,T9
1	1	Covered	T85,T90,T91

 LINE       629
 EXPRESSION ((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -----------------1----------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T44,T49
1	0	Covered	T34,T85,T90
1	1	Covered	T83,T84,T85

 LINE       629
 SUB-EXPRESSION (rand_update_i || rand_consumed_i)
                 ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T30,T31
0	1	Not Covered
1	0	Covered	T34,T83,T84

 LINE       629
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T31,T9
0	1	Covered	T30,T44,T49
1	0	Covered	T85,T90,T91

 LINE       629
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T31,T9
1	1	Covered	T85,T90,T91

 LINE       648
 EXPRESSION (seed_req & seed_update_i)
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T43
1	1	Covered	T1,T3,T43

 LINE       706
 EXPRESSION ((rand_update_i | rand_consumed_i) & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             ----------------1----------------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T72
1	0	Not Covered
1	1	Not Covered

 LINE       706
 SUB-EXPRESSION (rand_update_i | rand_consumed_i)
                 ------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T44,T45,T72
0	1	Not Covered
1	0	Not Covered

 LINE       706
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T72,T86
0	1	Covered	T44,T45,T72
1	0	Not Covered

 LINE       706
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T45,T72,T86
1	1	Not Covered

 LINE       742
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : kmac_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	20	16	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	545	Covered	T2,T30,T31
StRandErr	684	Covered	T44,T45,T72
StRandErrIncorrectMode	554	Covered	T45,T72,T86
StRandErrWaitExpired	613	Covered	T44,T81,T82
StRandGenerate	582	Covered	T1,T2,T3
StRandReady	586	Covered	T1,T2,T3
StRandReset	558	Covered	T1,T2,T3
StSwSeedWait	539	Covered	T1,T3,T43
StTerminalError	735	Covered	T9,T15,T16

transitions	Line No.	Covered	Tests
StRandEdn->StRandErrWaitExpired	613	Covered	T44,T81,T82
StRandEdn->StRandGenerate	619	Covered	T2,T30,T31
StRandEdn->StTerminalError	735	Covered	T87,T53
StRandErr->StRandReset	711	Covered	T44,T45,T72
StRandErr->StTerminalError	735	Not Covered
StRandErrIncorrectMode->StRandErr	693	Covered	T45,T72,T86
StRandErrIncorrectMode->StTerminalError	735	Not Covered
StRandErrWaitExpired->StRandErr	684	Covered	T44,T81,T82
StRandErrWaitExpired->StTerminalError	735	Not Covered
StRandGenerate->StRandReady	680	Covered	T1,T2,T3
StRandGenerate->StTerminalError	735	Covered	T61
StRandReady->StRandEdn	592	Covered	T79,T34,T80
StRandReady->StRandGenerate	582	Covered	T1,T2,T3
StRandReady->StTerminalError	735	Covered	T9,T16,T42
StRandReset->StRandEdn	545	Covered	T2,T30,T31
StRandReset->StRandErrIncorrectMode	554	Covered	T45,T72,T86
StRandReset->StSwSeedWait	539	Covered	T1,T3,T43
StRandReset->StTerminalError	735	Covered	T15,T40,T41
StSwSeedWait->StRandGenerate	651	Covered	T1,T3,T43
StSwSeedWait->StTerminalError	735	Not Covered

---

Branch Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
Branches		77	77	100.00
TERNARY	353	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	417	2	2	100.00
TERNARY	742	2	2	100.00
IF	241	3	3	100.00
IF	250	3	3	100.00
IF	259	5	5	100.00
IF	273	4	4	100.00
IF	284	5	5	100.00
IF	304	2	2	100.00
IF	340	4	4	100.00
IF	346	3	3	100.00
IF	391	3	3	100.00
IF	407	2	2	100.00
IF	422	2	2	100.00
IF	437	4	4	100.00
IF	468	2	2	100.00
IF	487	2	2	100.00
CASE	526	23	23	100.00
IF	734	2	2	100.00

353          assign seed = (mode_q == EntropyModeSw) ? seed_data_i : entropy_data_i;
                                                     -1-  
                                                     ==>  
                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T43
0	Covered	T1,T2,T3

404          assign aux_rand_d = aux_update ? rand_data_q[EntropyOutputW - 1] :
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

417          assign prng_en_rand_d =
                                    
418              aux_update ? rand_data_q[EntropyOutputW - 2 -: 4] : // refresh
                            -1-  
                            ==>  
                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

742          assign entropy_configured = (st != StRandReset)
                                                            
743                                    ? prim_mubi_pkg::MuBi4True
                                       -1-  
                                       ==>  
                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

241            if (!rst_ni) begin
               -1-  
242              non_zero_wait_timer_limit <= '0;
                 ==>
243            end else if (timer_update) begin
                        -2-  
244              non_zero_wait_timer_limit <= |wait_timer_limit_i;
                 ==>
245            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T30,T31
0	0	Covered	T1,T2,T3

250            if (!rst_ni) begin
               -1-  
251              wait_timer_prescaler_d <= '0;
                 ==>
252            end else if (timer_update) begin
                        -2-  
253              wait_timer_prescaler_d <= wait_timer_prescaler_i;
                 ==>
254            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T30,T31
0	0	Covered	T1,T2,T3

259            if (!rst_ni) begin
               -1-  
260              timer_value <= '0;
                 ==>
261            end else if (timer_update) begin
                        -2-  
262              timer_value <= timer_limit;
                 ==>
263            end else if (timer_expired) begin
                        -3-  
264              timer_value <= '0; // keep the value
                 ==>
265            end else if (timer_enable && timer_pulse && |timer_value) begin // if non-zero timer v
                        -4-  
266              timer_value <= timer_value - 1'b 1;
                 ==>
267            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T30,T31
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T31,T44,T9
0	0	0	0	Covered	T1,T2,T3

273            if (!rst_ni) begin
               -1-  
274              timer_expired <= 1'b 0;
                 ==>
275            end else if (timer_update) begin
                        -2-  
276              timer_expired <= 1'b 0;
                 ==>
277            end else if (timer_enable && (timer_value == '0)) begin
                        -3-  
278              timer_expired <= 1'b 1;
                 ==>
279            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T30,T31
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

284            if (!rst_ni) begin
               -1-  
285              prescaler_cnt <= '0;
                 ==>
286            end else if (timer_update) begin
                        -2-  
287              prescaler_cnt <= wait_timer_prescaler_i;
                 ==>
288            end else if (timer_enable && prescaler_cnt == '0) begin
                        -3-  
289              prescaler_cnt <= wait_timer_prescaler_d;
                 ==>
290            end else if (timer_enable) begin
                        -4-  
291              prescaler_cnt <= prescaler_cnt - 1'b 1;
                 ==>
292            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T30,T31
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T30,T31
0	0	0	0	Covered	T1,T2,T3

304            if (!rst_ni) hash_progress_q <= 1'b 0;
               -1-  
               ==>
305            else         hash_progress_q <= hash_progress_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

340            if (!rst_ni)                threshold_hit_q <= 1'b 0;
               -1-  
               ==>
341            else if (threshold_hit_clr) threshold_hit_q <= 1'b 0;
                    -2-  
               ==>
342            else if (threshold_hit)     threshold_hit_q <= 1'b 1;
                    -3-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T79,T34,T80
0	0	1	Covered	T79,T34,T80
0	0	0	Covered	T1,T2,T3

346            if (!rst_ni)         mode_q <= EntropyModeNone;
               -1-  
               ==>
347            else if (mode_latch) mode_q <= mode_i;
                    -2-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

391            if (!rst_ni) begin
               -1-  
392              rand_data_q <= RndCnstBufferLfsrSeed;
                 ==>
393            end else if (data_update || msg_mask_en_i) begin
                        -2-  
394              rand_data_q <= prng_data_permuted;
                 ==>
395            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

407            if (!rst_ni) begin
               -1-  
408              aux_rand_q <= '0;
                 ==>
409            end else begin
410              aux_rand_q <= aux_rand_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

422            if (!rst_ni) begin
               -1-  
423              prng_en_rand_q <= '0;
                 ==>
424            end else begin
425              prng_en_rand_q <= prng_en_rand_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

437            if (!rst_ni) begin
               -1-  
438              rand_valid_o <= 1'b 0;
                 ==>
439            end else if (rand_valid_set) begin
                        -2-  
440              rand_valid_o <= 1'b 1;
                 ==>
441            end else if (rand_valid_clear) begin
                        -3-  
442              rand_valid_o <= 1'b 0;
                 ==>
443            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

468            if (!rst_ni) begin
               -1-  
469              entropy_req_hold_q <= '0;
                 ==>
470            end else begin
471              entropy_req_hold_q <= entropy_req_hold_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

487          `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, rand_st_e, StRandReset)
             -1-                                                                     
             ==>                                                                     
             ==>                                                                     

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

526            unique case (st)
                      -1-  
527              StRandReset: begin
528                if (entropy_ready_i) begin
                   -2-  
529        
530                  // As SW ready, discard current dummy entropy and refresh.
531                  rand_valid_clear = 1'b 1;
532        
533                  mode_latch = 1'b 1;
534                  // SW has configured KMAC
535                  unique case (mode_i)
                            -3-  
536                    EntropyModeSw: begin
537                      // Start reseeding the PRNG via ENTROPY_SEED CSR.
538                      seed_en = 1'b 1;
                         ==>
539                      st_d = StSwSeedWait;
540                    end
541        
542                    EntropyModeEdn: begin
543                      // Start reseeding the PRNG via EDN.
544                      seed_en = 1'b 1;
                         ==>
545                      st_d = StRandEdn;
546        
547                      // Timer reset
548                      timer_update = 1'b 1;
549                    end
550        
551                    default: begin
552                      // EntropyModeNone or other values
553                      // Error. No valid mode given, report to SW
554                      st_d = StRandErrIncorrectMode;
                         ==>
555                    end
556                  endcase
557                end else begin
558                  st_d = StRandReset;
                     ==>
559        
560                  // Setting the dummy rand gate until SW prepares.
561                  // This lets the Application Interface move forward out of reset
562                  // without SW intervention.
563                  rand_valid_set = 1'b 1;
564                end
565              end
566        
567              StRandReady: begin
568                timer_enable = 1'b 1; // If limit is zero, timer won't work
569        
570                prng_en = prng_en_rand_q[0];
571        
572                if ((rand_update_i || rand_consumed_i) &&
                   -4-  
573                    ((fast_process_i && in_keyblock_i) || !fast_process_i)) begin
574                  // If fast_process is set, don't clear the rand valid, even
575                  // consumed. So, the logic does not expand the entropy again.
576                  // If fast_process is not set, then every rand_consume signal
577                  // triggers rand expansion.
578                  prng_en = 1'b 1;
579                  data_update = 1'b 1;
580        
581                  if (rand_consumed_i) begin
                     -5-  
582                    st_d = StRandGenerate;
                       ==>
583        
584                    rand_valid_clear = 1'b 1;
585                  end else begin
586                    st_d = StRandReady;
                       ==>
587                  end
588                end else if ((mode_q == EntropyModeEdn) &&
                            -6-  
589                    (entropy_refresh_req_i || threshold_hit_q)) begin
590                  // Start reseeding the PRNG via EDN.
591                  seed_en = 1'b 1;
                     ==>
592                  st_d = StRandEdn;
593        
594                  // Timer reset
595                  timer_update = 1'b 1;
596        
597                  // Clear the threshold as it refreshes the hash
598                  threshold_hit_clr = 1'b 1;
599                end else begin
600                  st_d = StRandReady;
                     ==>
601                end
602              end
603        
604              StRandEdn: begin
605                // Forward request of PRNG primitive.
606                entropy_req = seed_req;
607        
608                // Wait timer
609                timer_enable = 1'b 1;
610        
611                if (timer_expired && non_zero_wait_timer_limit) begin
                   -7-  
612                  // If timer count is non-zero and expired;
613                  st_d = StRandErrWaitExpired;
                     ==>
614        
615                end else if (entropy_req_o && entropy_ack_i) begin
                            -8-  
616                  seed_ack = 1'b 1;
617        
618                  if (seed_done) begin
                     -9-  
619                    st_d = StRandGenerate;
620        
621                    if ((fast_process_i && in_keyblock_i) || !fast_process_i) begin
                       -10-  
622                      prng_en = 1'b 1;
                         ==>
623                      data_update = 1'b 1;
624                      rand_valid_clear = 1'b 1;
625                    end
                       MISSING_ELSE
                       ==>
626                  end else begin
627                    st_d = StRandEdn;
                       ==>
628                  end
629                end else if ((rand_update_i || rand_consumed_i) &&
                            -11-  
630                    ((fast_process_i && in_keyblock_i) || !fast_process_i)) begin
631                  // Somehow, while waiting the EDN entropy, the KMAC or SHA3 logic
632                  // consumed the remained entropy. This can happen when the previous
633                  // SHA3/ KMAC op completed and this Entropy FSM has moved to this
634                  // state to refresh the entropy and the SW initiates another hash
635                  // operation while waiting for the EDN response.
636                  st_d = StRandEdn;
                     ==>
637        
638                  prng_en = 1'b 1;
639                  data_update = 1'b 1;
640                  rand_valid_clear = rand_consumed_i;
641                end else begin
642                  st_d = StRandEdn;
                     ==>
643                end
644              end
645        
646              StSwSeedWait: begin
647                // Forward ack driven by software.
648                seed_ack = seed_req & seed_update_i;
649        
650                if (seed_done) begin
                   -12-  
651                  st_d = StRandGenerate;
                     ==>
652        
653                  prng_en = 1'b 1;
654                  data_update = 1'b 1;
655        
656                  rand_valid_clear = 1'b 1;
657                end else begin
658                  st_d = StSwSeedWait;
                     ==>
659                end
660              end
661        
662              StRandGenerate: begin
663                // The current buffer output is used as auxiliary randomness and -
664                // depending on whether keccak_round is parametrized to always forward
665                // the buffer output and not use intermediate randomness - forwarded
666                // to the DOM multipliers without them updating in this cycle. We don't
667                // need to advance the PRNG as there is no risk of accidentally
668                // re-using the same randomness twice since after the current cycle:
669                // - We either load and re-mask the message/key which will use
670                //   different PRNG output bits. The PRNG is advanced once per 64 bits
671                //   loaded.
672                // - Or, the Keccak/SHA3 core is operated but it always starts with
673                //   the linear layers which don't require fresh randomness. While
674                //   processing the linear layers, the PRNG is advanced to have fresh
675                //   randomness for the non-linear layer requiring it.
676                aux_update = 1'b 1;
                   ==>
677                rand_valid_set = 1'b 1;
678                prng_en = prng_en_rand_q[0];
679        
680                st_d = StRandReady;
681              end
682        
683              StRandErrWaitExpired: begin
684                st_d = StRandErr;
                   ==>
685        
686                err_o = '{ valid: 1'b 1,
687                           code: ErrWaitTimerExpired,
688                           info: 24'(timer_value)
689                         };
690              end
691        
692              StRandErrIncorrectMode: begin
693                st_d = StRandErr;
                   ==>
694        
695                err_o = '{ valid: 1'b 1,
696                           code: ErrIncorrectEntropyMode,
697                           info: 24'(mode_q)
698                         };
699              end
700        
701              StRandErr: begin
702                // Keep entropy signal valid to complete current hashing even with error
703                rand_valid_set = 1'b 1;
704        
705                // Advance the PRNG after the entropy has been used.
706                prng_en = (rand_update_i | rand_consumed_i) &
707                    ((fast_process_i & in_keyblock_i) | ~fast_process_i);
708                data_update = prng_en;
709        
710                if (err_processed_i) begin
                   -13-  
711                  st_d = StRandReset;
                     ==>
712        
713                end else begin
714                  st_d = StRandErr;
                     ==>
715                end
716        
717              end
718        
719              StTerminalError: begin
720                // this state is terminal
721                st_d = st;
                   ==>
722                sparse_fsm_error_o = 1'b 1;
723              end
724        
725              default: begin
726                st_d = StTerminalError;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T43
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Covered	T2,T30,T31
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Covered	T45,T72,T86
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T79,T34,T80
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T44,T81,T82
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T30,T49,T8
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T2,T31,T9
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T2,T30,T31
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Covered	T83,T84,T85
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Covered	T2,T30,T31
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T43
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T3,T43
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T81,T82
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T72,T86
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T44,T45,T72
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T44,T45,T72
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T40,T41

734            if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
               -1-  
735              st_d = StTerminalError;
                 ==>
736            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_entropy

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ConsumeNotAssertWhenNotValid_M	640180531	64004333	0	0
EdnBusWidth_A	665	665	0	0
ModeKnown_A	640180531	640001293	0	0
RandStKnown_A	640180531	640001293	0	0
p_perm_check.PermutationCheck_A	665	665	0	0
u_state_regs_A	640180531	640001293	0	0

ConsumeNotAssertWhenNotValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	64004333	0	0
T1	84512	7632	0	0
T2	116868	10512	0	0
T3	201179	9936	0	0
T4	0	6336	0	0
T7	14564	648	0	0
T20	311127	16776	0	0
T29	448588	35640	0	0
T30	4435	792	0	0
T31	9839	792	0	0
T43	159485	5328	0	0
T44	1227	0	0	0

EdnBusWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

ModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

RandStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
TOTAL		968	968	100.00
ALWAYS	241	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	259	8	8	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	6	6	100.00
ALWAYS	284	8	8	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
ALWAYS	340	6	6	100.00
ALWAYS	346	4	4	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
ALWAYS	391	4	4	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	3	3	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	422	3	3	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
ALWAYS	437	6	6	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
ALWAYS	468	3	3	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	487	3	3	100.00
ALWAYS	492	86	86	100.00
CONT_ASSIGN	742	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Covered	Percent
Conditions	115	101	87.83
Logical	115	101	87.83
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T31,T9,T51
1	1	0	Covered	T1,T3,T43
1	1	1	Covered	T31,T44,T9

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T31,T44,T9
1	1	Covered	T1,T2,T3

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T31,T44,T9
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T30,T31
1	1	Covered	T1,T2,T3

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T30,T31
1	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T30,T31
1	1	Covered	T1,T2,T3

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T12,T79,T34
0	1	0	Covered	T79,T34,T80
1	0	0	Covered	T15,T12,T79

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T20
1	1	Covered	T30,T31,T20

 LINE       337
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T79,T34
1	1	Covered	T79,T34,T80

 LINE       353
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T43

 LINE       353
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T43

 LINE       364
 EXPRESSION (prng_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (data_update || msg_mask_en_i)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       404
 EXPRESSION (aux_update ? rand_data_q[(kmac_pkg::EntropyOutputW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       417
 EXPRESSION (aux_update ? rand_data_q[(kmac_pkg::EntropyOutputW - 2)-:4] : ({1'b0, prng_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T87,T81
1	0	Covered	T2,T30,T31

 LINE       466
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T30,T31
1	1	Covered	T2,T30,T31

 LINE       466
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T30,T31
1	0	Covered	T44,T87,T81

 LINE       572
 EXPRESSION ((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -----------------1----------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       572
 SUB-EXPRESSION (rand_update_i || rand_consumed_i)
                 ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       572
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T20

 LINE       572
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T20

 LINE       588
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T88,T89
1	0	Covered	T2,T30,T31
1	1	Covered	T79,T34,T80

 LINE       588
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T43
1	Covered	T2,T30,T31

 LINE       588
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T79,T34,T80
1	0	Covered	T12,T79,T34

 LINE       611
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T44,T9
1	0	Covered	T2,T30,T49
1	1	Covered	T44,T81,T82

 LINE       615
 EXPRESSION (entropy_req_o && entropy_ack_i)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T30,T31
1	1	Covered	T2,T30,T31

 LINE       621
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T31,T9
0	1	Covered	T30,T49,T8
1	0	Covered	T85,T90,T91

 LINE       621
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T31,T9
1	1	Covered	T85,T90,T91

 LINE       629
 EXPRESSION ((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -----------------1----------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T44,T49
1	0	Covered	T34,T85,T90
1	1	Covered	T83,T84,T85

 LINE       629
 SUB-EXPRESSION (rand_update_i || rand_consumed_i)
                 ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T30,T31
0	1	Not Covered
1	0	Covered	T34,T83,T84

 LINE       629
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T31,T9
0	1	Covered	T30,T44,T49
1	0	Covered	T85,T90,T91

 LINE       629
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T31,T9
1	1	Covered	T85,T90,T91

 LINE       648
 EXPRESSION (seed_req & seed_update_i)
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T43
1	1	Covered	T1,T3,T43

 LINE       706
 EXPRESSION ((rand_update_i | rand_consumed_i) & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             ----------------1----------------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T72
1	0	Not Covered
1	1	Not Covered

 LINE       706
 SUB-EXPRESSION (rand_update_i | rand_consumed_i)
                 ------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T44,T45,T72
0	1	Not Covered
1	0	Not Covered

 LINE       706
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T72,T86
0	1	Covered	T44,T45,T72
1	0	Not Covered

 LINE       706
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T45,T72,T86
1	1	Not Covered

 LINE       742
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_entropy.u_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	16	16	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	545	Covered	T2,T30,T31
StRandErr	684	Covered	T44,T45,T72
StRandErrIncorrectMode	554	Covered	T45,T72,T86
StRandErrWaitExpired	613	Covered	T44,T81,T82
StRandGenerate	582	Covered	T1,T2,T3
StRandReady	586	Covered	T1,T2,T3
StRandReset	558	Covered	T1,T2,T3
StSwSeedWait	539	Covered	T1,T3,T43
StTerminalError	735	Covered	T9,T15,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
StRandEdn->StRandErrWaitExpired	613	Covered	T44,T81,T82
StRandEdn->StRandGenerate	619	Covered	T2,T30,T31
StRandEdn->StTerminalError	735	Covered	T87,T53
StRandErr->StRandReset	711	Covered	T44,T45,T72
StRandErr->StTerminalError	735	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrIncorrectMode->StRandErr	693	Covered	T45,T72,T86
StRandErrIncorrectMode->StTerminalError	735	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrWaitExpired->StRandErr	684	Covered	T44,T81,T82
StRandErrWaitExpired->StTerminalError	735	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandGenerate->StRandReady	680	Covered	T1,T2,T3
StRandGenerate->StTerminalError	735	Covered	T61
StRandReady->StRandEdn	592	Covered	T79,T34,T80
StRandReady->StRandGenerate	582	Covered	T1,T2,T3
StRandReady->StTerminalError	735	Covered	T9,T16,T42
StRandReset->StRandEdn	545	Covered	T2,T30,T31
StRandReset->StRandErrIncorrectMode	554	Covered	T45,T72,T86
StRandReset->StSwSeedWait	539	Covered	T1,T3,T43
StRandReset->StTerminalError	735	Covered	T15,T40,T41
StSwSeedWait->StRandGenerate	651	Covered	T1,T3,T43
StSwSeedWait->StTerminalError	735	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.

---

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
Branches		77	77	100.00
TERNARY	353	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	417	2	2	100.00
TERNARY	742	2	2	100.00
IF	241	3	3	100.00
IF	250	3	3	100.00
IF	259	5	5	100.00
IF	273	4	4	100.00
IF	284	5	5	100.00
IF	304	2	2	100.00
IF	340	4	4	100.00
IF	346	3	3	100.00
IF	391	3	3	100.00
IF	407	2	2	100.00
IF	422	2	2	100.00
IF	437	4	4	100.00
IF	468	2	2	100.00
IF	487	2	2	100.00
CASE	526	23	23	100.00
IF	734	2	2	100.00

353          assign seed = (mode_q == EntropyModeSw) ? seed_data_i : entropy_data_i;
                                                     -1-  
                                                     ==>  
                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T43
0	Covered	T1,T2,T3

404          assign aux_rand_d = aux_update ? rand_data_q[EntropyOutputW - 1] :
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

417          assign prng_en_rand_d =
                                    
418              aux_update ? rand_data_q[EntropyOutputW - 2 -: 4] : // refresh
                            -1-  
                            ==>  
                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

742          assign entropy_configured = (st != StRandReset)
                                                            
743                                    ? prim_mubi_pkg::MuBi4True
                                       -1-  
                                       ==>  
                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

241            if (!rst_ni) begin
               -1-  
242              non_zero_wait_timer_limit <= '0;
                 ==>
243            end else if (timer_update) begin
                        -2-  
244              non_zero_wait_timer_limit <= |wait_timer_limit_i;
                 ==>
245            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T30,T31
0	0	Covered	T1,T2,T3

250            if (!rst_ni) begin
               -1-  
251              wait_timer_prescaler_d <= '0;
                 ==>
252            end else if (timer_update) begin
                        -2-  
253              wait_timer_prescaler_d <= wait_timer_prescaler_i;
                 ==>
254            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T30,T31
0	0	Covered	T1,T2,T3

259            if (!rst_ni) begin
               -1-  
260              timer_value <= '0;
                 ==>
261            end else if (timer_update) begin
                        -2-  
262              timer_value <= timer_limit;
                 ==>
263            end else if (timer_expired) begin
                        -3-  
264              timer_value <= '0; // keep the value
                 ==>
265            end else if (timer_enable && timer_pulse && |timer_value) begin // if non-zero timer v
                        -4-  
266              timer_value <= timer_value - 1'b 1;
                 ==>
267            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T30,T31
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T31,T44,T9
0	0	0	0	Covered	T1,T2,T3

273            if (!rst_ni) begin
               -1-  
274              timer_expired <= 1'b 0;
                 ==>
275            end else if (timer_update) begin
                        -2-  
276              timer_expired <= 1'b 0;
                 ==>
277            end else if (timer_enable && (timer_value == '0)) begin
                        -3-  
278              timer_expired <= 1'b 1;
                 ==>
279            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T30,T31
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

284            if (!rst_ni) begin
               -1-  
285              prescaler_cnt <= '0;
                 ==>
286            end else if (timer_update) begin
                        -2-  
287              prescaler_cnt <= wait_timer_prescaler_i;
                 ==>
288            end else if (timer_enable && prescaler_cnt == '0) begin
                        -3-  
289              prescaler_cnt <= wait_timer_prescaler_d;
                 ==>
290            end else if (timer_enable) begin
                        -4-  
291              prescaler_cnt <= prescaler_cnt - 1'b 1;
                 ==>
292            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T30,T31
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T30,T31
0	0	0	0	Covered	T1,T2,T3

304            if (!rst_ni) hash_progress_q <= 1'b 0;
               -1-  
               ==>
305            else         hash_progress_q <= hash_progress_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

340            if (!rst_ni)                threshold_hit_q <= 1'b 0;
               -1-  
               ==>
341            else if (threshold_hit_clr) threshold_hit_q <= 1'b 0;
                    -2-  
               ==>
342            else if (threshold_hit)     threshold_hit_q <= 1'b 1;
                    -3-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T79,T34,T80
0	0	1	Covered	T79,T34,T80
0	0	0	Covered	T1,T2,T3

346            if (!rst_ni)         mode_q <= EntropyModeNone;
               -1-  
               ==>
347            else if (mode_latch) mode_q <= mode_i;
                    -2-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

391            if (!rst_ni) begin
               -1-  
392              rand_data_q <= RndCnstBufferLfsrSeed;
                 ==>
393            end else if (data_update || msg_mask_en_i) begin
                        -2-  
394              rand_data_q <= prng_data_permuted;
                 ==>
395            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

407            if (!rst_ni) begin
               -1-  
408              aux_rand_q <= '0;
                 ==>
409            end else begin
410              aux_rand_q <= aux_rand_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

422            if (!rst_ni) begin
               -1-  
423              prng_en_rand_q <= '0;
                 ==>
424            end else begin
425              prng_en_rand_q <= prng_en_rand_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

437            if (!rst_ni) begin
               -1-  
438              rand_valid_o <= 1'b 0;
                 ==>
439            end else if (rand_valid_set) begin
                        -2-  
440              rand_valid_o <= 1'b 1;
                 ==>
441            end else if (rand_valid_clear) begin
                        -3-  
442              rand_valid_o <= 1'b 0;
                 ==>
443            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

468            if (!rst_ni) begin
               -1-  
469              entropy_req_hold_q <= '0;
                 ==>
470            end else begin
471              entropy_req_hold_q <= entropy_req_hold_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

487          `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, rand_st_e, StRandReset)
             -1-                                                                     
             ==>                                                                     
             ==>                                                                     

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

526            unique case (st)
                      -1-  
527              StRandReset: begin
528                if (entropy_ready_i) begin
                   -2-  
529        
530                  // As SW ready, discard current dummy entropy and refresh.
531                  rand_valid_clear = 1'b 1;
532        
533                  mode_latch = 1'b 1;
534                  // SW has configured KMAC
535                  unique case (mode_i)
                            -3-  
536                    EntropyModeSw: begin
537                      // Start reseeding the PRNG via ENTROPY_SEED CSR.
538                      seed_en = 1'b 1;
                         ==>
539                      st_d = StSwSeedWait;
540                    end
541        
542                    EntropyModeEdn: begin
543                      // Start reseeding the PRNG via EDN.
544                      seed_en = 1'b 1;
                         ==>
545                      st_d = StRandEdn;
546        
547                      // Timer reset
548                      timer_update = 1'b 1;
549                    end
550        
551                    default: begin
552                      // EntropyModeNone or other values
553                      // Error. No valid mode given, report to SW
554                      st_d = StRandErrIncorrectMode;
                         ==>
555                    end
556                  endcase
557                end else begin
558                  st_d = StRandReset;
                     ==>
559        
560                  // Setting the dummy rand gate until SW prepares.
561                  // This lets the Application Interface move forward out of reset
562                  // without SW intervention.
563                  rand_valid_set = 1'b 1;
564                end
565              end
566        
567              StRandReady: begin
568                timer_enable = 1'b 1; // If limit is zero, timer won't work
569        
570                prng_en = prng_en_rand_q[0];
571        
572                if ((rand_update_i || rand_consumed_i) &&
                   -4-  
573                    ((fast_process_i && in_keyblock_i) || !fast_process_i)) begin
574                  // If fast_process is set, don't clear the rand valid, even
575                  // consumed. So, the logic does not expand the entropy again.
576                  // If fast_process is not set, then every rand_consume signal
577                  // triggers rand expansion.
578                  prng_en = 1'b 1;
579                  data_update = 1'b 1;
580        
581                  if (rand_consumed_i) begin
                     -5-  
582                    st_d = StRandGenerate;
                       ==>
583        
584                    rand_valid_clear = 1'b 1;
585                  end else begin
586                    st_d = StRandReady;
                       ==>
587                  end
588                end else if ((mode_q == EntropyModeEdn) &&
                            -6-  
589                    (entropy_refresh_req_i || threshold_hit_q)) begin
590                  // Start reseeding the PRNG via EDN.
591                  seed_en = 1'b 1;
                     ==>
592                  st_d = StRandEdn;
593        
594                  // Timer reset
595                  timer_update = 1'b 1;
596        
597                  // Clear the threshold as it refreshes the hash
598                  threshold_hit_clr = 1'b 1;
599                end else begin
600                  st_d = StRandReady;
                     ==>
601                end
602              end
603        
604              StRandEdn: begin
605                // Forward request of PRNG primitive.
606                entropy_req = seed_req;
607        
608                // Wait timer
609                timer_enable = 1'b 1;
610        
611                if (timer_expired && non_zero_wait_timer_limit) begin
                   -7-  
612                  // If timer count is non-zero and expired;
613                  st_d = StRandErrWaitExpired;
                     ==>
614        
615                end else if (entropy_req_o && entropy_ack_i) begin
                            -8-  
616                  seed_ack = 1'b 1;
617        
618                  if (seed_done) begin
                     -9-  
619                    st_d = StRandGenerate;
620        
621                    if ((fast_process_i && in_keyblock_i) || !fast_process_i) begin
                       -10-  
622                      prng_en = 1'b 1;
                         ==>
623                      data_update = 1'b 1;
624                      rand_valid_clear = 1'b 1;
625                    end
                       MISSING_ELSE
                       ==>
626                  end else begin
627                    st_d = StRandEdn;
                       ==>
628                  end
629                end else if ((rand_update_i || rand_consumed_i) &&
                            -11-  
630                    ((fast_process_i && in_keyblock_i) || !fast_process_i)) begin
631                  // Somehow, while waiting the EDN entropy, the KMAC or SHA3 logic
632                  // consumed the remained entropy. This can happen when the previous
633                  // SHA3/ KMAC op completed and this Entropy FSM has moved to this
634                  // state to refresh the entropy and the SW initiates another hash
635                  // operation while waiting for the EDN response.
636                  st_d = StRandEdn;
                     ==>
637        
638                  prng_en = 1'b 1;
639                  data_update = 1'b 1;
640                  rand_valid_clear = rand_consumed_i;
641                end else begin
642                  st_d = StRandEdn;
                     ==>
643                end
644              end
645        
646              StSwSeedWait: begin
647                // Forward ack driven by software.
648                seed_ack = seed_req & seed_update_i;
649        
650                if (seed_done) begin
                   -12-  
651                  st_d = StRandGenerate;
                     ==>
652        
653                  prng_en = 1'b 1;
654                  data_update = 1'b 1;
655        
656                  rand_valid_clear = 1'b 1;
657                end else begin
658                  st_d = StSwSeedWait;
                     ==>
659                end
660              end
661        
662              StRandGenerate: begin
663                // The current buffer output is used as auxiliary randomness and -
664                // depending on whether keccak_round is parametrized to always forward
665                // the buffer output and not use intermediate randomness - forwarded
666                // to the DOM multipliers without them updating in this cycle. We don't
667                // need to advance the PRNG as there is no risk of accidentally
668                // re-using the same randomness twice since after the current cycle:
669                // - We either load and re-mask the message/key which will use
670                //   different PRNG output bits. The PRNG is advanced once per 64 bits
671                //   loaded.
672                // - Or, the Keccak/SHA3 core is operated but it always starts with
673                //   the linear layers which don't require fresh randomness. While
674                //   processing the linear layers, the PRNG is advanced to have fresh
675                //   randomness for the non-linear layer requiring it.
676                aux_update = 1'b 1;
                   ==>
677                rand_valid_set = 1'b 1;
678                prng_en = prng_en_rand_q[0];
679        
680                st_d = StRandReady;
681              end
682        
683              StRandErrWaitExpired: begin
684                st_d = StRandErr;
                   ==>
685        
686                err_o = '{ valid: 1'b 1,
687                           code: ErrWaitTimerExpired,
688                           info: 24'(timer_value)
689                         };
690              end
691        
692              StRandErrIncorrectMode: begin
693                st_d = StRandErr;
                   ==>
694        
695                err_o = '{ valid: 1'b 1,
696                           code: ErrIncorrectEntropyMode,
697                           info: 24'(mode_q)
698                         };
699              end
700        
701              StRandErr: begin
702                // Keep entropy signal valid to complete current hashing even with error
703                rand_valid_set = 1'b 1;
704        
705                // Advance the PRNG after the entropy has been used.
706                prng_en = (rand_update_i | rand_consumed_i) &
707                    ((fast_process_i & in_keyblock_i) | ~fast_process_i);
708                data_update = prng_en;
709        
710                if (err_processed_i) begin
                   -13-  
711                  st_d = StRandReset;
                     ==>
712        
713                end else begin
714                  st_d = StRandErr;
                     ==>
715                end
716        
717              end
718        
719              StTerminalError: begin
720                // this state is terminal
721                st_d = st;
                   ==>
722                sparse_fsm_error_o = 1'b 1;
723              end
724        
725              default: begin
726                st_d = StTerminalError;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T43
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Covered	T2,T30,T31
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Covered	T45,T72,T86
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T79,T34,T80
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T44,T81,T82
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T30,T49,T8
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T2,T31,T9
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T2,T30,T31
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Covered	T83,T84,T85
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Covered	T2,T30,T31
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T43
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T3,T43
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T81,T82
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T72,T86
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T44,T45,T72
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T44,T45,T72
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T40,T41

734            if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
               -1-  
735              st_d = StTerminalError;
                 ==>
736            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ConsumeNotAssertWhenNotValid_M	640180531	64004333	0	0
EdnBusWidth_A	665	665	0	0
ModeKnown_A	640180531	640001293	0	0
RandStKnown_A	640180531	640001293	0	0
p_perm_check.PermutationCheck_A	665	665	0	0
u_state_regs_A	640180531	640001293	0	0

ConsumeNotAssertWhenNotValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	64004333	0	0
T1	84512	7632	0	0
T2	116868	10512	0	0
T3	201179	9936	0	0
T4	0	6336	0	0
T7	14564	648	0	0
T20	311127	16776	0	0
T29	448588	35640	0	0
T30	4435	792	0	0
T31	9839	792	0	0
T43	159485	5328	0	0
T44	1227	0	0	0

EdnBusWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

ModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

RandStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0