Unified Coverage Report :: Module :: prim_sparse_fsm_flop

Module : prim_sparse_fsm_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_state_regs	100.00	100.00					100.00
tb.dut.u_kmac_core.u_state_regs	100.00	100.00					100.00
tb.dut.u_sha3.u_state_regs	100.00	100.00					100.00
tb.dut.u_sha3.u_pad.u_state_regs	100.00	100.00					100.00
tb.dut.u_sha3.u_keccak.u_state_regs	100.00	100.00					100.00
tb.dut.u_app_intf.u_state_regs	100.00	100.00					100.00
tb.dut.u_errchk.u_state_regs	100.00	100.00					100.00
tb.dut.gen_entropy.u_entropy.u_state_regs	100.00	100.00					100.00

---

Module Instance : tb.dut.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_kmac_core.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.30	98.68	92.86		100.00	91.07	88.89	u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sha3.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	97.56	88.89		100.00	93.33	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sha3.u_pad.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	99.41	88.37		100.00	95.70	100.00	u_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.81	94.55	100.00		73.33	91.18	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_app_intf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.27	94.57	86.30		44.44	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_errchk.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	94.59	94.59		80.00	93.33	100.00	u_errchk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.57	100.00	87.83		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

Line Coverage for Module : prim_sparse_fsm_flop

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_sparse_fsm_flop

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	5320	5320	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5320	5320	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T7	8	8	0	0
T20	8	8	0	0
T29	8	8	0	0
T30	8	8	0	0
T31	8	8	0	0
T43	8	8	0	0
T44	8	8	0	0

Line Coverage for Instance : tb.dut.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	665	665	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Line Coverage for Instance : tb.dut.u_kmac_core.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_kmac_core.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	665	665	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_sha3.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	665	665	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	665	665	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	665	665	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Line Coverage for Instance : tb.dut.u_app_intf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_app_intf.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	665	665	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Line Coverage for Instance : tb.dut.u_errchk.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_errchk.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	665	665	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	665	665	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0