Unified Coverage Report :: Module :: kmac_errchk

Module : kmac_errchk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	94.59	94.59		80.00	93.33	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_errchk	92.50	94.59	94.59		80.00	93.33	100.00

---

Module Instance : tb.dut.u_errchk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	94.59	94.59		80.00	93.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.66	95.18	94.59		80.00	93.55	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_errchk

	Line No.	Total	Covered	Percent
TOTAL		74	70	94.59
ALWAYS	187	15	13	86.67
CONT_ASSIGN	236	1	1	100.00
ALWAYS	244	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	266	4	4	100.00
ALWAYS	278	6	6	100.00
ALWAYS	286	4	3	75.00
ALWAYS	309	6	6	100.00
ALWAYS	322	6	5	83.33
CONT_ASSIGN	376	1	1	100.00
ALWAYS	391	3	3	100.00
CONT_ASSIGN	399	1	1	100.00
ALWAYS	402	19	19	100.00

186                       always_comb begin
187        1/1              err_swsequence = 1'b 0;
           Tests:       T1 T2 T3 
188        1/1              sparse_fsm_error_o = 1'b 0;
           Tests:       T1 T2 T3 
189                     
190        1/1              unique case (st)
           Tests:       T1 T2 T3 
191                           StIdle: begin
192                             // Allow Start command only
193        1/1                  if (!(sw_cmd_i inside {CmdNone, CmdStart})) begin
           Tests:       T1 T2 T3 
194        1/1                    err_swsequence = 1'b 1;
           Tests:       T17 T26 T76 
195                             end
                        MISSING_ELSE
196                           end
197                     
198                           StMsgFeed: begin
199                             // Allow Process only
200        1/1                  if (!(sw_cmd_i inside {CmdNone, CmdProcess})) begin
           Tests:       T1 T2 T3 
201        1/1                    err_swsequence = 1'b 1;
           Tests:       T17 T26 T18 
202                             end
                        MISSING_ELSE
203                           end
204                     
205                           StProcessing: begin
206        1/1                  if (sw_cmd_i != CmdNone) begin
           Tests:       T1 T2 T3 
207        0/1     ==>            err_swsequence = 1'b 1;
208                             end
                        MISSING_ELSE
209                           end
210                     
211                           StAbsorbed: begin
212                             // Allow ManualRun and Done
213        1/1                  if (!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone})) begin
           Tests:       T1 T2 T3 
214        1/1                    err_swsequence = 1'b 1;
           Tests:       T17 T26 T18 
215                             end
                        MISSING_ELSE
216                           end
217                     
218                           StSqueezing: begin
219        1/1                  if (sw_cmd_i != CmdNone) begin
           Tests:       T20 T9 T10 
220        0/1     ==>            err_swsequence = 1'b 1;
221                             end
                        MISSING_ELSE
222                           end
223                     
224                           StTerminalError: begin
225        1/1                  err_swsequence = 1'b 0;
           Tests:       T9 T15 T16 
226        1/1                  sparse_fsm_error_o = 1'b 1;
           Tests:       T9 T15 T16 
227                           end
228                     
229                           default: begin
230                             err_swsequence = 1'b 0;
231                             sparse_fsm_error_o = 1'b 1;
232                           end
233                         endcase
234                       end
235                     
236        1/1            assign block_swcmd =  (err_swsequence)
           Tests:       T1 T2 T3 
237                                          || (err_modestrength
238                                              && !cfg_en_unsupported_modestrength_i)
239                                          || err_entropy_ready;
240                     
241                       // sw_cmd_o latch
242                       // To reduce the command path delay, sw_cmd is latched here
243                       always_ff @(posedge clk_i or negedge rst_ni) begin
244        2/2              if (!rst_ni)           sw_cmd_o <= CmdNone;
           Tests:       T1 T2 T3  | T1 T2 T3 
245        2/2              else if (!block_swcmd) sw_cmd_o <= sw_cmd_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
246                       end
247                     
248                       // Mode & Strength
249                       always_comb begin : check_modestrength
250        1/1              err_modestrength = 1'b 0;
           Tests:       T1 T2 T3 
251                     
252        1/1              if (st == StIdle && st_d == StMsgFeed) begin
           Tests:       T1 T2 T3 
253                           // When moving to the next stage, checks the config
254        1/1                if (!((cfg_mode_i == Sha3 &&
           Tests:       T1 T2 T3 
255                                  cfg_strength_i inside {L224, L256, L384, L512}) ||
256                                 ((cfg_mode_i == Shake || cfg_mode_i == CShake) &&
257                                  (cfg_strength_i inside {L128, L256})))) begin
258        1/1                  err_modestrength = 1'b 1;
           Tests:       T17 T26 T76 
259                           end
                        MISSING_ELSE
260                         end
                        MISSING_ELSE
261                       end : check_modestrength
262                     
263                     
264                       // Check prefix 6B is `encode_string("KMAC")`
265                       always_comb begin : check_prefix
266        1/1              err_prefix = 1'b 0;
           Tests:       T1 T2 T3 
267                     
268        1/1              if (st == StIdle && st_d == StMsgFeed && kmac_en_i) begin
           Tests:       T1 T2 T3 
269        1/1                if (cfg_prefix_6B_i != EncodedStringKMAC) begin
           Tests:       T30 T31 T20 
270        1/1                  err_prefix = 1'b 1;
           Tests:       T17 T26 T76 
271                           end
                        MISSING_ELSE
272                         end
                        MISSING_ELSE
273                       end : check_prefix
274                     
275                       if (EnMasking) begin : g_entropy_chk
276                     
277                         always_ff @(posedge clk_i or negedge rst_ni) begin
278        2/2                if (!rst_ni)              cfg_entropy_ready <= 1'b 0;
           Tests:       T1 T2 T3  | T1 T2 T3 
279        2/2                else if (err_processed_i) cfg_entropy_ready <= 1'b 0;
           Tests:       T1 T2 T3  | T7 T44 T45 
280        1/1                else if (entropy_ready_pulse_i && st == StIdle) begin
           Tests:       T1 T2 T3 
281        1/1                  cfg_entropy_ready <= 1'b 1;
           Tests:       T1 T2 T3 
282                           end
                        MISSING_ELSE
283                         end
284                     
285                         always_comb begin : check_entropy_ready
286        1/1                err_entropy_ready = 1'b 0;
           Tests:       T1 T2 T3 
287                     
288        1/1                if (st == StIdle && st_d == StMsgFeed && kmac_en_i) begin
           Tests:       T1 T2 T3 
289        1/1                  if (!cfg_entropy_ready) begin
           Tests:       T30 T31 T20 
290        0/1     ==>            err_entropy_ready = 1'b 1;
291                             end
                        MISSING_ELSE
292                           end
                        MISSING_ELSE
293                         end : check_entropy_ready
294                     
295                       end else begin : g_pseudo_entropy_chk
296                     
297                         // If EnMasking is 0, entropy module is not generated.
298                         // tying the error signal to 0.
299                         assign err_entropy_ready = 1'b 0;
300                     
301                         assign cfg_entropy_ready = 1'b 1;
302                     
303                         logic unused_cfg_entropy_ready;
304                         assign unused_cfg_entropy_ready = cfg_entropy_ready;
305                     
306                       end
307                     
308                       always_comb begin : recode_st
309        1/1              unique case (st)
           Tests:       T1 T2 T3 
310        1/1                StIdle       : stL = StIdleL;
           Tests:       T1 T2 T3 
311        1/1                StMsgFeed    : stL = StMsgFeedL;
           Tests:       T1 T2 T3 
312        1/1                StProcessing : stL = StProcessingL;
           Tests:       T1 T2 T3 
313        1/1                StAbsorbed   : stL = StAbsorbedL;
           Tests:       T1 T2 T3 
314        1/1                StSqueezing  : stL = StSqueezingL;
           Tests:       T20 T9 T10 
315                           default      : stL = StErrorL;
316                         endcase
317                       end : recode_st
318                     
319                       // Return error code
320                       err_t err;
321                       always_comb begin : err_return
322        1/1              err = '{valid: 1'b0, code: ErrNone, info: '0};
           Tests:       T1 T2 T3 
323                     
324        1/1              priority case (1'b 1)
           Tests:       T1 T2 T3 
325                           err_swsequence: begin
326        1/1                  err = '{ valid: 1'b 1,
           Tests:       T17 T26 T76 
327                                      code: ErrSwCmdSequence,
328                                      info: {5'h0,
329                                             {err_swsequence, err_modestrength, err_prefix},
330                                             {5'h 0, stL},
331                                             {2'b0, sw_cmd_i}
332                                            }
333                                    };
334                           end
335                     
336                           err_modestrength: begin
337        1/1                  err = '{ valid: 1'b 1,
           Tests:       T17 T26 T76 
338                                      code:  ErrUnexpectedModeStrength,
339                                      info:  { 5'h 0,
340                                               {err_swsequence, err_modestrength, err_prefix},
341                                               8'h 0,
342                                               {2'b 00, cfg_mode_i},
343                                               {1'b 0,  cfg_strength_i}
344                                             }
345                                    };
346                           end
347                     
348                           err_prefix: begin
349        1/1                  err = '{ valid: 1'b 1,
           Tests:       T17 T26 T76 
350                                      code:  ErrIncorrectFunctionName,
351                                      info:  { 5'h 0,
352                                               {err_swsequence, err_modestrength, err_prefix},
353                                               16'h 0000
354                                             }
355                                    };
356                           end
357                     
358                           err_entropy_ready: begin
359        0/1     ==>          err = '{ valid: 1'b 1,
360                                      code:  ErrSwHashingWithoutEntropyReady,
361                                      info:  { 8'({ err_entropy_ready,
362                                                    err_swsequence,
363                                                    err_modestrength,
364                                                    err_prefix}),
365                                               16'({kmac_en_i, cfg_entropy_ready})
366                                             }
367                                    };
368                           end
369                     
370                           default: begin
371                             err = '{valid: 1'b0, code: ErrNone, info: '0};
372                           end
373                         endcase
374                       end : err_return
375                     
376        1/1            assign error_o = err;
           Tests:       T1 T2 T3 
377                     
378                       // If below failed, revise err_swsequence error response info field.
379                       `ASSERT_INIT(ExpectedStSwCmdBits_A, $bits(st) == StateWidth && $bits(sw_cmd_i) == 6)
380                     
381                       // If failed, revise err_modestrength error info field.
382                       `ASSERT_INIT(ExpectedModeStrengthBits_A,
383                                    $bits(cfg_mode_i) == 2 && $bits(cfg_strength_i) == 3)
384                     
385                     
386                       ///////////////////
387                       // State Machine //
388                       ///////////////////
389                       st_e st_gated_d;
390                     
391        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_gated_d, st, st_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_gated_d, st, st_e, StIdle):
391.1                   `ifdef SIMULATION                                   
391.2                       prim_sparse_fsm_flop #(                           
391.3                         .StateEnumT(st_e),                            
391.4                         .Width($bits(st_e)),                          
391.5                         .ResetValue($bits(st_e)'(StIdle)),          
391.6                         .EnableAlertTriggerSVA(1), 
391.7                         .CustomForceName("st")          
391.8                       ) u_state_regs (                                        
391.9                         .clk_i   ( clk_i   ),                           
391.10                        .rst_ni  ( rst_ni ),                           
391.11                        .state_i ( st_gated_d     ),                           
391.12                        .state_o (         )                            
391.13                      );                                                
391.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
391.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
391.16     1/1                st <= StIdle;                                
           Tests:       T1 T2 T3 
391.17                      end else begin                                    
391.18     1/1                st <= st_gated_d;                                     
           Tests:       T1 T2 T3 
391.19                      end                                               
391.20                    end  
391.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o))       
391.22                      else begin                                                                           
391.23                        `ifdef UVM                                                                               
391.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
391.25                                              "../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv", 391, "", 1);                                
391.26                  `else                                                                                    
391.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
391.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
391.29                  `endif                                                              
391.30                      end 
391.31                    `else                                               
391.32                      prim_sparse_fsm_flop #(                           
391.33                        .StateEnumT(st_e),                            
391.34                        .Width($bits(st_e)),                          
391.35                        .ResetValue($bits(st_e)'(StIdle)),          
391.36                        .EnableAlertTriggerSVA(1)  
391.37                      ) u_state_regs (                                        
391.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
391.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
391.40                        .state_i ( st_gated_d     ),                           
391.41                        .state_o ( st     )                            
391.42                      );                                                
391.43                    `endif392                     
393                       // ICEBOX(#14631): Move block_swcmd to PRIM_FLOP_SPARSE_FSM()
394                       //
395                       // It would be better to place this condition (block_swcmd) in `always_ff`
396                       // block to clearly indicate the clock gating condition. However, the
397                       // statemachine uses the sparse encoding scheme and macro. It prevents any
398                       // latch enable signals.
399        1/1            assign st_gated_d = (block_swcmd) ? st : st_d ;
           Tests:       T1 T2 T3 
400                     
401                       always_comb begin : next_state
402        1/1              st_d = st;
           Tests:       T1 T2 T3 
403                     
404        1/1              unique case (st)
           Tests:       T1 T2 T3 
405                           StIdle: begin
406        1/1                  if (!app_active_i && sw_cmd_i == CmdStart) begin
           Tests:       T1 T2 T3 
407                               // Proceed to the next state only when the SW issues the Start command
408                               // in a valid period.
409        1/1                    st_d = StMsgFeed;
           Tests:       T1 T2 T3 
410                             end
                        MISSING_ELSE
411                           end
412                     
413                           StMsgFeed: begin
414        1/1                  if (sw_cmd_i == CmdProcess) begin
           Tests:       T1 T2 T3 
415        1/1                    st_d = StProcessing;
           Tests:       T1 T2 T3 
416                             end
                        MISSING_ELSE
417                           end
418                     
419                           StProcessing: begin
420        1/1                  if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i)) begin
           Tests:       T1 T2 T3 
421        1/1                    st_d = StAbsorbed;
           Tests:       T1 T2 T3 
422                             end
                        MISSING_ELSE
423                           end
424                     
425                           StAbsorbed: begin
426        1/1                  if (sw_cmd_i == CmdManualRun) begin
           Tests:       T1 T2 T3 
427        1/1                    st_d = StSqueezing;
           Tests:       T20 T9 T10 
428        1/1                  end else if (sw_cmd_i == CmdDone) begin
           Tests:       T1 T2 T3 
429        1/1                    st_d = StIdle;
           Tests:       T1 T2 T3 
430                             end
                        MISSING_ELSE
431                           end
432                     
433                           StSqueezing: begin
434        1/1                  if (keccak_done_i) begin
           Tests:       T20 T9 T10 
435        1/1                    st_d = StAbsorbed;
           Tests:       T20 T9 T10 
436                             end
                        MISSING_ELSE
437                           end
438                     
439                           StTerminalError: begin
440                             // this state is terminal
441        1/1                  st_d = st;
           Tests:       T9 T15 T16 
442                           end
443                     
444                           default: begin
445                             // this state is terminal
446                             st_d = StTerminalError;
447                           end
448                         endcase
449                     
450                         // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC
451                         // Unconditionally jump into the terminal error state
452                         // if the life cycle controller triggers an escalation.
453        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
           Tests:       T1 T2 T3 
454        1/1                st_d = StTerminalError;
           Tests:       T9 T15 T16 
455                         end
                        MISSING_ELSE
456                     
457        1/1              if (st_d != StTerminalError &&
           Tests:       T1 T2 T3 
458                             prim_mubi_pkg::mubi4_test_true_strict(clear_after_error_i)) begin
459        1/1                st_d = StIdle;
           Tests:       T7 T4 T8 
460                         end
                        MISSING_ELSE

---

Cond Coverage for Module : kmac_errchk

	Total	Covered	Percent
Conditions	74	70	94.59
Logical	74	70	94.59
Non-Logical	0	0
Event	0	0

 LINE       206
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       219
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------

-1-	Status	Tests
0	Covered	T20,T9,T10
1	Not Covered

 LINE       236
 EXPRESSION (err_swsequence || (err_modestrength && ((!cfg_en_unsupported_modestrength_i))) || err_entropy_ready)
             -------1------    ------------------------------2-----------------------------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T17,T26,T76
1	0	0	Covered	T17,T26,T76

 LINE       236
 SUB-EXPRESSION (err_modestrength && ((!cfg_en_unsupported_modestrength_i)))
                 --------1-------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T26,T76
1	1	Covered	T17,T26,T76

 LINE       252
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed))
             -------1------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       252
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       252
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION 
 Number  Term
      1  (((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))) )

-1-	Status	Tests
0	Covered	T17,T26,T76
1	Covered	T1,T2,T3

 LINE       254
 SUB-EXPRESSION 
 Number  Term
      1  ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || 
      2  (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))

-1-	-2-	Status	Tests
0	0	Covered	T17,T26,T76
0	1	Covered	T30,T31,T20
1	0	Covered	T1,T2,T3

 LINE       254
 SUB-EXPRESSION ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512}))
                 ----------1---------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T20
1	0	Covered	T17,T26,T76
1	1	Covered	T1,T2,T3

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == Sha3)
                ----------1---------

-1-	Status	Tests
0	Covered	T30,T31,T20
1	Covered	T1,T2,T3

 LINE       254
 SUB-EXPRESSION (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))
                 ------------------------1------------------------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T29,T47
1	0	Covered	T17,T26,T76
1	1	Covered	T30,T31,T20

 LINE       254
 SUB-EXPRESSION ((cfg_mode_i == Shake) || (cfg_mode_i == CShake))
                 ----------1----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T20
1	0	Covered	T20,T29,T9

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == Shake)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T29,T9

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == CShake)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T20

 LINE       268
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T31,T20
1	0	1	Covered	T30,T31,T20
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T30,T31,T20

 LINE       268
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       268
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       269
 EXPRESSION (cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T30,T31,T20
1	Covered	T17,T26,T76

 LINE       280
 EXPRESSION (entropy_ready_pulse_i && (st == StIdle))
             ----------1----------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       280
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T31,T20
1	0	1	Covered	T30,T31,T20
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T30,T31,T20

 LINE       288
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       288
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (block_swcmd ? st : st_d)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T26,T76

 LINE       406
 EXPRESSION (((!app_active_i)) && (sw_cmd_i == CmdStart))
             --------1--------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       406
 SUB-EXPRESSION (sw_cmd_i == CmdStart)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (sw_cmd_i == CmdProcess)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (sw_cmd_i == CmdManualRun)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T9,T10

 LINE       428
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : kmac_errchk

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorbed	421	Covered	T1,T2,T3
StIdle	429	Covered	T1,T2,T3
StMsgFeed	409	Covered	T1,T2,T3
StProcessing	415	Covered	T1,T2,T3
StSqueezing	427	Covered	T20,T9,T10
StTerminalError	454	Covered	T9,T15,T16

transitions	Line No.	Covered	Tests
StAbsorbed->StIdle	429	Covered	T1,T2,T3
StAbsorbed->StSqueezing	427	Covered	T20,T9,T10
StAbsorbed->StTerminalError	454	Covered	T62,T63,T64
StIdle->StMsgFeed	409	Covered	T1,T2,T3
StIdle->StTerminalError	454	Covered	T15,T40,T41
StMsgFeed->StIdle	459	Not Covered
StMsgFeed->StProcessing	415	Covered	T1,T2,T3
StMsgFeed->StTerminalError	454	Covered	T9,T16,T42
StProcessing->StAbsorbed	421	Covered	T1,T2,T3
StProcessing->StIdle	459	Covered	T68,T69,T77
StProcessing->StTerminalError	454	Covered	T78
StSqueezing->StAbsorbed	435	Covered	T20,T9,T10
StSqueezing->StIdle	459	Not Covered
StSqueezing->StTerminalError	454	Not Covered
StTerminalError->StIdle	459	Covered	T9,T15,T16

---

Branch Coverage for Module : kmac_errchk

	Line No.	Total	Covered	Percent
Branches		60	56	93.33
TERNARY	399	2	2	100.00
CASE	190	12	10	83.33
IF	244	3	3	100.00
IF	252	3	3	100.00
IF	268	3	3	100.00
CASE	309	6	6	100.00
CASE	324	5	4	80.00
IF	391	2	2	100.00
CASE	404	13	13	100.00
IF	453	2	2	100.00
IF	457	2	2	100.00
IF	278	4	4	100.00
IF	288	3	2	66.67

399          assign st_gated_d = (block_swcmd) ? st : st_d ;
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T17,T26,T76
0	Covered	T1,T2,T3

190            unique case (st)
                      -1-  
191              StIdle: begin
192                // Allow Start command only
193                if (!(sw_cmd_i inside {CmdNone, CmdStart})) begin
                   -2-  
194                  err_swsequence = 1'b 1;
                     ==>
195                end
                   MISSING_ELSE
                   ==>
196              end
197        
198              StMsgFeed: begin
199                // Allow Process only
200                if (!(sw_cmd_i inside {CmdNone, CmdProcess})) begin
                   -3-  
201                  err_swsequence = 1'b 1;
                     ==>
202                end
                   MISSING_ELSE
                   ==>
203              end
204        
205              StProcessing: begin
206                if (sw_cmd_i != CmdNone) begin
                   -4-  
207                  err_swsequence = 1'b 1;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210        
211              StAbsorbed: begin
212                // Allow ManualRun and Done
213                if (!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone})) begin
                   -5-  
214                  err_swsequence = 1'b 1;
                     ==>
215                end
                   MISSING_ELSE
                   ==>
216              end
217        
218              StSqueezing: begin
219                if (sw_cmd_i != CmdNone) begin
                   -6-  
220                  err_swsequence = 1'b 1;
                     ==>
221                end
                   MISSING_ELSE
                   ==>
222              end
223        
224              StTerminalError: begin
225                err_swsequence = 1'b 0;
                   ==>
226                sparse_fsm_error_o = 1'b 1;
227              end
228        
229              default: begin
230                err_swsequence = 1'b 0;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	-	-	-	-	Covered	T17,T26,T76
StIdle	0	-	-	-	-	Covered	T1,T2,T3
StMsgFeed	-	1	-	-	-	Covered	T17,T26,T18
StMsgFeed	-	0	-	-	-	Covered	T1,T2,T3
StProcessing	-	-	1	-	-	Not Covered
StProcessing	-	-	0	-	-	Covered	T1,T2,T3
StAbsorbed	-	-	-	1	-	Covered	T17,T26,T18
StAbsorbed	-	-	-	0	-	Covered	T1,T2,T3
StSqueezing	-	-	-	-	1	Not Covered
StSqueezing	-	-	-	-	0	Covered	T20,T9,T10
StTerminalError	-	-	-	-	-	Covered	T9,T15,T16
default	-	-	-	-	-	Covered	T15,T40,T41

244            if (!rst_ni)           sw_cmd_o <= CmdNone;
               -1-  
               ==>
245            else if (!block_swcmd) sw_cmd_o <= sw_cmd_i;
                    -2-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T17,T26,T76

252            if (st == StIdle && st_d == StMsgFeed) begin
               -1-  
253              // When moving to the next stage, checks the config
254              if (!((cfg_mode_i == Sha3 &&
                 -2-  
255                     cfg_strength_i inside {L224, L256, L384, L512}) ||
256                    ((cfg_mode_i == Shake || cfg_mode_i == CShake) &&
257                     (cfg_strength_i inside {L128, L256})))) begin
258                err_modestrength = 1'b 1;
                   ==>
259              end
                 MISSING_ELSE
                 ==>
260            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T17,T26,T76
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

268            if (st == StIdle && st_d == StMsgFeed && kmac_en_i) begin
               -1-  
269              if (cfg_prefix_6B_i != EncodedStringKMAC) begin
                 -2-  
270                err_prefix = 1'b 1;
                   ==>
271              end
                 MISSING_ELSE
                 ==>
272            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T17,T26,T76
1	0	Covered	T30,T31,T20
0	-	Covered	T1,T2,T3

309            unique case (st)
                      -1-  
310              StIdle       : stL = StIdleL;
                 ==>
311              StMsgFeed    : stL = StMsgFeedL;
                 ==>
312              StProcessing : stL = StProcessingL;
                 ==>
313              StAbsorbed   : stL = StAbsorbedL;
                 ==>
314              StSqueezing  : stL = StSqueezingL;
                 ==>
315              default      : stL = StErrorL;
                 ==>

Branches:

-1-	Status	Tests
StIdle	Covered	T1,T2,T3
StMsgFeed	Covered	T1,T2,T3
StProcessing	Covered	T1,T2,T3
StAbsorbed	Covered	T1,T2,T3
StSqueezing	Covered	T20,T9,T10
default	Covered	T9,T15,T16

324            priority case (1'b 1)
                        -1-  
325              err_swsequence: begin
326                err = '{ valid: 1'b 1,
                   ==>
327                         code: ErrSwCmdSequence,
328                         info: {5'h0,
329                                {err_swsequence, err_modestrength, err_prefix},
330                                {5'h 0, stL},
331                                {2'b0, sw_cmd_i}
332                               }
333                       };
334              end
335        
336              err_modestrength: begin
337                err = '{ valid: 1'b 1,
                   ==>
338                         code:  ErrUnexpectedModeStrength,
339                         info:  { 5'h 0,
340                                  {err_swsequence, err_modestrength, err_prefix},
341                                  8'h 0,
342                                  {2'b 00, cfg_mode_i},
343                                  {1'b 0,  cfg_strength_i}
344                                }
345                       };
346              end
347        
348              err_prefix: begin
349                err = '{ valid: 1'b 1,
                   ==>
350                         code:  ErrIncorrectFunctionName,
351                         info:  { 5'h 0,
352                                  {err_swsequence, err_modestrength, err_prefix},
353                                  16'h 0000
354                                }
355                       };
356              end
357        
358              err_entropy_ready: begin
359                err = '{ valid: 1'b 1,
                   ==>
360                         code:  ErrSwHashingWithoutEntropyReady,
361                         info:  { 8'({ err_entropy_ready,
362                                       err_swsequence,
363                                       err_modestrength,
364                                       err_prefix}),
365                                  16'({kmac_en_i, cfg_entropy_ready})
366                                }
367                       };
368              end
369        
370              default: begin
371                err = '{valid: 1'b0, code: ErrNone, info: '0};
                   ==>

Branches:

-1-	Status	Tests
err_swsequence	Covered	T17,T26,T76
err_modestrength	Covered	T17,T26,T76
err_prefix	Covered	T17,T26,T76
err_entropy_ready	Not Covered
default	Covered	T1,T2,T3

391          `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_gated_d, st, st_e, StIdle)
             -1-                                                                 
             ==>                                                                 
             ==>                                                                 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

404            unique case (st)
                      -1-  
405              StIdle: begin
406                if (!app_active_i && sw_cmd_i == CmdStart) begin
                   -2-  
407                  // Proceed to the next state only when the SW issues the Start command
408                  // in a valid period.
409                  st_d = StMsgFeed;
                     ==>
410                end
                   MISSING_ELSE
                   ==>
411              end
412        
413              StMsgFeed: begin
414                if (sw_cmd_i == CmdProcess) begin
                   -3-  
415                  st_d = StProcessing;
                     ==>
416                end
                   MISSING_ELSE
                   ==>
417              end
418        
419              StProcessing: begin
420                if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i)) begin
                   -4-  
421                  st_d = StAbsorbed;
                     ==>
422                end
                   MISSING_ELSE
                   ==>
423              end
424        
425              StAbsorbed: begin
426                if (sw_cmd_i == CmdManualRun) begin
                   -5-  
427                  st_d = StSqueezing;
                     ==>
428                end else if (sw_cmd_i == CmdDone) begin
                            -6-  
429                  st_d = StIdle;
                     ==>
430                end
                   MISSING_ELSE
                   ==>
431              end
432        
433              StSqueezing: begin
434                if (keccak_done_i) begin
                   -7-  
435                  st_d = StAbsorbed;
                     ==>
436                end
                   MISSING_ELSE
                   ==>
437              end
438        
439              StTerminalError: begin
440                // this state is terminal
441                st_d = st;
                   ==>
442              end
443        
444              default: begin
445                // this state is terminal
446                st_d = StTerminalError;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	Covered	T1,T2,T3
StMsgFeed	-	1	-	-	-	-	Covered	T1,T2,T3
StMsgFeed	-	0	-	-	-	-	Covered	T1,T2,T3
StProcessing	-	-	1	-	-	-	Covered	T1,T2,T3
StProcessing	-	-	0	-	-	-	Covered	T1,T2,T3
StAbsorbed	-	-	-	1	-	-	Covered	T20,T9,T10
StAbsorbed	-	-	-	0	1	-	Covered	T1,T2,T3
StAbsorbed	-	-	-	0	0	-	Covered	T1,T2,T3
StSqueezing	-	-	-	-	-	1	Covered	T20,T9,T10
StSqueezing	-	-	-	-	-	0	Covered	T20,T9,T10
StTerminalError	-	-	-	-	-	-	Covered	T9,T15,T16
default	-	-	-	-	-	-	Covered	T15,T40,T41

453            if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
               -1-  
454              st_d = StTerminalError;
                 ==>
455            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T15,T16
0	Covered	T1,T2,T3

457            if (st_d != StTerminalError &&
               -1-  
458                prim_mubi_pkg::mubi4_test_true_strict(clear_after_error_i)) begin
459              st_d = StIdle;
                 ==>
460            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T4,T8
0	Covered	T1,T2,T3

278              if (!rst_ni)              cfg_entropy_ready <= 1'b 0;
                 -1-  
                 ==>
279              else if (err_processed_i) cfg_entropy_ready <= 1'b 0;
                      -2-  
                 ==>
280              else if (entropy_ready_pulse_i && st == StIdle) begin
                      -3-  
281                cfg_entropy_ready <= 1'b 1;
                   ==>
282              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T44,T45
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

288              if (st == StIdle && st_d == StMsgFeed && kmac_en_i) begin
                 -1-  
289                if (!cfg_entropy_ready) begin
                   -2-  
290                  err_entropy_ready = 1'b 1;
                     ==>
291                end
                   MISSING_ELSE
                   ==>
292              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T30,T31,T20
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_errchk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ExpectedModeStrengthBits_A	665	665	0	0
ExpectedStSwCmdBits_A	665	665	0	0
StKnown_A	640180531	640001293	0	0
u_state_regs_A	640180531	640001293	0	0

ExpectedModeStrengthBits_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

ExpectedStSwCmdBits_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

StKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0