KMAC/UNMASKED Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.031m	2.978ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	34.396us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.140s	194.118us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.710s	6.452ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.040s	638.222us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.340s	110.828us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.140s	194.118us	20	20	100.00
		kmac_csr_aliasing	9.040s	638.222us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	26.305us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.410s	36.917us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.237m	609.447ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.707m	35.566ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.559m	984.157ms	50	50	100.00
		kmac_test_vectors_sha3_256	31.481m	191.942ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.241m	147.107ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.189m	232.449ms	50	50	100.00
		kmac_test_vectors_shake_128	1.535h	260.144ms	50	50	100.00
		kmac_test_vectors_shake_256	1.306h	947.676ms	50	50	100.00
		kmac_test_vectors_kmac	5.670s	2.038ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.360s	2.036ms	50	50	100.00
V2	sideload	kmac_sideload	7.149m	183.336ms	50	50	100.00
V2	app	kmac_app	6.287m	38.420ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.431m	39.682ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.659m	74.616ms	48	50	96.00
V2	error	kmac_error	6.682m	29.006ms	50	50	100.00
V2	key_error	kmac_key_error	7.150s	4.951ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.820s	1.985ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	32.450s	1.685ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.225m	33.748ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.790s	2.649ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.886m	535.237ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.810s	19.219us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	151.142us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.030s	1.308ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.030s	1.308ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	34.396us	5	5	100.00
		kmac_csr_rw	1.140s	194.118us	20	20	100.00
		kmac_csr_aliasing	9.040s	638.222us	5	5	100.00
		kmac_same_csr_outstanding	2.650s	97.608us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	34.396us	5	5	100.00
		kmac_csr_rw	1.140s	194.118us	20	20	100.00
		kmac_csr_aliasing	9.040s	638.222us	5	5	100.00
		kmac_same_csr_outstanding	2.650s	97.608us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.990s	317.917us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.990s	317.917us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.990s	317.917us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.990s	317.917us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.410s	1.760ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	51.110s	13.068ms	5	5	100.00
		kmac_tl_intg_err	5.430s	257.251us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.430s	257.251us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.790s	2.649ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.031m	2.978ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.149m	183.336ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.990s	317.917us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	51.110s	13.068ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	51.110s	13.068ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	51.110s	13.068ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.031m	2.978ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.790s	2.649ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	51.110s	13.068ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.144m	80.743ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.031m	2.978ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	49.079m	72.908ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1274	1290	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.47	96.65	92.52	100.00	88.64	94.67	98.82	97.02

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 11 failures:

Test kmac_stress_all_with_rand_reset has 11 failures.

14.kmac_stress_all_with_rand_reset.608930167
Line 1363, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 52602709663 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 52602709663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_stress_all_with_rand_reset.1202144672
Line 467, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16892161567 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 16892161567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 1 failures.

4.kmac_entropy_refresh.319796951
Line 354, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 37094841307 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (49 [0x31] vs 228 [0xe4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 37094841307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

7.kmac_mubi.3232535129
Line 301, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_mubi/latest/run.log

  UVM_FATAL @ 34896862559 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (164 [0xa4] vs 86 [0x56]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 34896862559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

9.kmac_stress_all_with_rand_reset.3186066064
Line 537, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 57216582514 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (37 [0x25] vs 128 [0x80]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 57216582514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 31.kmac_stress_all_with_rand_reset.2001952011
    Line 463, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14067911796 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (181 [0xb5] vs 250 [0xfa]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 14067911796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 36.kmac_entropy_refresh.4229256411
    Line 391, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```