Unified Coverage Report :: Module :: sha3

Module : sha3

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_sha3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.74	0.00	0.00	8.70	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak	0.00	0.00	0.00	0.00	0.00	0.00
u_pad	0.00	0.00	0.00	0.00	0.00	0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : sha3

	Line No.	Total	Covered	Percent
TOTAL		74	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	137	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	159	1	0	0.00
ALWAYS	166	3	0	0.00
CONT_ASSIGN	171	1	0	0.00
ALWAYS	175	6	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	185	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
CONT_ASSIGN	188	1	0	0.00
ALWAYS	195	3	0	0.00
ALWAYS	205	38	0	0.00
ALWAYS	300	3	0	0.00
ALWAYS	317	12	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
131	0	1
137	0	1
141	0	1
159	0	1
166	0	2
167	0	1
171	0	1
175	0	2
176	0	2
177	0	1
178	0	1
			==> MISSING_ELSE
182	0	1
185	0	1
186	0	1
188	0	1
195	0	3
205	0	1
208	0	1
209	0	1
210	0	1
211	0	1
213	0	1
215	0	1
216	0	1
218	0	1
220	0	1
222	0	1
223	0	1
225	0	1
227	0	1
232	0	1
233	0	1
235	0	1
236	0	1
237	0	1
239	0	1
244	0	1
245	0	1
247	0	1
249	0	1
250	0	1
252	0	1
253	0	1
254	0	1
256	0	1
258	0	1
263	0	1
264	0	1
266	0	1
271	0	1
276	0	1
277	0	1
289	0	1
290	0	1
			==> MISSING_ELSE
300	0	1
301	0	1
302	0	1
317	0	1
319	0	1
321	0	1
323	0	1
			==> MISSING_ELSE
332	0	1
334	0	1
			==> MISSING_ELSE
343	0	1
344	0	1
			==> MISSING_ELSE
353	0	1
355	0	1
			==> MISSING_ELSE
364	0	1
366	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : sha3

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       131
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       137
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       159
 EXPRESSION (sha3pad_keccak_run | sw_keccak_run)
             ---------1--------   ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       232
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       343
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Module : sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	223	Not Covered
StFlush_sparse	254	Not Covered
StIdle_sparse	227	Not Covered
StManualRun_sparse	250	Not Covered
StSqueeze_sparse	237	Not Covered
StTerminalError_sparse	276	Not Covered

transitions	Line No.	Covered	Tests
StAbsorb_sparse->StSqueeze_sparse	237	Not Covered
StAbsorb_sparse->StTerminalError_sparse	290	Not Covered
StFlush_sparse->StIdle_sparse	271	Not Covered
StFlush_sparse->StTerminalError_sparse	290	Not Covered
StIdle_sparse->StAbsorb_sparse	223	Not Covered
StIdle_sparse->StTerminalError_sparse	290	Not Covered
StManualRun_sparse->StSqueeze_sparse	264	Not Covered
StManualRun_sparse->StTerminalError_sparse	290	Not Covered
StSqueeze_sparse->StFlush_sparse	254	Not Covered
StSqueeze_sparse->StManualRun_sparse	250	Not Covered
StSqueeze_sparse->StTerminalError_sparse	290	Not Covered

---

Branch Coverage for Module : sha3

	Line No.	Total	Covered	Percent
Branches		37	0	0.00
IF	166	2	0	0.00
IF	175	4	0	0.00
IF	195	2	0	0.00
CASE	220	13	0	0.00
IF	289	2	0	0.00
CASE	300	3	0	0.00
CASE	319	11	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	166	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	175	if ((!rst_ni))
-2-:	176	if (process_i)
-3-:	177	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	195	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	220	case (st)
-2-:	222	if (start_i)
-3-:	232	if ((process_i && (!processing)))
-4-:	236	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	249	if (run_i)
-6-:	253	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	263	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Not Covered
StIdle_sparse	0	-	-	-	-	-	Not Covered
StAbsorb_sparse	-	1	-	-	-	-	Not Covered
StAbsorb_sparse	-	0	1	-	-	-	Not Covered
StAbsorb_sparse	-	0	0	-	-	-	Not Covered
StSqueeze_sparse	-	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	-	0	1	-	Not Covered
StSqueeze_sparse	-	-	-	0	0	-	Not Covered
StManualRun_sparse	-	-	-	-	-	1	Not Covered
StManualRun_sparse	-	-	-	-	-	0	Not Covered
StFlush_sparse	-	-	-	-	-	-	Not Covered
StTerminalError_sparse	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	289	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	300	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Not Covered
MuxRelease	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	319	case (st)
-2-:	321	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	332	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	343	if ((start_i || process_i))
-5-:	353	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	364	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Not Covered
StIdle_sparse	0	-	-	-	-	Not Covered
StAbsorb_sparse	-	1	-	-	-	Not Covered
StAbsorb_sparse	-	0	-	-	-	Not Covered
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Not Covered
StManualRun_sparse	-	-	-	1	-	Not Covered
StManualRun_sparse	-	-	-	0	-	Not Covered
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
TOTAL		74	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	137	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	159	1	0	0.00
ALWAYS	166	3	0	0.00
CONT_ASSIGN	171	1	0	0.00
ALWAYS	175	6	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	185	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
CONT_ASSIGN	188	1	0	0.00
ALWAYS	195	3	0	0.00
ALWAYS	205	38	0	0.00
ALWAYS	300	3	0	0.00
ALWAYS	317	12	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
131	0	1
137	0	1
141	0	1
159	0	1
166	0	2
167	0	1
171	0	1
175	0	2
176	0	2
177	0	1
178	0	1
			==> MISSING_ELSE
182	0	1
185	0	1
186	0	1
188	0	1
195	0	3
205	0	1
208	0	1
209	0	1
210	0	1
211	0	1
213	0	1
215	0	1
216	0	1
218	0	1
220	0	1
222	0	1
223	0	1
225	0	1
227	0	1
232	0	1
233	0	1
235	0	1
236	0	1
237	0	1
239	0	1
244	0	1
245	0	1
247	0	1
249	0	1
250	0	1
252	0	1
253	0	1
254	0	1
256	0	1
258	0	1
263	0	1
264	0	1
266	0	1
271	0	1
276	0	1
277	0	1
289	0	1
290	0	1
			==> MISSING_ELSE
300	0	1
301	0	1
302	0	1
317	0	1
319	0	1
321	0	1
323	0	1
			==> MISSING_ELSE
332	0	1
334	0	1
			==> MISSING_ELSE
343	0	1
344	0	1
			==> MISSING_ELSE
353	0	1
355	0	1
			==> MISSING_ELSE
364	0	1
366	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       131
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       137
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       159
 EXPRESSION (sha3pad_keccak_run | sw_keccak_run)
             ---------1--------   ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       232
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       343
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	223	Not Covered
StFlush_sparse	254	Not Covered
StIdle_sparse	227	Not Covered
StManualRun_sparse	250	Not Covered
StSqueeze_sparse	237	Not Covered
StTerminalError_sparse	276	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
StAbsorb_sparse->StSqueeze_sparse	237	Not Covered
StAbsorb_sparse->StTerminalError_sparse	290	Not Covered
StFlush_sparse->StIdle_sparse	271	Not Covered
StFlush_sparse->StTerminalError_sparse	290	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse	223	Not Covered
StIdle_sparse->StTerminalError_sparse	290	Not Covered
StManualRun_sparse->StSqueeze_sparse	264	Not Covered
StManualRun_sparse->StTerminalError_sparse	290	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse	254	Not Covered
StSqueeze_sparse->StManualRun_sparse	250	Not Covered
StSqueeze_sparse->StTerminalError_sparse	290	Not Covered

---

Branch Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
Branches		37	0	0.00
IF	166	2	0	0.00
IF	175	4	0	0.00
IF	195	2	0	0.00
CASE	220	13	0	0.00
IF	289	2	0	0.00
CASE	300	3	0	0.00
CASE	319	11	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	166	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	175	if ((!rst_ni))
-2-:	176	if (process_i)
-3-:	177	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	195	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	220	case (st)
-2-:	222	if (start_i)
-3-:	232	if ((process_i && (!processing)))
-4-:	236	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	249	if (run_i)
-6-:	253	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	263	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Not Covered
StIdle_sparse	0	-	-	-	-	-	Not Covered
StAbsorb_sparse	-	1	-	-	-	-	Not Covered
StAbsorb_sparse	-	0	1	-	-	-	Not Covered
StAbsorb_sparse	-	0	0	-	-	-	Not Covered
StSqueeze_sparse	-	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	-	0	1	-	Not Covered
StSqueeze_sparse	-	-	-	0	0	-	Not Covered
StManualRun_sparse	-	-	-	-	-	1	Not Covered
StManualRun_sparse	-	-	-	-	-	0	Not Covered
StFlush_sparse	-	-	-	-	-	-	Not Covered
StTerminalError_sparse	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	289	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	300	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Not Covered
MuxRelease	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	319	case (st)
-2-:	321	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	332	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	343	if ((start_i || process_i))
-5-:	353	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	364	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Not Covered
StIdle_sparse	0	-	-	-	-	Not Covered
StAbsorb_sparse	-	1	-	-	-	Not Covered
StAbsorb_sparse	-	0	-	-	-	Not Covered
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Not Covered
StManualRun_sparse	-	-	-	1	-	Not Covered
StManualRun_sparse	-	-	-	0	-	Not Covered
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered