Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.11	0.00	0.00	5.54	0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	1.74	0.00	0.00	8.70	0.00	0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.74	0.00	0.00	8.70	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.76	49.31	65.68	16.53	0.00	49.06	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	0.00	0.00	0.00			0.00
intr_kmac_done	0.00	0.00	0.00			0.00
intr_kmac_err	0.00	0.00	0.00			0.00
kmac_csr_assert	100.00						100.00
tlul_assert_device	33.33	0.00				0.00	100.00
u_app_intf	0.00	0.00	0.00		0.00	0.00
u_errchk	0.00	0.00	0.00		0.00	0.00
u_kmac_core	0.00	0.00	0.00	0.00	0.00	0.00
u_msgfifo	0.00	0.00	0.00		0.00	0.00
u_prim_lc_sync	0.00	0.00				0.00
u_reg	94.16	99.11	96.47	76.26		98.94	100.00
u_sha3	0.00	0.00	0.00	0.00	0.00	0.00
u_sha3_done_sender	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00
u_staterd	0.00	0.00	0.00			0.00
u_tlul_adapter_msgfifo	0.00	0.00	0.00			0.00

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		163	0	0.00
ALWAYS	346	0	0
ALWAYS	346	2	0	0.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	0	0.00
CONT_ASSIGN	422	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
ALWAYS	429	9	0	0.00
CONT_ASSIGN	464	1	0	0.00
CONT_ASSIGN	465	1	0	0.00
CONT_ASSIGN	466	1	0	0.00
CONT_ASSIGN	469	1	0	0.00
CONT_ASSIGN	473	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	478	1	0	0.00
CONT_ASSIGN	481	1	0	0.00
ALWAYS	488	6	0	0.00
CONT_ASSIGN	513	1	0	0.00
CONT_ASSIGN	518	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	528	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	530	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	537	1	0	0.00
CONT_ASSIGN	539	0	0
CONT_ASSIGN	541	1	0	0.00
CONT_ASSIGN	545	1	0	0.00
CONT_ASSIGN	547	1	0	0.00
CONT_ASSIGN	548	1	0	0.00
CONT_ASSIGN	551	1	0	0.00
CONT_ASSIGN	552	1	0	0.00
CONT_ASSIGN	555	1	0	0.00
ALWAYS	563	5	0	0.00
CONT_ASSIGN	573	1	0	0.00
CONT_ASSIGN	580	1	0	0.00
CONT_ASSIGN	581	1	0	0.00
CONT_ASSIGN	582	1	0	0.00
CONT_ASSIGN	592	1	0	0.00
ALWAYS	612	3	0	0.00
CONT_ASSIGN	616	1	0	0.00
CONT_ASSIGN	635	1	0	0.00
CONT_ASSIGN	640	1	0	0.00
ALWAYS	643	7	0	0.00
CONT_ASSIGN	679	1	0	0.00
CONT_ASSIGN	684	1	0	0.00
CONT_ASSIGN	691	1	0	0.00
CONT_ASSIGN	701	1	0	0.00
ALWAYS	721	3	0	0.00
ALWAYS	725	28	0	0.00
CONT_ASSIGN	875	1	0	0.00
CONT_ASSIGN	878	1	0	0.00
CONT_ASSIGN	942	1	0	0.00
CONT_ASSIGN	944	1	0	0.00
CONT_ASSIGN	974	1	0	0.00
CONT_ASSIGN	979	1	0	0.00
CONT_ASSIGN	980	1	0	0.00
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	985	0	0
ALWAYS	1103	0	0
ALWAYS	1103	2	0	0.00
CONT_ASSIGN	1255	1	0	0.00
CONT_ASSIGN	1256	1	0	0.00
CONT_ASSIGN	1257	1	0	0.00
CONT_ASSIGN	1266	1	0	0.00
CONT_ASSIGN	1272	1	0	0.00
CONT_ASSIGN	1273	1	0	0.00
CONT_ASSIGN	1274	1	0	0.00
CONT_ASSIGN	1275	1	0	0.00
CONT_ASSIGN	1278	1	0	0.00
CONT_ASSIGN	1287	1	0	0.00
CONT_ASSIGN	1331	1	0	0.00
CONT_ASSIGN	1345	1	0	0.00
CONT_ASSIGN	1352	1	0	0.00
CONT_ASSIGN	1357	1	0	0.00
ALWAYS	1363	6	0	0.00
CONT_ASSIGN	1372	1	0	0.00
CONT_ASSIGN	1374	1	0	0.00
ALWAYS	1386	4	0	0.00
CONT_ASSIGN	1392	1	0	0.00
ALWAYS	1415	4	0	0.00
ALWAYS	1425	3	0	0.00
CONT_ASSIGN	1436	1	0	0.00
CONT_ASSIGN	1440	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	0	1
347	0	1
352	0	1
421	0	1
422	0	1
426	0	1
429	0	1
430	0	1
431	0	1
432	0	1
434	0	1
436	0	1
440	0	1
444	0	1
448	0	1
464	0	1
465	0	1
466	0	1
469	0	1
473	0	1
474	0	1
478	0	1
481	0	1
488	0	1
489	0	1
490	0	1
491	0	1
492	0	1
493	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
513	0	1
518	0	1
525	0	1
528	0	1
529	0	1
530	0	1
533	0	5
534	0	5
537	0	1
539		unreachable
541	0	1
545	0	1
547	0	1
548	0	1
551	0	1
552	0	1
555	0	1
563	0	1
564	0	1
565	0	1
566	0	1
568	0	1
573	0	1
580	0	1
581	0	1
582	0	1
592	0	1
612	0	2
613	0	1
616	0	1
635	0	1
640	0	1
643	0	1
645	0	1
650	0	1
654	0	1
658	0	1
662	0	1
666	0	1
679	0	1
684	0	1
691	0	1
701	0	1
721	0	3
725	0	1
727	0	1
728	0	1
730	0	1
732	0	1
734	0	1
735	0	1
738	0	1
741	0	1
747	0	1
748	0	1
750	0	1
755	0	1
756	0	1
757	0	1
759	0	1
765	0	1
770	0	1
771	0	1
773	0	1
775	0	1
781	0	1
782	0	1
784	0	1
790	0	1
791	0	1
803	0	1
804	0	1
			==> MISSING_ELSE
875	0	1
878	0	1
942	0	1
944	0	1
974	0	1
979	0	1
980	0	1
982	0	1
985		unreachable
1103	0	1
1104	0	1
1255	0	1
1256	0	1
1257	0	1
1266	0	1
1272	0	1
1273	0	1
1274	0	1
1275	0	1
1278	0	1
1287	0	1
1331	0	1
1345	0	1
1352	0	1
1357	0	1
1363	0	1
1364	0	1
1365	0	1
1366	0	1
1367	0	1
1368	0	1
			==> MISSING_ELSE
1372	0	1
1374	0	1
1386	0	1
1387	0	1
1388	0	1
1389	0	1
			==> MISSING_ELSE
1392	0	1
1415	0	1
1416	0	1
1417	0	1
1419	0	1
			==> MISSING_ELSE
1425	0	1
1426	0	1
1429	0	1
1436	0	1
1440	0	1
1442	0	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	74	0	0.00
Logical	74	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       541
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       545
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       552
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       565
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       565
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       565
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Not Covered
1	-	Not Covered

 LINE       573
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       616
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       635
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       679
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Unreachable
1	0	0	0	Not Covered

 LINE       691
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       732
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       734
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       748
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       974
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1104
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1374
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Not Covered
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	38	53.52
Total Bits	6534	362	5.54
Total Bits 0->1	3267	181	5.54
Total Bits 1->0	3267	181	5.54

Ports	71	38	53.52
Port Bits	6534	362	5.54
Port Bits 0->1	3267	181	5.54
Port Bits 1->0	3267	181	5.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T6	Yes	T1,T2,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T5,T7	Yes	T2,T5,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
keymgr_key_i.key[1:0][255:0]	No	No		No		INPUT
keymgr_key_i.valid	No	No		No		INPUT
app_i[0].last	No	No		No		INPUT
app_i[0].strb[7:0]	No	No		No		INPUT
app_i[0].data[63:0]	No	No		No		INPUT
app_i[0].valid	No	No		No		INPUT
app_i[1].last	No	No		No		INPUT
app_i[1].strb[7:0]	No	No		No		INPUT
app_i[1].data[63:0]	No	No		No		INPUT
app_i[1].valid	No	No		No		INPUT
app_i[2].last	No	No		No		INPUT
app_i[2].strb[7:0]	No	No		No		INPUT
app_i[2].data[63:0]	No	No		No		INPUT
app_i[2].valid	No	No		No		INPUT
app_o[0].error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	No	No		No		OUTPUT
app_o[0].done	No	No		No		OUTPUT
app_o[0].ready	No	No		No		OUTPUT
app_o[1].error	No	No		No		OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	No	No		No		OUTPUT
app_o[1].done	No	No		No		OUTPUT
app_o[1].ready	No	No		No		OUTPUT
app_o[2].error	No	No		No		OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	No	No		No		OUTPUT
app_o[2].done	No	No		No		OUTPUT
app_o[2].ready	No	No		No		OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_kmac_done_o	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	OUTPUT
intr_kmac_err_o	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	773	Not Covered
KmacIdle	741	Not Covered
KmacKeyBlock	748	Not Covered
KmacMsgFeed	738	Not Covered
KmacPrefix	735	Not Covered
KmacTerminalError	790	Not Covered

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	782	Not Covered
KmacDigest->KmacTerminalError	804	Not Covered
KmacIdle->KmacMsgFeed	738	Not Covered
KmacIdle->KmacPrefix	735	Not Covered
KmacIdle->KmacTerminalError	804	Not Covered
KmacKeyBlock->KmacMsgFeed	757	Not Covered
KmacKeyBlock->KmacTerminalError	804	Not Covered
KmacMsgFeed->KmacDigest	773	Not Covered
KmacMsgFeed->KmacIdle	770	Not Covered
KmacMsgFeed->KmacTerminalError	804	Not Covered
KmacPrefix->KmacKeyBlock	748	Not Covered
KmacPrefix->KmacMsgFeed	748	Not Covered
KmacPrefix->KmacTerminalError	804	Not Covered

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		55	0	0.00
TERNARY	426	2	0	0.00
CASE	434	6	0	0.00
IF	488	3	0	0.00
IF	563	3	0	0.00
IF	612	2	0	0.00
CASE	645	6	0	0.00
IF	721	2	0	0.00
CASE	730	15	0	0.00
IF	803	2	0	0.00
TERNARY	1104	2	0	0.00
IF	1363	4	0	0.00
IF	1386	3	0	0.00
IF	1415	3	0	0.00
IF	1425	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Not Covered
CmdProcess	Not Covered
CmdManualRun	Not Covered
CmdDone	Not Covered
CmdNone	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	563	if ((!rst_ni))
-2-:	565	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	612	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	645	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Not Covered
errchecker_err.valid	Not Covered
sha3_err.valid	Not Covered
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	721	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	730	case (kmac_st)
-2-:	732	if ((kmac_cmd == CmdStart))
-3-:	734	if ((CShake == app_sha3_mode))
-4-:	747	if (sha3_block_processed)
-5-:	748	(app_kmac_en) ? 
-6-:	756	if (sha3_block_processed)
-7-:	765	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	771	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	781	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Not Covered
KmacIdle	1	0	-	-	-	-	-	-	Not Covered
KmacIdle	0	-	-	-	-	-	-	-	Not Covered
KmacPrefix	-	-	1	1	-	-	-	-	Not Covered
KmacPrefix	-	-	1	0	-	-	-	-	Not Covered
KmacPrefix	-	-	0	-	-	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	1	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	0	-	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	1	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	1	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	0	-	Not Covered
KmacDigest	-	-	-	-	-	-	-	1	Not Covered
KmacDigest	-	-	-	-	-	-	-	0	Not Covered
KmacTerminalError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	803	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1104	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1363	if ((!rst_ni))
-2-:	1365	if (alert_recov_operation)
-3-:	1367	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	1386	if ((!rst_ni))
-2-:	1388	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1415	if ((!rst_ni))
-2-:	1417	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1425	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		163	0	0.00
ALWAYS	346	0	0
ALWAYS	346	2	0	0.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	0	0.00
CONT_ASSIGN	422	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
ALWAYS	429	9	0	0.00
CONT_ASSIGN	464	1	0	0.00
CONT_ASSIGN	465	1	0	0.00
CONT_ASSIGN	466	1	0	0.00
CONT_ASSIGN	469	1	0	0.00
CONT_ASSIGN	473	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	478	1	0	0.00
CONT_ASSIGN	481	1	0	0.00
ALWAYS	488	6	0	0.00
CONT_ASSIGN	513	1	0	0.00
CONT_ASSIGN	518	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	528	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	530	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	537	1	0	0.00
CONT_ASSIGN	539	0	0
CONT_ASSIGN	541	1	0	0.00
CONT_ASSIGN	545	1	0	0.00
CONT_ASSIGN	547	1	0	0.00
CONT_ASSIGN	548	1	0	0.00
CONT_ASSIGN	551	1	0	0.00
CONT_ASSIGN	552	1	0	0.00
CONT_ASSIGN	555	1	0	0.00
ALWAYS	563	5	0	0.00
CONT_ASSIGN	573	1	0	0.00
CONT_ASSIGN	580	1	0	0.00
CONT_ASSIGN	581	1	0	0.00
CONT_ASSIGN	582	1	0	0.00
CONT_ASSIGN	592	1	0	0.00
ALWAYS	612	3	0	0.00
CONT_ASSIGN	616	1	0	0.00
CONT_ASSIGN	635	1	0	0.00
CONT_ASSIGN	640	1	0	0.00
ALWAYS	643	7	0	0.00
CONT_ASSIGN	679	1	0	0.00
CONT_ASSIGN	684	1	0	0.00
CONT_ASSIGN	691	1	0	0.00
CONT_ASSIGN	701	1	0	0.00
ALWAYS	721	3	0	0.00
ALWAYS	725	28	0	0.00
CONT_ASSIGN	875	1	0	0.00
CONT_ASSIGN	878	1	0	0.00
CONT_ASSIGN	942	1	0	0.00
CONT_ASSIGN	944	1	0	0.00
CONT_ASSIGN	974	1	0	0.00
CONT_ASSIGN	979	1	0	0.00
CONT_ASSIGN	980	1	0	0.00
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	985	0	0
ALWAYS	1103	0	0
ALWAYS	1103	2	0	0.00
CONT_ASSIGN	1255	1	0	0.00
CONT_ASSIGN	1256	1	0	0.00
CONT_ASSIGN	1257	1	0	0.00
CONT_ASSIGN	1266	1	0	0.00
CONT_ASSIGN	1272	1	0	0.00
CONT_ASSIGN	1273	1	0	0.00
CONT_ASSIGN	1274	1	0	0.00
CONT_ASSIGN	1275	1	0	0.00
CONT_ASSIGN	1278	1	0	0.00
CONT_ASSIGN	1287	1	0	0.00
CONT_ASSIGN	1331	1	0	0.00
CONT_ASSIGN	1345	1	0	0.00
CONT_ASSIGN	1352	1	0	0.00
CONT_ASSIGN	1357	1	0	0.00
ALWAYS	1363	6	0	0.00
CONT_ASSIGN	1372	1	0	0.00
CONT_ASSIGN	1374	1	0	0.00
ALWAYS	1386	4	0	0.00
CONT_ASSIGN	1392	1	0	0.00
ALWAYS	1415	4	0	0.00
ALWAYS	1425	3	0	0.00
CONT_ASSIGN	1436	1	0	0.00
CONT_ASSIGN	1440	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	0	1
347	0	1
352	0	1
421	0	1
422	0	1
426	0	1
429	0	1
430	0	1
431	0	1
432	0	1
434	0	1
436	0	1
440	0	1
444	0	1
448	0	1
464	0	1
465	0	1
466	0	1
469	0	1
473	0	1
474	0	1
478	0	1
481	0	1
488	0	1
489	0	1
490	0	1
491	0	1
492	0	1
493	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
513	0	1
518	0	1
525	0	1
528	0	1
529	0	1
530	0	1
533	0	5
534	0	5
537	0	1
539		unreachable
541	0	1
545	0	1
547	0	1
548	0	1
551	0	1
552	0	1
555	0	1
563	0	1
564	0	1
565	0	1
566	0	1
568	0	1
573	0	1
580	0	1
581	0	1
582	0	1
592	0	1
612	0	2
613	0	1
616	0	1
635	0	1
640	0	1
643	0	1
645	0	1
650	0	1
654	0	1
658	0	1
662	0	1
666	0	1
679	0	1
684	0	1
691	0	1
701	0	1
721	0	3
725	0	1
727	0	1
728	0	1
730	0	1
732	0	1
734	0	1
735	0	1
738	0	1
741	0	1
747	0	1
748	0	1
750	0	1
755	0	1
756	0	1
757	0	1
759	0	1
765	0	1
770	0	1
771	0	1
773	0	1
775	0	1
781	0	1
782	0	1
784	0	1
790	0	1
791	0	1
803	0	1
804	0	1
			==> MISSING_ELSE
875	0	1
878	0	1
942	0	1
944	0	1
974	0	1
979	0	1
980	0	1
982	0	1
985		unreachable
1103	0	1
1104	0	1
1255	0	1
1256	0	1
1257	0	1
1266	0	1
1272	0	1
1273	0	1
1274	0	1
1275	0	1
1278	0	1
1287	0	1
1331	0	1
1345	0	1
1352	0	1
1357	0	1
1363	0	1
1364	0	1
1365	0	1
1366	0	1
1367	0	1
1368	0	1
			==> MISSING_ELSE
1372	0	1
1374	0	1
1386	0	1
1387	0	1
1388	0	1
1389	0	1
			==> MISSING_ELSE
1392	0	1
1415	0	1
1416	0	1
1417	0	1
1419	0	1
			==> MISSING_ELSE
1425	0	1
1426	0	1
1429	0	1
1436	0	1
1440	0	1
1442	0	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	74	0	0.00
Logical	74	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       541
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       545
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       552
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       565
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       565
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       565
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Not Covered
1	-	Not Covered

 LINE       573
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       616
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       635
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       679
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Unreachable
1	0	0	0	Not Covered

 LINE       691
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       732
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       734
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       748
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       974
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1104
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1374
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Not Covered
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	38	59.38
Total Bits	4160	362	8.70
Total Bits 0->1	2080	181	8.70
Total Bits 1->0	2080	181	8.70

Ports	64	38	59.38
Port Bits	4160	362	8.70
Port Bits 0->1	2080	181	8.70
Port Bits 1->0	2080	181	8.70

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T6	Yes	T1,T2,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T5,T7	Yes	T2,T5,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
keymgr_key_i.key[1:0][255:0]	No	No		No		INPUT
keymgr_key_i.valid	No	No		No		INPUT
app_i[0].last	No	No		No		INPUT
app_i[0].strb[7:0]	No	No		No		INPUT
app_i[0].data[63:0]	No	No		No		INPUT
app_i[0].valid	No	No		No		INPUT
app_i[1].last	No	No		No		INPUT
app_i[1].strb[7:0]	No	No		No		INPUT
app_i[1].data[63:0]	No	No		No		INPUT
app_i[1].valid	No	No		No		INPUT
app_i[2].last	No	No		No		INPUT
app_i[2].strb[7:0]	No	No		No		INPUT
app_i[2].data[63:0]	No	No		No		INPUT
app_i[2].valid	No	No		No		INPUT
app_o[0].error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	No	No		No		OUTPUT
app_o[0].done	No	No		No		OUTPUT
app_o[0].ready	No	No		No		OUTPUT
app_o[1].error	No	No		No		OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	No	No		No		OUTPUT
app_o[1].done	No	No		No		OUTPUT
app_o[1].ready	No	No		No		OUTPUT
app_o[2].error	No	No		No		OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	No	No		No		OUTPUT
app_o[2].done	No	No		No		OUTPUT
app_o[2].ready	No	No		No		OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_kmac_done_o	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	OUTPUT
intr_kmac_err_o	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	773	Not Covered
KmacIdle	741	Not Covered
KmacKeyBlock	748	Not Covered
KmacMsgFeed	738	Not Covered
KmacPrefix	735	Not Covered
KmacTerminalError	790	Not Covered

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	782	Not Covered
KmacDigest->KmacTerminalError	804	Not Covered
KmacIdle->KmacMsgFeed	738	Not Covered
KmacIdle->KmacPrefix	735	Not Covered
KmacIdle->KmacTerminalError	804	Not Covered
KmacKeyBlock->KmacMsgFeed	757	Not Covered
KmacKeyBlock->KmacTerminalError	804	Not Covered
KmacMsgFeed->KmacDigest	773	Not Covered
KmacMsgFeed->KmacIdle	770	Not Covered
KmacMsgFeed->KmacTerminalError	804	Not Covered
KmacPrefix->KmacKeyBlock	748	Not Covered
KmacPrefix->KmacMsgFeed	748	Not Covered
KmacPrefix->KmacTerminalError	804	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		55	0	0.00
TERNARY	426	2	0	0.00
CASE	434	6	0	0.00
IF	488	3	0	0.00
IF	563	3	0	0.00
IF	612	2	0	0.00
CASE	645	6	0	0.00
IF	721	2	0	0.00
CASE	730	15	0	0.00
IF	803	2	0	0.00
TERNARY	1104	2	0	0.00
IF	1363	4	0	0.00
IF	1386	3	0	0.00
IF	1415	3	0	0.00
IF	1425	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Not Covered
CmdProcess	Not Covered
CmdManualRun	Not Covered
CmdDone	Not Covered
CmdNone	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	563	if ((!rst_ni))
-2-:	565	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	612	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	645	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Not Covered
errchecker_err.valid	Not Covered
sha3_err.valid	Not Covered
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	721	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	730	case (kmac_st)
-2-:	732	if ((kmac_cmd == CmdStart))
-3-:	734	if ((CShake == app_sha3_mode))
-4-:	747	if (sha3_block_processed)
-5-:	748	(app_kmac_en) ? 
-6-:	756	if (sha3_block_processed)
-7-:	765	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	771	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	781	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Not Covered
KmacIdle	1	0	-	-	-	-	-	-	Not Covered
KmacIdle	0	-	-	-	-	-	-	-	Not Covered
KmacPrefix	-	-	1	1	-	-	-	-	Not Covered
KmacPrefix	-	-	1	0	-	-	-	-	Not Covered
KmacPrefix	-	-	0	-	-	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	1	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	0	-	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	1	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	1	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	0	-	Not Covered
KmacDigest	-	-	-	-	-	-	-	1	Not Covered
KmacDigest	-	-	-	-	-	-	-	0	Not Covered
KmacTerminalError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	803	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1104	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1363	if ((!rst_ni))
-2-:	1365	if (alert_recov_operation)
-3-:	1367	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	1386	if ((!rst_ni))
-2-:	1388	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1415	if ((!rst_ni))
-2-:	1417	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1425	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered