Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.74	0.00	0.00	8.70	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1248526	3367	0	0
entropy_period_rd_A	1248526	1381	0	0
intr_enable_rd_A	1248526	2284	0	0
prefix_0_rd_A	1248526	1332	0	0
prefix_10_rd_A	1248526	1365	0	0
prefix_1_rd_A	1248526	1278	0	0
prefix_2_rd_A	1248526	1374	0	0
prefix_3_rd_A	1248526	1291	0	0
prefix_4_rd_A	1248526	1424	0	0
prefix_5_rd_A	1248526	1392	0	0
prefix_6_rd_A	1248526	1388	0	0
prefix_7_rd_A	1248526	1280	0	0
prefix_8_rd_A	1248526	1319	0	0
prefix_9_rd_A	1248526	1457	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	3367	0	0
T7	6786	162	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T13	9646	2	0	0
T14	2477	8	0	0
T16	0	2	0	0
T17	0	17	0	0
T18	0	165	0	0
T19	0	13	0	0
T24	7542	0	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	0	0	0
T28	10719	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1381	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T20	0	1	0	0
T24	7542	25	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	42	0	0
T28	10719	29	0	0
T30	0	119	0	0
T31	13254	78	0	0
T38	0	29	0	0
T69	0	14	0	0
T75	0	12	0	0
T76	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	2284	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T16	0	8	0	0
T24	7542	31	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	34	0	0
T28	10719	49	0	0
T31	13254	79	0	0
T36	0	1	0	0
T38	0	38	0	0
T77	0	10	0	0
T78	0	11	0	0
T79	0	20	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1332	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T16	0	10	0	0
T20	0	11	0	0
T24	7542	23	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	35	0	0
T28	10719	35	0	0
T30	0	76	0	0
T31	13254	44	0	0
T38	0	40	0	0
T69	0	10	0	0
T75	0	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1365	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T18	0	1	0	0
T20	0	6	0	0
T24	7542	35	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	32	0	0
T28	10719	17	0	0
T30	0	102	0	0
T31	13254	33	0	0
T36	0	5	0	0
T38	0	13	0	0
T75	0	17	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1278	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T16	0	9	0	0
T20	0	4	0	0
T24	7542	28	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	24	0	0
T28	10719	10	0	0
T30	0	84	0	0
T31	13254	38	0	0
T38	0	18	0	0
T69	0	11	0	0
T75	0	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1374	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T16	0	5	0	0
T20	0	10	0	0
T24	7542	28	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	44	0	0
T28	10719	49	0	0
T30	0	85	0	0
T31	13254	48	0	0
T38	0	6	0	0
T69	0	11	0	0
T75	0	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1291	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T16	0	10	0	0
T20	0	8	0	0
T24	7542	27	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	39	0	0
T28	10719	12	0	0
T30	0	67	0	0
T31	13254	41	0	0
T36	0	7	0	0
T38	0	24	0	0
T75	0	6	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1424	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T20	0	5	0	0
T24	7542	27	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	30	0	0
T28	10719	20	0	0
T30	0	92	0	0
T31	13254	40	0	0
T36	0	6	0	0
T38	0	52	0	0
T69	0	19	0	0
T75	0	6	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1392	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T16	0	2	0	0
T20	0	13	0	0
T24	7542	24	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	41	0	0
T28	10719	19	0	0
T30	0	91	0	0
T31	13254	43	0	0
T36	0	7	0	0
T69	0	14	0	0
T75	0	2	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1388	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T16	0	11	0	0
T20	0	8	0	0
T24	7542	27	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	26	0	0
T28	10719	33	0	0
T30	0	78	0	0
T31	13254	40	0	0
T36	0	8	0	0
T38	0	48	0	0
T75	0	10	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1280	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T20	0	15	0	0
T24	7542	32	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	15	0	0
T28	10719	27	0	0
T30	0	84	0	0
T31	13254	43	0	0
T34	0	3	0	0
T38	0	25	0	0
T69	0	15	0	0
T75	0	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1319	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T16	0	7	0	0
T20	0	7	0	0
T24	7542	13	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	33	0	0
T28	10719	24	0	0
T30	0	72	0	0
T31	13254	44	0	0
T36	0	1	0	0
T38	0	11	0	0
T75	0	19	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1457	0	0
T9	1204	0	0	0
T11	2030	0	0	0
T14	2477	0	0	0
T15	2022	0	0	0
T20	0	14	0	0
T24	7542	22	0	0
T25	13302	0	0	0
T26	14764	0	0	0
T27	7720	40	0	0
T28	10719	29	0	0
T30	0	68	0	0
T31	13254	45	0	0
T38	0	19	0	0
T69	0	8	0	0
T75	0	10	0	0
T76	0	4	0	0