KMAC/UNMASKED Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.173m	58.038ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	34.206us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	31.937us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.860s	1.212ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.540s	4.050ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.130s	28.209us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	31.937us	20	20	100.00
		kmac_csr_aliasing	10.540s	4.050ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	42.961us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.380s	125.894us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.331m	876.936ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.360m	26.449ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.457m	406.428ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.278m	385.601ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.062m	467.811ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.752m	203.229ms	50	50	100.00
		kmac_test_vectors_shake_128	1.653h	2.839s	50	50	100.00
		kmac_test_vectors_shake_256	1.529h	3.650s	50	50	100.00
		kmac_test_vectors_kmac	5.370s	1.032ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.580s	1.064ms	50	50	100.00
V2	sideload	kmac_sideload	7.162m	85.951ms	50	50	100.00
V2	app	kmac_app	5.497m	72.770ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.604m	16.224ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.843m	25.783ms	50	50	100.00
V2	error	kmac_error	6.504m	85.340ms	50	50	100.00
V2	key_error	kmac_key_error	10.690s	17.164ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.330s	6.440ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.720s	5.233ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.020m	12.641ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	24.230s	2.132ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.950m	101.051ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.900s	19.972us	50	50	100.00
V2	alert_test	kmac_alert_test	0.980s	113.518us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.530s	299.763us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.530s	299.763us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	34.206us	5	5	100.00
		kmac_csr_rw	1.180s	31.937us	20	20	100.00
		kmac_csr_aliasing	10.540s	4.050ms	5	5	100.00
		kmac_same_csr_outstanding	2.850s	1.093ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	34.206us	5	5	100.00
		kmac_csr_rw	1.180s	31.937us	20	20	100.00
		kmac_csr_aliasing	10.540s	4.050ms	5	5	100.00
		kmac_same_csr_outstanding	2.850s	1.093ms	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	36.605us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	36.605us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	36.605us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	36.605us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.020s	522.162us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.052m	20.012ms	5	5	100.00
		kmac_tl_intg_err	6.050s	558.450us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.050s	558.450us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	24.230s	2.132ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.173m	58.038ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.162m	85.951ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	36.605us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.052m	20.012ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.052m	20.012ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.052m	20.012ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.173m	58.038ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	24.230s	2.132ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.052m	20.012ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.037m	200.000ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.173m	58.038ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	44.463m	98.869ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1269	1290	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.11	96.58	92.46	100.00	86.36	94.67	98.84	96.88

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 16 failures:

  • Test kmac_stress_all_with_rand_reset has 16 failures.

    • 1.kmac_stress_all_with_rand_reset.93894260423877487189463618109940090448609167885308168692434136185329976004795
      Line 1285, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 117341126843 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 117341126843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.kmac_stress_all_with_rand_reset.71525302440487150529355990002062628362210146365873172599850548009514697309935
      Line 1142, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 123231161212 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 123231161212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

  • Test kmac_app_with_partial_data has 1 failures.

    • 1.kmac_app_with_partial_data.3837521211177074538804349914595317984317435878341577780388828562743679559689
      Line 360, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log

        UVM_FATAL @ 19082762383 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (83 [0x53] vs 154 [0x9a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 19082762383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 11.kmac_stress_all_with_rand_reset.9381847625321821262137071686329767319361930232152627813124668070768503187643
      Line 273, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1639369278 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (36 [0x24] vs 143 [0x8f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 1639369278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_stress_all has 1 failures.

    • 13.kmac_stress_all.26146881803907021314384123613933876483181457200282092973245885747399859858359
      Line 559, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest/run.log

        UVM_FATAL @ 6320027878 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (226 [0xe2] vs 194 [0xc2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 6320027878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test kmac_mubi has 1 failures.

    • 5.kmac_mubi.44662157308884444672970087394344480398940614874086553012168955717254748758868
      Line 416, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_mubi/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_burst_write has 1 failures.

    • 20.kmac_burst_write.35177970510530739492830418557796119077082361556745608256902627191515920238043
      Line 359, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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