Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54395	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113742

1

T1

892

T2

887

T3

929

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	94967	1			T1	708		T2	693		T3	718
values[0x0]	34637	1			T1	287		T2	271		T3	259
values[0x1]	38533	1			T1	275		T2	293		T3	250

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

128921

1

T1

1006

T2

1001

T3

1014

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	628	1			T2	6		T3	9		T11	4
valid_sources[0x01]	888	1			T2	2		T5	2		T10	1
valid_sources[0x02]	583	1			T2	2		T11	5		T21	1
valid_sources[0x03]	901	1			T2	3		T5	1		T11	3
valid_sources[0x04]	716	1			T2	2		T3	2		T5	5
valid_sources[0x05]	620	1			T2	3		T11	6		T12	1
valid_sources[0x06]	786	1			T2	8		T5	4		T10	2
valid_sources[0x07]	637	1			T2	2		T10	4		T21	1
valid_sources[0x08]	687	1			T2	5		T3	11		T10	2
valid_sources[0x09]	580	1			T2	3		T5	1		T7	2
valid_sources[0x0a]	876	1			T2	2		T5	2		T10	3
valid_sources[0x0b]	521	1			T2	7		T3	1		T12	1
valid_sources[0x0c]	583	1			T2	5		T5	4		T10	3
valid_sources[0x0d]	602	1			T2	9		T5	8		T11	30
valid_sources[0x0e]	607	1			T2	11		T3	5		T5	3
valid_sources[0x0f]	564	1			T2	7		T5	7		T10	3
valid_sources[0x10]	685	1			T2	5		T5	5		T12	3
valid_sources[0x11]	726	1			T2	5		T3	25		T4	44
valid_sources[0x12]	618	1			T1	20		T2	5		T3	5
valid_sources[0x13]	650	1			T2	4		T5	2		T11	32
valid_sources[0x14]	636	1			T2	4		T10	1		T11	4
valid_sources[0x15]	670	1			T2	5		T5	4		T11	23
valid_sources[0x16]	594	1			T2	6		T10	1		T11	7
valid_sources[0x17]	773	1			T1	39		T2	6		T3	37
valid_sources[0x18]	584	1			T2	5		T3	4		T10	4
valid_sources[0x19]	791	1			T2	4		T5	1		T10	4
valid_sources[0x1a]	668	1			T1	34		T2	1		T3	13
valid_sources[0x1b]	759	1			T2	2		T5	3		T11	7
valid_sources[0x1c]	755	1			T2	3		T5	4		T11	47
valid_sources[0x1d]	615	1			T2	8		T3	8		T5	1
valid_sources[0x1e]	629	1			T2	4		T11	2		T21	2
valid_sources[0x1f]	796	1			T1	124		T2	6		T3	34
valid_sources[0x20]	544	1			T2	5		T5	3		T10	1
valid_sources[0x21]	657	1			T2	8		T5	4		T11	9
valid_sources[0x22]	587	1			T2	3		T5	1		T11	21
valid_sources[0x23]	757	1			T2	5		T3	8		T11	8
valid_sources[0x24]	577	1			T2	3		T5	2		T11	8
valid_sources[0x25]	605	1			T2	5		T3	2		T5	5
valid_sources[0x26]	679	1			T2	3		T11	20		T21	1
valid_sources[0x27]	769	1			T1	41		T2	3		T5	4
valid_sources[0x28]	642	1			T2	7		T3	10		T5	5
valid_sources[0x29]	575	1			T2	6		T3	32		T5	1
valid_sources[0x2a]	835	1			T2	7		T10	3		T7	2
valid_sources[0x2b]	652	1			T2	11		T5	4		T11	20
valid_sources[0x2c]	601	1			T2	11		T11	12		T21	2
valid_sources[0x2d]	752	1			T2	5		T5	3		T11	26
valid_sources[0x2e]	580	1			T2	3		T3	4		T5	8
valid_sources[0x2f]	778	1			T2	4		T11	8		T22	5
valid_sources[0x30]	634	1			T2	3		T5	5		T10	1
valid_sources[0x31]	548	1			T2	5		T5	5		T10	2
valid_sources[0x32]	769	1			T2	5		T3	26		T5	4
valid_sources[0x33]	512	1			T2	6		T5	1		T10	1
valid_sources[0x34]	675	1			T2	2		T10	1		T7	2
valid_sources[0x35]	719	1			T2	4		T5	4		T10	1
valid_sources[0x36]	706	1			T1	84		T2	6		T3	7
valid_sources[0x37]	839	1			T2	5		T5	1		T12	1
valid_sources[0x38]	663	1			T2	5		T5	2		T10	2
valid_sources[0x39]	596	1			T2	5		T3	17		T5	2
valid_sources[0x3a]	616	1			T2	5		T10	1		T11	3
valid_sources[0x3b]	749	1			T1	100		T2	4		T3	55
valid_sources[0x3c]	667	1			T2	6		T3	2		T5	3
valid_sources[0x3d]	620	1			T2	9		T5	1		T12	1
valid_sources[0x3e]	595	1			T2	3		T3	8		T5	5
valid_sources[0x3f]	688	1			T1	6		T2	1		T5	2
valid_sources[0x40]	555	1			T2	3		T3	19		T5	2
valid_sources[0x41]	676	1			T2	6		T5	3		T11	15
valid_sources[0x42]	555	1			T1	9		T2	1		T3	3
valid_sources[0x43]	784	1			T2	10		T3	8		T5	1
valid_sources[0x44]	804	1			T2	10		T10	2		T7	1
valid_sources[0x45]	752	1			T1	42		T2	2		T5	2
valid_sources[0x46]	649	1			T2	10		T3	5		T12	1
valid_sources[0x47]	623	1			T2	5		T3	16		T5	3
valid_sources[0x48]	581	1			T2	4		T10	4		T11	18
valid_sources[0x49]	550	1			T2	7		T5	1		T11	1
valid_sources[0x4a]	455	1			T2	3		T5	1		T10	1
valid_sources[0x4b]	670	1			T2	3		T5	2		T10	1
valid_sources[0x4c]	717	1			T1	116		T2	5		T7	1
valid_sources[0x4d]	628	1			T2	11		T5	1		T10	7
valid_sources[0x4e]	586	1			T2	4		T3	22		T5	6
valid_sources[0x4f]	580	1			T2	6		T5	2		T11	12
valid_sources[0x50]	617	1			T2	4		T5	2		T6	3
valid_sources[0x51]	526	1			T2	2		T5	4		T10	2
valid_sources[0x52]	627	1			T2	3		T5	3		T11	17
valid_sources[0x53]	646	1			T2	4		T5	1		T10	2
valid_sources[0x54]	799	1			T2	5		T5	11		T10	1
valid_sources[0x55]	621	1			T1	5		T2	6		T3	2
valid_sources[0x56]	647	1			T2	1		T3	3		T10	1
valid_sources[0x57]	531	1			T2	4		T11	3		T22	1
valid_sources[0x58]	526	1			T2	9		T5	8		T10	1
valid_sources[0x59]	599	1			T2	9		T3	1		T5	1
valid_sources[0x5a]	783	1			T2	2		T3	1		T11	10
valid_sources[0x5b]	649	1			T2	9		T3	9		T5	1
valid_sources[0x5c]	843	1			T2	6		T5	4		T11	60
valid_sources[0x5d]	599	1			T2	6		T5	4		T11	24
valid_sources[0x5e]	713	1			T2	8		T5	2		T10	5
valid_sources[0x5f]	699	1			T2	3		T3	15		T10	2
valid_sources[0x60]	676	1			T2	4		T3	17		T5	5
valid_sources[0x61]	662	1			T2	4		T5	2		T10	1
valid_sources[0x62]	675	1			T2	10		T5	3		T10	2
valid_sources[0x63]	614	1			T2	10		T5	2		T11	6
valid_sources[0x64]	650	1			T2	3		T5	5		T10	2
valid_sources[0x65]	903	1			T2	7		T3	23		T5	2
valid_sources[0x66]	651	1			T2	2		T10	1		T11	20
valid_sources[0x67]	567	1			T2	2		T3	55		T7	2
valid_sources[0x68]	566	1			T2	7		T3	1		T5	1
valid_sources[0x69]	683	1			T2	5		T5	1		T11	15
valid_sources[0x6a]	647	1			T2	2		T5	4		T11	26
valid_sources[0x6b]	468	1			T2	1		T11	1		T12	3
valid_sources[0x6c]	585	1			T2	2		T5	4		T10	3
valid_sources[0x6d]	572	1			T2	1		T3	5		T5	1
valid_sources[0x6e]	708	1			T2	4		T5	4		T11	6
valid_sources[0x6f]	616	1			T2	5		T3	1		T5	1
valid_sources[0x70]	795	1			T2	3		T5	3		T10	8
valid_sources[0x71]	555	1			T2	2		T5	1		T10	2
valid_sources[0x72]	877	1			T2	4		T3	3		T5	7
valid_sources[0x73]	674	1			T1	12		T2	6		T5	2
valid_sources[0x74]	506	1			T2	2		T10	4		T11	27
valid_sources[0x75]	581	1			T2	3		T5	6		T6	1
valid_sources[0x76]	692	1			T1	118		T2	5		T3	12
valid_sources[0x77]	576	1			T2	3		T3	8		T5	1
valid_sources[0x78]	701	1			T2	9		T5	2		T11	6
valid_sources[0x79]	699	1			T2	7		T3	4		T5	3
valid_sources[0x7a]	620	1			T2	5		T5	6		T10	2
valid_sources[0x7b]	896	1			T2	9		T5	5		T11	12
valid_sources[0x7c]	642	1			T2	3		T3	13		T5	4
valid_sources[0x7d]	553	1			T1	32		T2	3		T5	3
valid_sources[0x7e]	690	1			T1	32		T2	2		T3	16
valid_sources[0x7f]	579	1			T1	2		T2	5		T11	5
valid_sources[0x80]	594	1			T2	4		T5	6		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53860

1

T1

372

T2

362

T3

443

values[0x0]

all_enables

biggest_size

30278

1

T1

269

T2

255

T3

249

values[0x1]

all_enables

biggest_size

29604

1

T1

251

T2

270

T3

237