Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

67371

1

T1

382

T2

371

T3

298

full_word

114568

1

T1

892

T2

887

T3

929

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	181629	1			T1	1264		T2	1248		T3	1227
auto[TlIntgErrCmd]	107	1			T1	4		T2	2		T25	7
auto[TlIntgErrData]	106	1			T1	3		T2	1		T25	7
auto[TlIntgErrBoth]	97	1			T1	3		T2	7		T25	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97412

1

T1

709

T2

693

T3

718

auto[1]

84527

1

T1

565

T2

565

T3

509

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	43240	1			T1	332		T2	326		T3	275
auto[TlIntgErrNone]	partial	auto[1]	23846	1			T1	40		T2	35		T3	23
auto[TlIntgErrNone]	full_word	auto[0]	54028	1			T1	372		T2	362		T3	443
auto[TlIntgErrNone]	full_word	auto[1]	60515	1			T1	520		T2	525		T3	486
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T1	2		T2	1		T25	4
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T1	2		T2	1		T25	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T24	1		T78	1		T79	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T24	1		T80	1		T81	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T1	2		T2	1		T25	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T1	1		T25	5		T24	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T77	1		T82	1		T81	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T23	2		T83	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T1	1		T2	3		T25	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T1	2		T2	4		T25	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T23	1		T81	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T25	1		T26	1		T69	1