Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1317000	21158	0	0
DepthKnown_A	1317000	1265606	0	0
RvalidKnown_A	1317000	1265606	0	0
WreadyKnown_A	1317000	1265606	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	21158	0	0
T4	2614	157	0	0
T5	2423	733	0	0
T6	1178	0	0	0
T7	1265	0	0	0
T9	1187	0	0	0
T10	2070	0	0	0
T11	26046	0	0	0
T12	6161	221	0	0
T13	0	272	0	0
T14	0	314	0	0
T15	0	530	0	0
T16	0	974	0	0
T17	0	273	0	0
T18	0	489	0	0
T19	0	132	0	0
T21	2342	0	0	0
T22	10471	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1317000	24116	0	0
DepthKnown_A	1317000	1265606	0	0
RvalidKnown_A	1317000	1265606	0	0
WreadyKnown_A	1317000	1265606	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	24116	0	0
T4	2614	150	0	0
T5	2423	372	0	0
T6	1178	0	0	0
T7	1265	0	0	0
T9	1187	0	0	0
T10	2070	0	0	0
T11	26046	0	0	0
T12	6161	766	0	0
T13	0	254	0	0
T14	0	305	0	0
T15	0	1895	0	0
T16	0	522	0	0
T17	0	214	0	0
T18	0	1044	0	0
T19	0	130	0	0
T21	2342	0	0	0
T22	10471	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1317000	254136	0	0
DepthKnown_A	1317000	1265606	0	0
RvalidKnown_A	1317000	1265606	0	0
WreadyKnown_A	1317000	1265606	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	254136	0	0
T1	8170	2469	0	0
T2	5344	2457	0	0
T3	9419	1464	0	0
T4	2614	74	0	0
T5	2423	371	0	0
T6	1178	40	0	0
T7	1265	40	0	0
T9	1187	20	0	0
T10	2070	260	0	0
T11	26046	6850	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1317000	307826	0	0
DepthKnown_A	1317000	1265606	0	0
RvalidKnown_A	1317000	1265606	0	0
WreadyKnown_A	1317000	1265606	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	307826	0	0
T1	8170	1274	0	0
T2	5344	1258	0	0
T3	9419	1227	0	0
T4	2614	70	0	0
T5	2423	197	0	0
T6	1178	40	0	0
T7	1265	136	0	0
T9	1187	20	0	0
T10	2070	238	0	0
T11	26046	14779	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1265606	0	0
T1	8170	7300	0	0
T2	5344	4554	0	0
T3	9419	9131	0	0
T4	2614	2552	0	0
T5	2423	2329	0	0
T6	1178	1117	0	0
T7	1265	1206	0	0
T9	1187	1128	0	0
T10	2070	2009	0	0
T11	26046	25983	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0