Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	464648	0	0
entropy_period_rd_A	2147483647	1960	0	0
intr_enable_rd_A	2147483647	2437	0	0
prefix_0_rd_A	2147483647	1681	0	0
prefix_10_rd_A	2147483647	1692	0	0
prefix_1_rd_A	2147483647	1637	0	0
prefix_2_rd_A	2147483647	1594	0	0
prefix_3_rd_A	2147483647	1837	0	0
prefix_4_rd_A	2147483647	1701	0	0
prefix_5_rd_A	2147483647	1859	0	0
prefix_6_rd_A	2147483647	1606	0	0
prefix_7_rd_A	2147483647	1764	0	0
prefix_8_rd_A	2147483647	1615	0	0
prefix_9_rd_A	2147483647	1630	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	464648	0	0
T13	283137	26082	0	0
T14	23326	0	0	0
T15	118174	0	0	0
T16	326024	27891	0	0
T17	133165	0	0	0
T18	112966	0	0	0
T22	179058	0	0	0
T27	394051	0	0	0
T31	141037	0	0	0
T38	5792	0	0	0
T49	0	40076	0	0
T84	0	56573	0	0
T85	0	23511	0	0
T86	0	49953	0	0
T109	0	75852	0	0
T110	0	101111	0	0
T111	0	20309	0	0
T112	0	14268	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1960	0	0
T84	593402	206	0	0
T85	0	40	0	0
T86	0	135	0	0
T90	0	59	0	0
T105	0	71	0	0
T122	0	281	0	0
T123	0	5	0	0
T124	0	19	0	0
T125	0	36	0	0
T126	0	1	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2437	0	0
T84	593402	88	0	0
T85	0	77	0	0
T86	0	145	0	0
T107	0	15	0	0
T122	0	268	0	0
T123	0	11	0	0
T124	0	25	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T136	0	13	0	0
T137	0	10	0	0
T138	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1681	0	0
T84	593402	203	0	0
T85	0	41	0	0
T86	0	140	0	0
T90	0	29	0	0
T105	0	43	0	0
T122	0	296	0	0
T123	0	8	0	0
T124	0	24	0	0
T125	0	8	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1692	0	0
T84	593402	144	0	0
T85	0	61	0	0
T86	0	151	0	0
T90	0	54	0	0
T105	0	63	0	0
T122	0	177	0	0
T123	0	6	0	0
T124	0	10	0	0
T125	0	5	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1637	0	0
T84	593402	166	0	0
T85	0	73	0	0
T86	0	171	0	0
T90	0	39	0	0
T105	0	30	0	0
T122	0	201	0	0
T123	0	7	0	0
T124	0	42	0	0
T125	0	28	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1594	0	0
T84	593402	121	0	0
T85	0	68	0	0
T86	0	144	0	0
T90	0	34	0	0
T105	0	51	0	0
T122	0	222	0	0
T123	0	5	0	0
T124	0	23	0	0
T125	0	32	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1837	0	0
T84	593402	180	0	0
T85	0	44	0	0
T86	0	157	0	0
T90	0	44	0	0
T105	0	49	0	0
T122	0	233	0	0
T123	0	7	0	0
T124	0	28	0	0
T125	0	27	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1701	0	0
T84	593402	142	0	0
T85	0	67	0	0
T86	0	169	0	0
T90	0	24	0	0
T105	0	44	0	0
T122	0	205	0	0
T123	0	7	0	0
T124	0	25	0	0
T125	0	23	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1859	0	0
T84	593402	137	0	0
T85	0	80	0	0
T86	0	164	0	0
T90	0	53	0	0
T105	0	25	0	0
T122	0	181	0	0
T123	0	8	0	0
T124	0	34	0	0
T125	0	33	0	0
T126	0	8	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1606	0	0
T84	593402	129	0	0
T85	0	73	0	0
T86	0	173	0	0
T90	0	45	0	0
T105	0	46	0	0
T122	0	184	0	0
T123	0	1	0	0
T124	0	11	0	0
T125	0	11	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1764	0	0
T84	593402	170	0	0
T85	0	72	0	0
T86	0	117	0	0
T90	0	49	0	0
T105	0	51	0	0
T122	0	255	0	0
T124	0	25	0	0
T125	0	44	0	0
T126	0	2	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	4	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1615	0	0
T84	593402	90	0	0
T85	0	66	0	0
T86	0	179	0	0
T90	0	36	0	0
T105	0	30	0	0
T122	0	233	0	0
T123	0	4	0	0
T124	0	19	0	0
T125	0	21	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0
T138	0	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1630	0	0
T84	593402	100	0	0
T85	0	63	0	0
T86	0	161	0	0
T90	0	51	0	0
T105	0	30	0	0
T122	0	217	0	0
T123	0	3	0	0
T124	0	28	0	0
T125	0	33	0	0
T126	0	6	0	0
T127	243557	0	0	0
T128	674983	0	0	0
T129	70894	0	0	0
T130	521138	0	0	0
T131	144370	0	0	0
T132	31379	0	0	0
T133	1800	0	0	0
T134	24810	0	0	0
T135	49339	0	0	0