Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.19	96.27	93.33	63.67	100.00	93.85	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.24	96.27	93.33	100.00	100.00	93.85	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.24	96.27	93.33	100.00	100.00	93.85	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.12	96.18	92.44	100.00	88.64	94.60	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	93.01	94.07	89.80		88.24	92.94	100.00
u_errchk	95.99	97.14	96.67		90.00	96.15	100.00
u_kmac_core	95.80	98.75	92.86	100.00	100.00	92.31	90.91
u_msgfifo	97.75	100.00	95.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.98	99.21	96.90	100.00		98.78	100.00
u_sha3	92.16	91.91	88.51	100.00	80.56	92.00	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.93	89.80	81.39			88.54	100.00
u_tlul_adapter_msgfifo	79.91	87.01	74.59			77.38	80.65

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
ALWAYS	649	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
ALWAYS	686	7	5	71.43
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	727	1	0	0.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	764	3	3	100.00
ALWAYS	768	28	28	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1034	0	0
ALWAYS	1152	0	0
ALWAYS	1152	2	2	100.00
CONT_ASSIGN	1305	1	0	0.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1407	1	1	100.00
ALWAYS	1413	6	5	83.33
CONT_ASSIGN	1422	1	1	100.00
CONT_ASSIGN	1424	1	1	100.00
ALWAYS	1436	4	4	100.00
CONT_ASSIGN	1442	1	1	100.00
ALWAYS	1465	4	4	100.00
ALWAYS	1475	3	3	100.00
CONT_ASSIGN	1486	1	1	100.00
CONT_ASSIGN	1490	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534		unreachable
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
585	1	1
627	1	1
633	1	1
641	1	1
646	1	1
649	1	1
650	1	1
651	1	1
653	1	1
654	1	1
678	1	1
683	1	1
686	1	1
688	1	1
693	1	1
697	1	1
701	1	1
705	0	1
709	0	1
722	1	1
727	0	1
734	1	1
744	1	1
764	3	3
768	1	1
770	1	1
771	1	1
773	1	1
775	1	1
777	1	1
778	1	1
781	1	1
784	1	1
790	1	1
791	1	1
793	1	1
798	1	1
799	1	1
800	1	1
802	1	1
808	1	1
813	1	1
814	1	1
816	1	1
818	1	1
824	1	1
825	1	1
827	1	1
833	1	1
834	1	1
846	1	1
847	1	1
			MISSING_ELSE
918	1	1
921	1	1
990	1	1
992	1	1
1023	1	1
1028	1	1
1029	1	1
1031	1	1
1034		unreachable
1152	1	1
1153	1	1
1305	0	1
1306	1	1
1307	1	1
1317	1	1
1318	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1330	1	1
1339	1	1
1381	1	1
1395	1	1
1402	1	1
1407	1	1
1413	1	1
1414	1	1
1415	1	1
1416	0	1
1417	1	1
1418	1	1
			MISSING_ELSE
1422	1	1
1424	1	1
1436	1	1
1437	1	1
1438	1	1
1439	1	1
			MISSING_ELSE
1442	1	1
1465	1	1
1466	1	1
1467	1	1
1469	1	1
			MISSING_ELSE
1475	1	1
1476	1	1
1479	1	1
1486	1	1
1490	1	1
1492	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T28,T29,T44

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T28,T29

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T13,T14
1	1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T31,T25

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T16,T22

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T40,T26,T41
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T22,T31,T32
0	0	1	0	Not Covered
0	1	0	0	Covered	T22,T31,T32
1	0	0	0	Covered	T13,T25,T26

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T6,T10,T11
0	1	0	0	Unreachable
1	0	0	0	Covered	T6,T10,T11

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T6,T10,T11
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T6,T10,T11
0	0	1	0	0	0	Covered	T6,T10,T11
0	1	0	0	0	0	Covered	T6,T10,T11
1	0	0	0	0	0	Covered	T6,T10,T11

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T13,T14

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T13,T16,T22
1	Covered	T2,T13,T14

 LINE       1023
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1153
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T46,T47,T48

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T46,T47,T48

 LINE       1424
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T6,T10,T11
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T6,T10,T11
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T16,T25	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T13,T16,T25	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T13,T16,T25	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T13,T16,T49	Yes	T13,T16,T49	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T2,T13,T15	Yes	T2,T13,T15	INPUT
keymgr_key_i.valid	Yes	Yes	T2,T13,T15	Yes	T2,T13,T15	INPUT
app_i[0].last	Yes	Yes	T16,T27,T31	Yes	T13,T16,T27	INPUT
app_i[0].strb[7:0]	Yes	Yes	T13,T16,T28	Yes	T13,T16,T28	INPUT
app_i[0].data[63:0]	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_i[0].valid	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_i[1].last	Yes	Yes	T16,T27,T31	Yes	T13,T16,T22	INPUT
app_i[1].strb[7:0]	Yes	Yes	T13,T16,T28	Yes	T13,T16,T28	INPUT
app_i[1].data[63:0]	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	INPUT
app_i[1].valid	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	INPUT
app_i[2].last	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_i[2].strb[7:0]	Yes	Yes	T13,T16,T28	Yes	T13,T16,T28	INPUT
app_i[2].data[63:0]	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_i[2].valid	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_o[0].error	Yes	Yes	T13,T25,T4	Yes	T13,T25,T4	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T16,T27,T31	Yes	T16,T27,T31	OUTPUT
app_o[0].done	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
app_o[0].ready	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
app_o[1].error	Yes	Yes	T25,T26,T44	Yes	T25,T26,T44	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	OUTPUT
app_o[1].done	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	OUTPUT
app_o[1].ready	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	OUTPUT
app_o[2].error	Yes	Yes	T13,T25,T44	Yes	T13,T25,T44	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
app_o[2].done	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
app_o[2].ready	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T35	Yes	T4,T5,T35	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T40,T26,T41	Yes	T40,T26,T41	OUTPUT
intr_kmac_err_o	Yes	Yes	T22,T31,T25	Yes	T22,T31,T25	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Covered	T1,T2,T3
KmacIdle	784	Covered	T1,T2,T3
KmacKeyBlock	791	Covered	T2,T13,T14
KmacMsgFeed	781	Covered	T1,T2,T3
KmacPrefix	778	Covered	T2,T13,T14
KmacTerminalError	833	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	847	Covered	T50,T51
KmacIdle->KmacMsgFeed	781	Covered	T1,T2,T3
KmacIdle->KmacPrefix	778	Covered	T2,T13,T14
KmacIdle->KmacTerminalError	847	Covered	T6,T37,T10
KmacKeyBlock->KmacMsgFeed	800	Covered	T2,T13,T14
KmacKeyBlock->KmacTerminalError	847	Covered	T8,T52,T53
KmacMsgFeed->KmacDigest	816	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	813	Covered	T13,T16,T22
KmacMsgFeed->KmacTerminalError	847	Covered	T4,T5,T54
KmacPrefix->KmacKeyBlock	791	Covered	T2,T13,T14
KmacPrefix->KmacMsgFeed	791	Covered	T13,T16,T22
KmacPrefix->KmacTerminalError	847	Covered	T35,T7,T55

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	423	2	2	100.00
TERNARY	633	4	4	100.00
TERNARY	641	4	4	100.00
TERNARY	646	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	649	2	2	100.00
CASE	688	6	4	66.67
IF	764	2	2	100.00
CASE	773	15	15	100.00
IF	846	2	2	100.00
TERNARY	1153	2	2	100.00
IF	1413	4	3	75.00
IF	1436	3	3	100.00
IF	1465	3	3	100.00
IF	1475	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T22,T31,T25
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T13,T16,T22
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T40,T26,T41

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T2,T13,T15
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T22,T31,T32
errchecker_err.valid	Covered	T22,T31,T32
sha3_err.valid	Covered	T13,T25,T26
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T2,T13,T14
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T2,T13,T14
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T13,T16,T22
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T2,T13,T14
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T2,T13,T14
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T2,T13,T14
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T13,T16,T22
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1153	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1413	if ((!rst_ni))
-2-:	1415	if (alert_recov_operation)
-3-:	1417	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1436	if ((!rst_ni))
-2-:	1438	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1465	if ((!rst_ni))
-2-:	1467	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1475	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1278743	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	337469	0	0
EntrySizeRegSameToEntrySizePkg_A	1033	1033	0	0
ErrProcessedLatched_A	2147483647	507	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	90	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	90	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	90	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacFsmCheck_A	2147483647	90	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	90	0	0
FpvSecCmRoundCountCheck_A	2147483647	90	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	90	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	90	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	90	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1033	1033	0	0
NumEntriesRegSameToNumEntriesPkg_A	1033	1033	0	0
PrefixRegSameToPrefixPkg_A	1033	1033	0	0
SecretKeyDivideBy32_A	1033	1033	0	0
Sha3AbsorbedPulse_A	2147483647	347156	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1278743	0	0
T1	995579	1259	0	0
T2	743026	682	0	0
T3	648184	1273	0	0
T12	506487	780	0	0
T13	283137	912	0	0
T14	23326	30	0	0
T15	118174	1164	0	0
T16	326024	916	0	0
T17	133165	1000	0	0
T18	112966	1109	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337469	0	0
T1	995579	377	0	0
T2	743026	97	0	0
T3	648184	378	0	0
T12	506487	239	0	0
T13	283137	184	0	0
T14	23326	9	0	0
T15	118174	156	0	0
T16	326024	177	0	0
T17	133165	297	0	0
T18	112966	148	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	507	0	0
T19	46984	8	0	0
T20	57387	11	0	0
T21	0	12	0	0
T48	1077	0	0	0
T56	0	3	0	0
T57	0	7	0	0
T58	0	15	0	0
T59	0	4	0	0
T60	0	4	0	0
T61	0	10	0	0
T62	0	11	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T66	224814	0	0	0
T67	157570	0	0	0
T68	6718	0	0	0
T69	6509	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347156	0	0
T1	995579	390	0	0
T2	743026	98	0	0
T3	648184	390	0	0
T12	506487	246	0	0
T13	283137	184	0	0
T14	23326	9	0	0
T15	118174	159	0	0
T16	326024	180	0	0
T17	133165	310	0	0
T18	112966	148	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
ALWAYS	649	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
ALWAYS	686	7	5	71.43
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	727	1	0	0.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	764	3	3	100.00
ALWAYS	768	28	28	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1034	0	0
ALWAYS	1152	0	0
ALWAYS	1152	2	2	100.00
CONT_ASSIGN	1305	1	0	0.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1407	1	1	100.00
ALWAYS	1413	6	5	83.33
CONT_ASSIGN	1422	1	1	100.00
CONT_ASSIGN	1424	1	1	100.00
ALWAYS	1436	4	4	100.00
CONT_ASSIGN	1442	1	1	100.00
ALWAYS	1465	4	4	100.00
ALWAYS	1475	3	3	100.00
CONT_ASSIGN	1486	1	1	100.00
CONT_ASSIGN	1490	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534		unreachable
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
585	1	1
627	1	1
633	1	1
641	1	1
646	1	1
649	1	1
650	1	1
651	1	1
653	1	1
654	1	1
678	1	1
683	1	1
686	1	1
688	1	1
693	1	1
697	1	1
701	1	1
705	0	1
709	0	1
722	1	1
727	0	1
734	1	1
744	1	1
764	3	3
768	1	1
770	1	1
771	1	1
773	1	1
775	1	1
777	1	1
778	1	1
781	1	1
784	1	1
790	1	1
791	1	1
793	1	1
798	1	1
799	1	1
800	1	1
802	1	1
808	1	1
813	1	1
814	1	1
816	1	1
818	1	1
824	1	1
825	1	1
827	1	1
833	1	1
834	1	1
846	1	1
847	1	1
			MISSING_ELSE
918	1	1
921	1	1
990	1	1
992	1	1
1023	1	1
1028	1	1
1029	1	1
1031	1	1
1034		unreachable
1152	1	1
1153	1	1
1305	0	1
1306	1	1
1307	1	1
1317	1	1
1318	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1330	1	1
1339	1	1
1381	1	1
1395	1	1
1402	1	1
1407	1	1
1413	1	1
1414	1	1
1415	1	1
1416	0	1
1417	1	1
1418	1	1
			MISSING_ELSE
1422	1	1
1424	1	1
1436	1	1
1437	1	1
1438	1	1
1439	1	1
			MISSING_ELSE
1442	1	1
1465	1	1
1466	1	1
1467	1	1
1469	1	1
			MISSING_ELSE
1475	1	1
1476	1	1
1479	1	1
1486	1	1
1490	1	1
1492	6	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T28,T29,T44

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T28,T29

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T13,T14
1	1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T31,T25

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T16,T22

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T40,T26,T41
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T22,T31,T32
0	0	1	0	Not Covered
0	1	0	0	Covered	T22,T31,T32
1	0	0	0	Covered	T13,T25,T26

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T6,T10,T11
0	1	0	0	Unreachable
1	0	0	0	Covered	T6,T10,T11

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T6,T10,T11
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T6,T10,T11
0	0	1	0	0	0	Covered	T6,T10,T11
0	1	0	0	0	0	Covered	T6,T10,T11
1	0	0	0	0	0	Covered	T6,T10,T11

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T13,T14

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T13,T16,T22
1	Covered	T2,T13,T14

 LINE       1023
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1153
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T46,T47,T48

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T46,T47,T48

 LINE       1424
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T6,T10,T11
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T6,T10,T11
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T16,T25	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T13,T16,T25	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T13,T16,T25	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T13,T16,T49	Yes	T13,T16,T49	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T2,T13,T15	Yes	T2,T13,T15	INPUT
keymgr_key_i.valid	Yes	Yes	T2,T13,T15	Yes	T2,T13,T15	INPUT
app_i[0].last	Yes	Yes	T16,T27,T31	Yes	T13,T16,T27	INPUT
app_i[0].strb[7:0]	Yes	Yes	T13,T16,T28	Yes	T13,T16,T28	INPUT
app_i[0].data[63:0]	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_i[0].valid	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_i[1].last	Yes	Yes	T16,T27,T31	Yes	T13,T16,T22	INPUT
app_i[1].strb[7:0]	Yes	Yes	T13,T16,T28	Yes	T13,T16,T28	INPUT
app_i[1].data[63:0]	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	INPUT
app_i[1].valid	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	INPUT
app_i[2].last	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_i[2].strb[7:0]	Yes	Yes	T13,T16,T28	Yes	T13,T16,T28	INPUT
app_i[2].data[63:0]	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_i[2].valid	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	INPUT
app_o[0].error	Yes	Yes	T13,T25,T4	Yes	T13,T25,T4	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T16,T27,T31	Yes	T16,T27,T31	OUTPUT
app_o[0].done	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
app_o[0].ready	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
app_o[1].error	Yes	Yes	T25,T26,T44	Yes	T25,T26,T44	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	OUTPUT
app_o[1].done	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	OUTPUT
app_o[1].ready	Yes	Yes	T13,T16,T22	Yes	T13,T16,T22	OUTPUT
app_o[2].error	Yes	Yes	T13,T25,T44	Yes	T13,T25,T44	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
app_o[2].done	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
app_o[2].ready	Yes	Yes	T13,T16,T27	Yes	T13,T16,T27	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T35	Yes	T4,T5,T35	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T40,T26,T41	Yes	T40,T26,T41	OUTPUT
intr_kmac_err_o	Yes	Yes	T22,T31,T25	Yes	T22,T31,T25	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Covered	T1,T2,T3
KmacIdle	784	Covered	T1,T2,T3
KmacKeyBlock	791	Covered	T2,T13,T14
KmacMsgFeed	781	Covered	T1,T2,T3
KmacPrefix	778	Covered	T2,T13,T14
KmacTerminalError	833	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	847	Covered	T50,T51
KmacIdle->KmacMsgFeed	781	Covered	T1,T2,T3
KmacIdle->KmacPrefix	778	Covered	T2,T13,T14
KmacIdle->KmacTerminalError	847	Covered	T6,T37,T10
KmacKeyBlock->KmacMsgFeed	800	Covered	T2,T13,T14
KmacKeyBlock->KmacTerminalError	847	Covered	T8,T52,T53
KmacMsgFeed->KmacDigest	816	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	813	Covered	T13,T16,T22
KmacMsgFeed->KmacTerminalError	847	Covered	T4,T5,T54
KmacPrefix->KmacKeyBlock	791	Covered	T2,T13,T14
KmacPrefix->KmacMsgFeed	791	Covered	T13,T16,T22
KmacPrefix->KmacTerminalError	847	Covered	T35,T7,T55

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	423	2	2	100.00
TERNARY	633	4	4	100.00
TERNARY	641	4	4	100.00
TERNARY	646	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	649	2	2	100.00
CASE	688	6	4	66.67
IF	764	2	2	100.00
CASE	773	15	15	100.00
IF	846	2	2	100.00
TERNARY	1153	2	2	100.00
IF	1413	4	3	75.00
IF	1436	3	3	100.00
IF	1465	3	3	100.00
IF	1475	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T22,T31,T25
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T13,T16,T22
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T40,T26,T41

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T2,T13,T15
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T22,T31,T32
errchecker_err.valid	Covered	T22,T31,T32
sha3_err.valid	Covered	T13,T25,T26
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T2,T13,T14
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T2,T13,T14
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T13,T16,T22
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T2,T13,T14
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T2,T13,T14
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T2,T13,T14
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T13,T16,T22
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1153	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1413	if ((!rst_ni))
-2-:	1415	if (alert_recov_operation)
-3-:	1417	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1436	if ((!rst_ni))
-2-:	1438	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1465	if ((!rst_ni))
-2-:	1467	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1475	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1278743	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	337469	0	0
EntrySizeRegSameToEntrySizePkg_A	1033	1033	0	0
ErrProcessedLatched_A	2147483647	507	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	90	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	90	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	90	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacFsmCheck_A	2147483647	90	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	90	0	0
FpvSecCmRoundCountCheck_A	2147483647	90	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	90	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	90	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	90	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1033	1033	0	0
NumEntriesRegSameToNumEntriesPkg_A	1033	1033	0	0
PrefixRegSameToPrefixPkg_A	1033	1033	0	0
SecretKeyDivideBy32_A	1033	1033	0	0
Sha3AbsorbedPulse_A	2147483647	347156	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1278743	0	0
T1	995579	1259	0	0
T2	743026	682	0	0
T3	648184	1273	0	0
T12	506487	780	0	0
T13	283137	912	0	0
T14	23326	30	0	0
T15	118174	1164	0	0
T16	326024	916	0	0
T17	133165	1000	0	0
T18	112966	1109	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337469	0	0
T1	995579	377	0	0
T2	743026	97	0	0
T3	648184	378	0	0
T12	506487	239	0	0
T13	283137	184	0	0
T14	23326	9	0	0
T15	118174	156	0	0
T16	326024	177	0	0
T17	133165	297	0	0
T18	112966	148	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	507	0	0
T19	46984	8	0	0
T20	57387	11	0	0
T21	0	12	0	0
T48	1077	0	0	0
T56	0	3	0	0
T57	0	7	0	0
T58	0	15	0	0
T59	0	4	0	0
T60	0	4	0	0
T61	0	10	0	0
T62	0	11	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T66	224814	0	0	0
T67	157570	0	0	0
T68	6718	0	0	0
T69	6509	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T6	567327	20	0	0
T7	3315	0	0	0
T10	0	20	0	0
T11	0	20	0	0
T19	46984	0	0	0
T35	5404	0	0	0
T48	1077	0	0	0
T63	1390	0	0	0
T64	331747	0	0	0
T65	31808	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	13644	0	0	0
T73	259518	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347156	0	0
T1	995579	390	0	0
T2	743026	98	0	0
T3	648184	390	0	0
T12	506487	246	0	0
T13	283137	184	0	0
T14	23326	9	0	0
T15	118174	159	0	0
T16	326024	180	0	0
T17	133165	310	0	0
T18	112966	148	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	995579	995573	0	0
T2	743026	742972	0	0
T3	648184	648174	0	0
T12	506487	506477	0	0
T13	283137	283126	0	0
T14	23326	23251	0	0
T15	118174	118167	0	0
T16	326024	326016	0	0
T17	133165	133159	0	0
T18	112966	112956	0	0