Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58790	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

128472

1

T1

177

T2

11

T3

1737

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	104290	1			T1	141		T2	20		T3	1403
values[0x0]	39289	1			T1	54		T2	11		T3	580
values[0x1]	43683	1			T1	58		T2	9		T3	548

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144652

1

T1

210

T2

20

T3

1986

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	699	1			T1	2		T3	4		T6	2
valid_sources[0x01]	563	1			T1	2		T3	7		T6	4
valid_sources[0x02]	614	1			T3	5		T6	4		T7	1
valid_sources[0x03]	569	1			T3	6		T6	5		T4	3
valid_sources[0x04]	655	1			T3	10		T6	2		T4	6
valid_sources[0x05]	826	1			T1	3		T3	5		T7	2
valid_sources[0x06]	678	1			T1	3		T3	14		T6	3
valid_sources[0x07]	919	1			T1	2		T3	10		T6	7
valid_sources[0x08]	602	1			T1	2		T3	18		T6	2
valid_sources[0x09]	854	1			T3	14		T6	4		T22	4
valid_sources[0x0a]	524	1			T1	3		T3	12		T6	3
valid_sources[0x0b]	804	1			T1	1		T3	10		T6	8
valid_sources[0x0c]	738	1			T1	2		T3	13		T6	9
valid_sources[0x0d]	816	1			T3	15		T6	1		T7	2
valid_sources[0x0e]	660	1			T1	1		T3	12		T6	3
valid_sources[0x0f]	602	1			T1	1		T3	20		T6	2
valid_sources[0x10]	554	1			T2	1		T3	10		T6	3
valid_sources[0x11]	553	1			T3	10		T5	3		T21	1
valid_sources[0x12]	721	1			T3	14		T6	6		T7	3
valid_sources[0x13]	1056	1			T1	2		T3	7		T6	3
valid_sources[0x14]	791	1			T1	1		T3	10		T6	10
valid_sources[0x15]	603	1			T1	1		T3	5		T6	1
valid_sources[0x16]	700	1			T1	4		T3	9		T6	8
valid_sources[0x17]	896	1			T1	2		T3	11		T6	5
valid_sources[0x18]	569	1			T3	15		T6	5		T4	3
valid_sources[0x19]	607	1			T3	9		T6	1		T7	1
valid_sources[0x1a]	801	1			T3	5		T6	1		T7	1
valid_sources[0x1b]	524	1			T1	2		T3	10		T6	3
valid_sources[0x1c]	631	1			T1	1		T3	10		T6	13
valid_sources[0x1d]	743	1			T2	1		T3	8		T6	5
valid_sources[0x1e]	870	1			T3	11		T6	4		T7	1
valid_sources[0x1f]	675	1			T3	13		T6	6		T7	3
valid_sources[0x20]	761	1			T2	2		T3	12		T6	12
valid_sources[0x21]	655	1			T3	10		T6	4		T4	1
valid_sources[0x22]	689	1			T3	9		T6	4		T7	1
valid_sources[0x23]	593	1			T1	1		T3	12		T6	3
valid_sources[0x24]	670	1			T3	16		T6	8		T11	1
valid_sources[0x25]	946	1			T3	12		T6	4		T7	1
valid_sources[0x26]	663	1			T3	8		T10	3		T6	8
valid_sources[0x27]	606	1			T1	2		T3	8		T6	5
valid_sources[0x28]	682	1			T1	3		T3	3		T6	5
valid_sources[0x29]	1033	1			T1	1		T3	10		T7	3
valid_sources[0x2a]	749	1			T3	18		T6	6		T7	1
valid_sources[0x2b]	765	1			T3	10		T6	2		T7	1
valid_sources[0x2c]	755	1			T1	1		T3	12		T6	3
valid_sources[0x2d]	718	1			T1	1		T2	2		T3	11
valid_sources[0x2e]	518	1			T1	1		T3	10		T6	8
valid_sources[0x2f]	535	1			T3	19		T6	2		T5	14
valid_sources[0x30]	685	1			T1	2		T3	7		T6	4
valid_sources[0x31]	715	1			T3	12		T6	11		T4	10
valid_sources[0x32]	841	1			T1	1		T3	13		T6	3
valid_sources[0x33]	620	1			T2	1		T3	10		T6	2
valid_sources[0x34]	587	1			T3	9		T6	6		T4	1
valid_sources[0x35]	556	1			T2	2		T3	10		T6	10
valid_sources[0x36]	698	1			T1	1		T3	9		T6	6
valid_sources[0x37]	471	1			T1	1		T3	12		T6	1
valid_sources[0x38]	639	1			T3	7		T4	1		T5	3
valid_sources[0x39]	689	1			T3	3		T6	2		T7	1
valid_sources[0x3a]	914	1			T1	1		T3	6		T6	4
valid_sources[0x3b]	914	1			T1	1		T3	11		T6	8
valid_sources[0x3c]	768	1			T3	10		T6	2		T4	6
valid_sources[0x3d]	800	1			T3	12		T6	1		T4	7
valid_sources[0x3e]	657	1			T3	7		T6	2		T7	2
valid_sources[0x3f]	860	1			T1	3		T3	7		T6	5
valid_sources[0x40]	933	1			T1	1		T2	1		T3	4
valid_sources[0x41]	756	1			T3	13		T6	6		T7	1
valid_sources[0x42]	626	1			T1	2		T3	9		T6	4
valid_sources[0x43]	623	1			T3	8		T6	6		T7	1
valid_sources[0x44]	598	1			T1	1		T3	18		T6	5
valid_sources[0x45]	769	1			T1	2		T3	9		T6	10
valid_sources[0x46]	879	1			T3	17		T6	7		T12	2
valid_sources[0x47]	515	1			T3	7		T6	6		T7	2
valid_sources[0x48]	490	1			T1	2		T3	9		T6	4
valid_sources[0x49]	686	1			T2	1		T3	13		T6	8
valid_sources[0x4a]	624	1			T1	1		T3	13		T6	6
valid_sources[0x4b]	645	1			T2	1		T3	15		T6	4
valid_sources[0x4c]	943	1			T3	5		T6	3		T7	1
valid_sources[0x4d]	703	1			T3	12		T6	10		T7	3
valid_sources[0x4e]	863	1			T3	5		T6	3		T7	2
valid_sources[0x4f]	792	1			T3	18		T6	2		T7	2
valid_sources[0x50]	580	1			T3	9		T6	7		T4	2
valid_sources[0x51]	1052	1			T3	10		T6	7		T7	1
valid_sources[0x52]	706	1			T3	11		T6	3		T7	2
valid_sources[0x53]	714	1			T3	5		T6	2		T5	4
valid_sources[0x54]	537	1			T1	1		T3	9		T6	5
valid_sources[0x55]	736	1			T3	9		T6	2		T5	7
valid_sources[0x56]	1083	1			T3	5		T6	6		T4	1
valid_sources[0x57]	536	1			T2	2		T3	19		T6	7
valid_sources[0x58]	568	1			T1	4		T2	1		T3	6
valid_sources[0x59]	557	1			T3	10		T6	10		T7	2
valid_sources[0x5a]	1013	1			T3	13		T6	11		T7	3
valid_sources[0x5b]	935	1			T1	2		T3	16		T6	1
valid_sources[0x5c]	710	1			T1	3		T3	11		T6	6
valid_sources[0x5d]	669	1			T1	4		T3	6		T6	7
valid_sources[0x5e]	706	1			T3	13		T6	4		T4	2
valid_sources[0x5f]	662	1			T3	8		T6	4		T7	3
valid_sources[0x60]	1058	1			T1	2		T2	1		T3	3
valid_sources[0x61]	615	1			T3	11		T6	11		T7	1
valid_sources[0x62]	1023	1			T3	20		T6	8		T7	1
valid_sources[0x63]	721	1			T1	3		T3	11		T6	9
valid_sources[0x64]	495	1			T1	1		T3	13		T6	8
valid_sources[0x65]	698	1			T1	1		T3	10		T6	9
valid_sources[0x66]	735	1			T3	10		T6	1		T4	1
valid_sources[0x67]	992	1			T3	11		T6	7		T4	2
valid_sources[0x68]	786	1			T1	1		T3	11		T6	3
valid_sources[0x69]	787	1			T1	1		T3	5		T6	9
valid_sources[0x6a]	740	1			T3	9		T6	2		T7	1
valid_sources[0x6b]	672	1			T1	2		T3	11		T6	19
valid_sources[0x6c]	529	1			T1	2		T3	9		T6	6
valid_sources[0x6d]	585	1			T1	5		T2	1		T3	3
valid_sources[0x6e]	593	1			T1	1		T3	9		T7	1
valid_sources[0x6f]	706	1			T3	10		T6	14		T7	2
valid_sources[0x70]	1014	1			T3	8		T6	6		T4	3
valid_sources[0x71]	787	1			T1	3		T3	11		T6	13
valid_sources[0x72]	740	1			T3	14		T6	5		T7	1
valid_sources[0x73]	953	1			T3	5		T6	6		T7	1
valid_sources[0x74]	651	1			T1	3		T3	3		T6	2
valid_sources[0x75]	860	1			T3	18		T6	3		T7	2
valid_sources[0x76]	534	1			T1	1		T3	10		T6	5
valid_sources[0x77]	646	1			T3	14		T6	1		T7	1
valid_sources[0x78]	993	1			T2	4		T3	11		T6	5
valid_sources[0x79]	497	1			T3	1		T6	2		T7	1
valid_sources[0x7a]	709	1			T2	1		T3	9		T6	3
valid_sources[0x7b]	679	1			T1	2		T3	12		T6	5
valid_sources[0x7c]	781	1			T1	2		T3	11		T6	8
valid_sources[0x7d]	998	1			T3	6		T6	4		T7	2
valid_sources[0x7e]	686	1			T3	20		T6	2		T7	1
valid_sources[0x7f]	751	1			T3	9		T6	3		T7	1
valid_sources[0x80]	899	1			T3	8		T6	5		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59146

1

T1

72

T2

7

T3

699

values[0x0]

all_enables

biggest_size

34930

1

T1

52

T2

2

T3

536

values[0x1]

all_enables

biggest_size

34396

1

T1

53

T2

2

T3

502