Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

75218

1

T1

76

T2

29

T3

797

full_word

129585

1

T1

177

T2

11

T3

1737

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	204513	1			T1	253		T2	40		T3	2514
auto[TlIntgErrCmd]	105	1			T3	7		T23	9		T25	2
auto[TlIntgErrData]	86	1			T3	7		T23	5		T25	3
auto[TlIntgErrBoth]	99	1			T3	6		T23	6		T25	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108430

1

T1

141

T2

20

T3

1403

auto[1]

96373

1

T1

112

T2

20

T3

1131

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	48852	1			T1	69		T2	13		T3	696
auto[TlIntgErrNone]	partial	auto[1]	26102	1			T1	7		T2	16		T3	82
auto[TlIntgErrNone]	full_word	auto[0]	59443	1			T1	72		T2	7		T3	698
auto[TlIntgErrNone]	full_word	auto[1]	70116	1			T1	105		T2	4		T3	1038
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T3	2		T23	5		T25	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T3	5		T23	3		T24	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T23	1		T88	1		T89	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T90	1		T39	1		T91	2
auto[TlIntgErrData]	partial	auto[0]	38	1			T3	3		T23	2		T24	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T3	4		T23	3		T25	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T92	1		T88	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T24	1		T91	1		T93	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T3	3		T23	2		T25	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T3	2		T23	3		T25	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T3	1		T24	1		T94	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T23	1		T24	1		T48	1