Unified Coverage Report :: Module :: prim_generic_flop

Module : prim_generic_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_state_regs.u_state_flop.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_kmac_core.u_state_regs.u_state_flop.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_sha3.u_state_regs.u_state_flop.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_sha3.u_pad.u_state_regs.u_state_flop.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_sha3.u_keccak.u_state_regs.u_state_flop.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_app_intf.u_state_regs.u_state_flop.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_errchk.u_state_regs.u_state_flop.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	0.00	0.00				0.00
tb.dut.u_reg.u_cfg_shadowed0_qe.gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_kmac_core.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_pad.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_app_intf.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_errchk.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed0_qe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_cfg_shadowed0_qe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_kmac_core.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_kmac_core.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_sha3.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_sha3.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_sha3.u_pad.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_app_intf.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_app_intf.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_errchk.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_errchk.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	18	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	0	1
19	0	1
21	0	1

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	18	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed0_qe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed0_qe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3