Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1418747	271562	0	0
DepthKnown_A	1418747	1367551	0	0
RvalidKnown_A	1418747	1367551	0	0
WreadyKnown_A	1418747	1367551	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	271562	0	0
T1	1592	483	0	0
T2	1090	40	0	0
T3	38480	6818	0	0
T4	7073	1498	0	0
T5	2886	668	0	0
T6	8864	1347	0	0
T7	12894	500	0	0
T8	1455	225	0	0
T10	1361	22	0	0
T11	1384	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1367551	0	0
T1	1592	1507	0	0
T2	1090	1024	0	0
T3	38480	36773	0	0
T4	7073	6690	0	0
T5	2886	2797	0	0
T6	8864	8794	0	0
T7	12894	12804	0	0
T8	1455	1338	0	0
T10	1361	1279	0	0
T11	1384	1317	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1367551	0	0
T1	1592	1507	0	0
T2	1090	1024	0	0
T3	38480	36773	0	0
T4	7073	6690	0	0
T5	2886	2797	0	0
T6	8864	8794	0	0
T7	12894	12804	0	0
T8	1455	1338	0	0
T10	1361	1279	0	0
T11	1384	1317	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1367551	0	0
T1	1592	1507	0	0
T2	1090	1024	0	0
T3	38480	36773	0	0
T4	7073	6690	0	0
T5	2886	2797	0	0
T6	8864	8794	0	0
T7	12894	12804	0	0
T8	1455	1338	0	0
T10	1361	1279	0	0
T11	1384	1317	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1418747	373530	0	0
DepthKnown_A	1418747	1367551	0	0
RvalidKnown_A	1418747	1367551	0	0
WreadyKnown_A	1418747	1367551	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	373530	0	0
T1	1592	253	0	0
T2	1090	40	0	0
T3	38480	12899	0	0
T4	7073	2964	0	0
T5	2886	367	0	0
T6	8864	1237	0	0
T7	12894	485	0	0
T8	1455	114	0	0
T10	1361	22	0	0
T11	1384	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1367551	0	0
T1	1592	1507	0	0
T2	1090	1024	0	0
T3	38480	36773	0	0
T4	7073	6690	0	0
T5	2886	2797	0	0
T6	8864	8794	0	0
T7	12894	12804	0	0
T8	1455	1338	0	0
T10	1361	1279	0	0
T11	1384	1317	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1367551	0	0
T1	1592	1507	0	0
T2	1090	1024	0	0
T3	38480	36773	0	0
T4	7073	6690	0	0
T5	2886	2797	0	0
T6	8864	8794	0	0
T7	12894	12804	0	0
T8	1455	1338	0	0
T10	1361	1279	0	0
T11	1384	1317	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1367551	0	0
T1	1592	1507	0	0
T2	1090	1024	0	0
T3	38480	36773	0	0
T4	7073	6690	0	0
T5	2886	2797	0	0
T6	8864	8794	0	0
T7	12894	12804	0	0
T8	1455	1338	0	0
T10	1361	1279	0	0
T11	1384	1317	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0