LC_CTRL Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.260s	547.395us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.210s	18.673us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	16.361us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.120s	607.398us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.380s	34.593us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.710s	107.716us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	16.361us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	34.593us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.950s	160.227us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	14.870s	276.482us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.930s	21.898us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.120s	155.355us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.700s	4.197ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_prog_failure	5.120s	155.355us	50	50	100.00
		lc_ctrl_errors	26.700s	4.197ms	50	50	100.00
		lc_ctrl_security_escalation	17.690s	981.600us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.502m	3.781ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.140s	1.007ms	20	20	100.00
		lc_ctrl_jtag_errors	2.268m	5.355ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.560s	853.811us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.310s	1.225ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.140s	1.007ms	20	20	100.00
		lc_ctrl_jtag_errors	2.268m	5.355ms	20	20	100.00
		lc_ctrl_jtag_access	27.500s	1.274ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.670s	1.484ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.730s	150.448us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.790s	100.476us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	54.530s	2.673ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.970s	1.400ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.060s	50.155us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.650s	132.151us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.790s	111.248us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.281m	3.750ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.940s	26.132us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.539m	22.400ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.360s	31.311us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.530s	625.753us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.530s	625.753us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.210s	18.673us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	16.361us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	34.593us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	39.130us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.210s	18.673us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	16.361us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	34.593us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	39.130us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.630s	714.588us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.630s	714.588us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	14.870s	276.482us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	56.640s	379.324us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	1.173ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.690s	981.600us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.950s	160.227us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.310s	1.225ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.290s	675.086us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.290s	675.086us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.410s	832.100us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.350s	2.049ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.350s	2.049ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.537h	361.284ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			984	1030	95.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.29	97.18	95.26	91.98	100.00	95.88	98.73	95.00

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 22 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 22 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.576449597
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a7fe7ff5-6c41-4241-b217-11cb6d8a1da2
```
  - 7.lc_ctrl_stress_all_with_rand_reset.3058524931
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9a1e05dc-9325-41a7-b3e1-3a8df408a039
```
  - ... and 20 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 9 failures:

Test lc_ctrl_stress_all_with_rand_reset has 9 failures.

2.lc_ctrl_stress_all_with_rand_reset.3638377133
Line 10629, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 16285200709 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xc6257bbc
  UVM_INFO @ 16285200709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.lc_ctrl_stress_all_with_rand_reset.1418871380
Line 757, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 1134049540 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xa873d600
  UVM_INFO @ 1134049540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 8 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.550084036
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9c8cc49b-01aa-4833-8c1d-15314c588060
```
  - 9.lc_ctrl_stress_all_with_rand_reset.961984038
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9ff504ff-79a4-4464-bf14-cbc71e8d5d52
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

20.lc_ctrl_stress_all_with_rand_reset.441127133
Line 5659, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3752014416 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0
  UVM_INFO @ 3752014416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.lc_ctrl_stress_all_with_rand_reset.2482948008
Line 28246, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 27171018501 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0
  UVM_INFO @ 27171018501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

29.lc_ctrl_stress_all_with_rand_reset.2069075349
Line 2526, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12995347801 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 3941711088 [0xeaf1bcf0]) Regname: lc_ctrl_reg_block.transition_token_2 reset value: 0x0
  UVM_INFO @ 12995347801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.lc_ctrl_stress_all_with_rand_reset.1778268727
Line 14385, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15185638467 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 2965230793 [0xb0bdd4c9]) Regname: lc_ctrl_reg_block.transition_token_3 reset value: 0x0
  UVM_INFO @ 15185638467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_target reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 18.lc_ctrl_stress_all_with_rand_reset.1478142455
    Line 18696, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6303491240 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 138547332 [0x8421084]) Regname: lc_ctrl_reg_block.transition_target reset value: 0x0
  UVM_INFO @ 6303491240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.lc_ctrl_stress_all_with_rand_reset.3589230724
    Line 6378, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20616109910 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 20616109910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 45.lc_ctrl_stress_all_with_rand_reset.3451754750
    Line 8207, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16133012394 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked6
  UVM_INFO @ 16133012394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```