Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.06	100.00	83.10	87.81		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	149536900	17320	0	0
claim_transition_if_regwen_rd_A	149536900	3580	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149536900	17320	0	0
T69	2305	37	0	0
T70	3751	0	0	0
T71	2305	37	0	0
T72	0	37	0	0
T73	12310	789	0	0
T74	11061	0	0	0
T75	20191	0	0	0
T76	102881	0	0	0
T92	7873	0	0	0
T93	3751	0	0	0
T95	12310	789	0	0
T96	0	789	0	0
T99	0	58	0	0
T107	0	789	0	0
T108	0	789	0	0
T109	0	789	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149536900	3580	0	0
T46	3751	10	0	0
T69	2305	3	0	0
T70	3751	10	0	0
T71	2305	3	0	0
T73	12310	6	0	0
T74	11061	0	0	0
T75	20191	0	0	0
T76	102881	0	0	0
T81	0	3	0	0
T92	7873	311	0	0
T93	3751	10	0	0
T95	0	6	0	0
T96	0	6	0	0