Unified Coverage Report :: Module :: lc_ctrl

Module : lc_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.83	100.00	81.94	87.81		100.00	84.38

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.06	100.00	83.10	87.81		100.00	84.38

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.06	100.00	83.10	87.81		100.00	84.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.81	96.94	91.76	84.26	90.70	94.70	98.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
lc_ctrl_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_dmi_jtag	95.65			95.65
u_lc_ctrl_fsm	91.42	97.72	76.92		91.89	93.41	97.14
u_lc_ctrl_kmac_if	95.42	98.21	100.00		83.33	95.56	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_esc_receiver0	16.07			16.07
u_prim_esc_receiver1	16.07			16.07
u_prim_flop_2sync_init	100.00	100.00				100.00
u_prim_lc_sync	100.00	100.00					100.00
u_prim_mubi4_dec	0.00	0.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg	98.22	97.79	93.32	100.00		100.00	100.00
u_reg_tap	87.09	95.78	98.26	50.24		91.18	100.00
u_tap_tlul_host	77.17	96.08	92.86	6.90		90.00	100.00

Line Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
ALWAYS	315	41	41	100.00
ALWAYS	366	41	41	100.00
ALWAYS	464	33	33	100.00
ALWAYS	523	3	3	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	565	1	1	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
ALWAYS	666	5	5	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	676	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
213	1	1
266	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
339	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
373	1	1
378	1	1
380	1	1
382	1	1
384	1	1
			MISSING_ELSE
389	1	1
391	1	1
392	1	1
395	1	1
396	1	1
			MISSING_ELSE
404	1	1
405	1	1
			MISSING_ELSE
409	1	1
410	1	1
411	1	1
			MISSING_ELSE
415	1	1
416	1	1
417	1	1
			MISSING_ELSE
422	1	1
423	1	1
			MISSING_ELSE
425	1	1
426	1	1
429	1	1
430	1	1
			MISSING_ELSE
438	1	1
439	1	1
			MISSING_ELSE
443	1	1
444	1	1
445	1	1
			MISSING_ELSE
449	1	1
450	1	1
451	1	1
			MISSING_ELSE
456	1	1
457	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
478	1	1
479	1	1
489	1	1
490	1	1
492	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
511	1	1
523	1	1
524	1	1
526	1	1
536	1	1
552	1	1
554	1	1
565	1	1
571	1	1
580	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
675	1	1
676	1	1

---

Cond Coverage for Module : lc_ctrl

	Total	Covered	Percent
Conditions	72	59	81.94
Logical	72	59	81.94
Non-Logical	0	0
Event	0	0

 LINE       213
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       240
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       240
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       392
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       426
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       489
 EXPRESSION (SecVolatileRawUnlockEn && transition_cmd && ((!volatile_raw_unlock_q)))
             -----------1----------    -------2------    -------------3------------

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T10,T12,T13
-	1	1	Covered	T1,T2,T3

 LINE       492
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9

 LINE       495
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T5,T15
1	0	Covered	T11,T5,T15

 LINE       496
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       497
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T21,T22
1	0	Covered	T11,T21,T22

 LINE       498
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T22,T5
1	0	Covered	T11,T22,T5

 LINE       499
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T19
1	0	Covered	T1,T11,T19

 LINE       500
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T42,T22
1	0	Covered	T4,T42,T22

 LINE       501
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T26
1	0	Covered	T11,T5,T15

 LINE       502
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T63,T64,T65
1	0	0	Covered	T63,T64,T65

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T66,T67,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T66,T67,T68

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T66,T67,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T66,T67,T68

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T66,T67,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T66,T67,T68

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Not Covered

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Not Covered

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Not Covered

 LINE       593
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T66,T67,T68

 LINE       593
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T66,T67,T68

 LINE       593
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T66,T67,T68

---

Toggle Coverage for Module : lc_ctrl

	Total	Covered	Percent
Totals	106	93	87.74
Total Bits	7434	6528	87.81
Total Bits 0->1	3717	3264	87.81
Total Bits 1->0	3717	3264	87.81

Ports	106	93	87.74
Port Bits	7434	6528	87.81
Port Bits 0->1	3717	3264	87.81
Port Bits 1->0	3717	3264	87.81

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
rst_ni	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
clk_kmac_i	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
rst_kmac_ni	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.d_ready	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_address[31:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_source[7:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_size[1:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_valid	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_o.a_ready	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_error	Yes	Yes	T69,T71,T72	Yes	T69,T73,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T46,T69,*T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T73,T71	Yes	T69,T73,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
jtag_i.tdi	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
jtag_i.trst_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
jtag_i.tms	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
jtag_i.tck	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
jtag_o.tdo_oe	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
jtag_o.tdo	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
scan_rst_ni	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T46,T70,T74	Yes	T46,T70,T74	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T46,T70,T74	Yes	T46,T70,T74	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
strap_en_override_o	No	No		No		OUTPUT
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.status[1:0]	No	No		No		INPUT
lc_otp_vendor_test_i.status[2]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[3]	No	No		No		INPUT
lc_otp_vendor_test_i.status[4]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[6:5]	No	No		No		INPUT
lc_otp_vendor_test_i.status[9:7]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[13:10]	No	No		No		INPUT
lc_otp_vendor_test_i.status[20:14]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[21]	No	No		No		INPUT
lc_otp_vendor_test_i.status[22]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[23]	No	No		No		INPUT
lc_otp_vendor_test_i.status[31:24]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
lc_otp_program_o.count[4:0]	Yes	Yes	T10,T12,T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[5]	No	No		No		OUTPUT
lc_otp_program_o.count[7:6]	Yes	Yes	T10,T12,T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[8]	No	No		No		OUTPUT
lc_otp_program_o.count[10:9]	Yes	Yes	T10,T12,T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[11]	No	No		No		OUTPUT
lc_otp_program_o.count[13:12]	Yes	Yes	T10,T12,T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[14]	No	No		No		OUTPUT
lc_otp_program_o.count[51:15]	Yes	Yes	*T10,*T12,*T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[52]	No	No		No		OUTPUT
lc_otp_program_o.count[55:53]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
lc_otp_program_o.count[56]	No	No		No		OUTPUT
lc_otp_program_o.count[59:57]	Yes	Yes	T10,T12,T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[61:60]	No	No		No		OUTPUT
lc_otp_program_o.count[159:62]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[160]	No	No		No		OUTPUT
lc_otp_program_o.count[162:161]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[163]	No	No		No		OUTPUT
lc_otp_program_o.count[167:164]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[168]	No	No		No		OUTPUT
lc_otp_program_o.count[169]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[170]	No	No		No		OUTPUT
lc_otp_program_o.count[174:171]	Yes	Yes	*T42,*T28,*T77	Yes	T42,T28,T77	OUTPUT
lc_otp_program_o.count[175]	No	No		No		OUTPUT
lc_otp_program_o.count[196:176]	Yes	Yes	*T10,*T12,*T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[197]	No	No		No		OUTPUT
lc_otp_program_o.count[200:198]	Yes	Yes	*T10,*T12,*T13	Yes	T5,T15,T26	OUTPUT
lc_otp_program_o.count[201]	No	No		No		OUTPUT
lc_otp_program_o.count[205:202]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.count[206]	No	No		No		OUTPUT
lc_otp_program_o.count[209:207]	Yes	Yes	*T10,*T12,*T13	Yes	T42,T28,T16	OUTPUT
lc_otp_program_o.count[211:210]	No	No		No		OUTPUT
lc_otp_program_o.count[213:212]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[214]	No	No		No		OUTPUT
lc_otp_program_o.count[215]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.count[218:216]	No	No		No		OUTPUT
lc_otp_program_o.count[220:219]	Yes	Yes	T46,T70,T75	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.count[222:221]	No	No		No		OUTPUT
lc_otp_program_o.count[274:223]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[275]	No	No		No		OUTPUT
lc_otp_program_o.count[278:276]	Yes	Yes	T10,T12,T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[280:279]	No	No		No		OUTPUT
lc_otp_program_o.count[281]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[282]	No	No		No		OUTPUT
lc_otp_program_o.count[283]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.count[285:284]	No	No		No		OUTPUT
lc_otp_program_o.count[305:286]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[306]	No	No		No		OUTPUT
lc_otp_program_o.count[307]	Yes	Yes	*T10,*T12,*T13	Yes	T5,T15,T26	OUTPUT
lc_otp_program_o.count[308]	No	No		No		OUTPUT
lc_otp_program_o.count[310:309]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.count[311]	No	No		No		OUTPUT
lc_otp_program_o.count[370:312]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.count[372:371]	No	No		No		OUTPUT
lc_otp_program_o.count[375:373]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.count[376]	No	No		No		OUTPUT
lc_otp_program_o.count[380:377]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[381]	No	No		No		OUTPUT
lc_otp_program_o.count[383:382]	Yes	Yes	T10,T12,T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.state[31:0]	Yes	Yes	*T5,*T15,*T26	Yes	T5,T15,T26	OUTPUT
lc_otp_program_o.state[32]	No	No		No		OUTPUT
lc_otp_program_o.state[41:33]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[42]	No	No		No		OUTPUT
lc_otp_program_o.state[46:43]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[47]	No	No		No		OUTPUT
lc_otp_program_o.state[85:48]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[86]	No	No		No		OUTPUT
lc_otp_program_o.state[88:87]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[89]	No	No		No		OUTPUT
lc_otp_program_o.state[240:90]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[241]	No	No		No		OUTPUT
lc_otp_program_o.state[243:242]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[244]	No	No		No		OUTPUT
lc_otp_program_o.state[251:245]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	OUTPUT
lc_otp_program_o.state[252]	No	No		No		OUTPUT
lc_otp_program_o.state[254:253]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[255]	No	No		No		OUTPUT
lc_otp_program_o.state[319:256]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_otp_program_i.err	Yes	Yes	T5,T15,T26	Yes	T5,T15,T26	INPUT
kmac_data_i.error	Yes	Yes	T11,T5,T15	Yes	T11,T5,T15	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
kmac_data_i.done	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
kmac_data_i.ready	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
kmac_data_o.last	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
kmac_data_o.valid	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T69,T71,T72	Yes	T46,T69,T70	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T22,T40,T45	Yes	T22,T40,T45	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T46,T70,T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T46,T70,T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T22,T40,T45	Yes	T22,T40,T45	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T22,T40,T45	Yes	T22,T40,T45	INPUT
otp_lc_data_i.count[4:0]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[5]	No	No		No		INPUT
otp_lc_data_i.count[7:6]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[8]	No	No		No		INPUT
otp_lc_data_i.count[10:9]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[11]	No	No		No		INPUT
otp_lc_data_i.count[13:12]	Yes	Yes	T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[14]	No	No		No		INPUT
otp_lc_data_i.count[51:15]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[52]	No	No		No		INPUT
otp_lc_data_i.count[55:53]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
otp_lc_data_i.count[56]	No	No		No		INPUT
otp_lc_data_i.count[59:57]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[61:60]	No	No		No		INPUT
otp_lc_data_i.count[159:62]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[160]	No	No		No		INPUT
otp_lc_data_i.count[162:161]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[163]	No	No		No		INPUT
otp_lc_data_i.count[165:164]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[166]	No	No		No		INPUT
otp_lc_data_i.count[167]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[168]	No	No		No		INPUT
otp_lc_data_i.count[169]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[171:170]	No	No		No		INPUT
otp_lc_data_i.count[174:172]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[175]	No	No		No		INPUT
otp_lc_data_i.count[195:176]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[197:196]	No	No		No		INPUT
otp_lc_data_i.count[198]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[199]	No	No		No		INPUT
otp_lc_data_i.count[200]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[201]	No	No		No		INPUT
otp_lc_data_i.count[205:202]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[206]	No	No		No		INPUT
otp_lc_data_i.count[209:207]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[211:210]	No	No		No		INPUT
otp_lc_data_i.count[213:212]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[214]	No	No		No		INPUT
otp_lc_data_i.count[215]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[218:216]	No	No		No		INPUT
otp_lc_data_i.count[220:219]	Yes	Yes	T46,T70,T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[222:221]	No	No		No		INPUT
otp_lc_data_i.count[274:223]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[275]	No	No		No		INPUT
otp_lc_data_i.count[278:276]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[280:279]	No	No		No		INPUT
otp_lc_data_i.count[281]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[282]	No	No		No		INPUT
otp_lc_data_i.count[283]	Yes	Yes	*T69,*T71,*T75	Yes	T69,T71,T75	INPUT
otp_lc_data_i.count[285:284]	No	No		No		INPUT
otp_lc_data_i.count[303:286]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[304]	No	No		No		INPUT
otp_lc_data_i.count[305]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[306]	No	No		No		INPUT
otp_lc_data_i.count[307]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[308]	No	No		No		INPUT
otp_lc_data_i.count[310:309]	Yes	Yes	*T75,*T81,*T78	Yes	T75,T81,T78	INPUT
otp_lc_data_i.count[311]	No	No		No		INPUT
otp_lc_data_i.count[314:312]	Yes	Yes	T75,T81,T78	Yes	T75,T81,T78	INPUT
otp_lc_data_i.count[315]	No	No		No		INPUT
otp_lc_data_i.count[370:316]	Yes	Yes	*T75,*T81,*T78	Yes	T75,T81,T78	INPUT
otp_lc_data_i.count[372:371]	No	No		No		INPUT
otp_lc_data_i.count[375:373]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[376]	No	No		No		INPUT
otp_lc_data_i.count[380:377]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[381]	No	No		No		INPUT
otp_lc_data_i.count[383:382]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.state[31:0]	Yes	Yes	*T5,*T15,*T26	Yes	T5,T15,T26	INPUT
otp_lc_data_i.state[32]	No	No		No		INPUT
otp_lc_data_i.state[41:33]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[42]	No	No		No		INPUT
otp_lc_data_i.state[46:43]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[47]	No	No		No		INPUT
otp_lc_data_i.state[84:48]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[86:85]	No	No		No		INPUT
otp_lc_data_i.state[88:87]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[89]	No	No		No		INPUT
otp_lc_data_i.state[240:90]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[241]	No	No		No		INPUT
otp_lc_data_i.state[243:242]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[245:244]	No	No		No		INPUT
otp_lc_data_i.state[251:246]	Yes	Yes	*T1,*T2,*T3	Yes	T69,T71,T72	INPUT
otp_lc_data_i.state[252]	No	No		No		INPUT
otp_lc_data_i.state[254:253]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[255]	No	No		No		INPUT
otp_lc_data_i.state[319:256]	Yes	Yes	T78,T79,T80	Yes	T69,T71,T72	INPUT
otp_lc_data_i.error	Yes	Yes	T11,T5,T15	Yes	T11,T5,T15	INPUT
otp_lc_data_i.valid	Yes	Yes	T4,T42,T24	Yes	T4,T42,T24	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T75	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T1,T9,T4	Yes	T78,T79,T80	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T2,T3,T11	Yes	T2,T3,T11	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
lc_flash_rma_ack_i[3:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
otp_device_id_i[1:0]	No	No		No		INPUT
otp_device_id_i[2]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[3]	No	No		No		INPUT
otp_device_id_i[5:4]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[9:6]	No	No		No		INPUT
otp_device_id_i[11:10]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[12]	No	No		No		INPUT
otp_device_id_i[13]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[18:14]	No	No		No		INPUT
otp_device_id_i[19]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[21:20]	No	No		No		INPUT
otp_device_id_i[23:22]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[25:24]	No	No		No		INPUT
otp_device_id_i[26]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[29:27]	No	No		No		INPUT
otp_device_id_i[30]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[31]	No	No		No		INPUT
otp_device_id_i[32]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[35:33]	No	No		No		INPUT
otp_device_id_i[36]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[38:37]	No	No		No		INPUT
otp_device_id_i[40:39]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[41]	No	No		No		INPUT
otp_device_id_i[42]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[43]	No	No		No		INPUT
otp_device_id_i[44]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[45]	No	No		No		INPUT
otp_device_id_i[46]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[49:47]	No	No		No		INPUT
otp_device_id_i[51:50]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[52]	No	No		No		INPUT
otp_device_id_i[55:53]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[58:56]	No	No		No		INPUT
otp_device_id_i[59]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[60]	No	No		No		INPUT
otp_device_id_i[61]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[65:62]	No	No		No		INPUT
otp_device_id_i[69:66]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[71:70]	No	No		No		INPUT
otp_device_id_i[72]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[75:73]	No	No		No		INPUT
otp_device_id_i[78:76]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[79]	No	No		No		INPUT
otp_device_id_i[81:80]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[82]	No	No		No		INPUT
otp_device_id_i[84:83]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[85]	No	No		No		INPUT
otp_device_id_i[86]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[87]	No	No		No		INPUT
otp_device_id_i[88]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[90:89]	No	No		No		INPUT
otp_device_id_i[91]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[92]	No	No		No		INPUT
otp_device_id_i[93]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[94]	No	No		No		INPUT
otp_device_id_i[95]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[96]	No	No		No		INPUT
otp_device_id_i[97]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[100:98]	No	No		No		INPUT
otp_device_id_i[102:101]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[103]	No	No		No		INPUT
otp_device_id_i[104]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[107:105]	No	No		No		INPUT
otp_device_id_i[110:108]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[112:111]	No	No		No		INPUT
otp_device_id_i[113]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[118:114]	No	No		No		INPUT
otp_device_id_i[121:119]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[122]	No	No		No		INPUT
otp_device_id_i[123]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[125:124]	No	No		No		INPUT
otp_device_id_i[131:126]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[133:132]	No	No		No		INPUT
otp_device_id_i[134]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[139:135]	No	No		No		INPUT
otp_device_id_i[140]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[141]	No	No		No		INPUT
otp_device_id_i[142]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[144:143]	No	No		No		INPUT
otp_device_id_i[146:145]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[149:147]	No	No		No		INPUT
otp_device_id_i[150]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[151]	No	No		No		INPUT
otp_device_id_i[152]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[153]	No	No		No		INPUT
otp_device_id_i[154]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[155]	No	No		No		INPUT
otp_device_id_i[157:156]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[158]	No	No		No		INPUT
otp_device_id_i[160:159]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[162:161]	No	No		No		INPUT
otp_device_id_i[164:163]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[165]	No	No		No		INPUT
otp_device_id_i[166]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[167]	No	No		No		INPUT
otp_device_id_i[170:168]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[171]	No	No		No		INPUT
otp_device_id_i[174:172]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[175]	No	No		No		INPUT
otp_device_id_i[177:176]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[179:178]	No	No		No		INPUT
otp_device_id_i[180]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[182:181]	No	No		No		INPUT
otp_device_id_i[185:183]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[192:186]	No	No		No		INPUT
otp_device_id_i[193]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[195:194]	No	No		No		INPUT
otp_device_id_i[197:196]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[198]	No	No		No		INPUT
otp_device_id_i[199]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[200]	No	No		No		INPUT
otp_device_id_i[207:201]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[208]	No	No		No		INPUT
otp_device_id_i[210:209]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[214:211]	No	No		No		INPUT
otp_device_id_i[215]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[216]	No	No		No		INPUT
otp_device_id_i[217]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[218]	No	No		No		INPUT
otp_device_id_i[220:219]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[223:221]	No	No		No		INPUT
otp_device_id_i[225:224]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[226]	No	No		No		INPUT
otp_device_id_i[227]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[228]	No	No		No		INPUT
otp_device_id_i[233:229]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[234]	No	No		No		INPUT
otp_device_id_i[235]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[236]	No	No		No		INPUT
otp_device_id_i[237]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[239:238]	No	No		No		INPUT
otp_device_id_i[240]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[243:241]	No	No		No		INPUT
otp_device_id_i[244]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[246:245]	No	No		No		INPUT
otp_device_id_i[247]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[249:248]	No	No		No		INPUT
otp_device_id_i[250]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[251]	No	No		No		INPUT
otp_device_id_i[254:252]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[255]	No	No		No		INPUT
otp_manuf_state_i[0]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[1]	No	No		No		INPUT
otp_manuf_state_i[5:2]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[6]	No	No		No		INPUT
otp_manuf_state_i[7]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[8]	No	No		No		INPUT
otp_manuf_state_i[9]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[12:10]	No	No		No		INPUT
otp_manuf_state_i[15:13]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[16]	No	No		No		INPUT
otp_manuf_state_i[17]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[20:18]	No	No		No		INPUT
otp_manuf_state_i[21]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[27:22]	No	No		No		INPUT
otp_manuf_state_i[28]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[30:29]	No	No		No		INPUT
otp_manuf_state_i[31]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[32]	No	No		No		INPUT
otp_manuf_state_i[34:33]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[35]	No	No		No		INPUT
otp_manuf_state_i[38:36]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[39]	No	No		No		INPUT
otp_manuf_state_i[41:40]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[43:42]	No	No		No		INPUT
otp_manuf_state_i[44]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[46:45]	No	No		No		INPUT
otp_manuf_state_i[48:47]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[49]	No	No		No		INPUT
otp_manuf_state_i[52:50]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[53]	No	No		No		INPUT
otp_manuf_state_i[55:54]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[57:56]	No	No		No		INPUT
otp_manuf_state_i[59:58]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[62:60]	No	No		No		INPUT
otp_manuf_state_i[63]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[68:64]	No	No		No		INPUT
otp_manuf_state_i[70:69]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[72:71]	No	No		No		INPUT
otp_manuf_state_i[73]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[75:74]	No	No		No		INPUT
otp_manuf_state_i[77:76]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[78]	No	No		No		INPUT
otp_manuf_state_i[80:79]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[82:81]	No	No		No		INPUT
otp_manuf_state_i[83]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[84]	No	No		No		INPUT
otp_manuf_state_i[87:85]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[93:88]	No	No		No		INPUT
otp_manuf_state_i[96:94]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[97]	No	No		No		INPUT
otp_manuf_state_i[99:98]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[100]	No	No		No		INPUT
otp_manuf_state_i[102:101]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[103]	No	No		No		INPUT
otp_manuf_state_i[104]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[105]	No	No		No		INPUT
otp_manuf_state_i[107:106]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[108]	No	No		No		INPUT
otp_manuf_state_i[109]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[110]	No	No		No		INPUT
otp_manuf_state_i[113:111]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[114]	No	No		No		INPUT
otp_manuf_state_i[116:115]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[119:117]	No	No		No		INPUT
otp_manuf_state_i[120]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[121]	No	No		No		INPUT
otp_manuf_state_i[123:122]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[124]	No	No		No		INPUT
otp_manuf_state_i[125]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[126]	No	No		No		INPUT
otp_manuf_state_i[127]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[128]	No	No		No		INPUT
otp_manuf_state_i[129]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[132:130]	No	No		No		INPUT
otp_manuf_state_i[134:133]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[135]	No	No		No		INPUT
otp_manuf_state_i[136]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[138:137]	No	No		No		INPUT
otp_manuf_state_i[139]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[141:140]	No	No		No		INPUT
otp_manuf_state_i[143:142]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[144]	No	No		No		INPUT
otp_manuf_state_i[145]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[147:146]	No	No		No		INPUT
otp_manuf_state_i[149:148]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[151:150]	No	No		No		INPUT
otp_manuf_state_i[153:152]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[159:154]	No	No		No		INPUT
otp_manuf_state_i[160]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[163:161]	No	No		No		INPUT
otp_manuf_state_i[165:164]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[166]	No	No		No		INPUT
otp_manuf_state_i[167]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[170:168]	No	No		No		INPUT
otp_manuf_state_i[171]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[172]	No	No		No		INPUT
otp_manuf_state_i[173]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[176:174]	No	No		No		INPUT
otp_manuf_state_i[178:177]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[179]	No	No		No		INPUT
otp_manuf_state_i[180]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[184:181]	No	No		No		INPUT
otp_manuf_state_i[186:185]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[188:187]	No	No		No		INPUT
otp_manuf_state_i[191:189]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[192]	No	No		No		INPUT
otp_manuf_state_i[193]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[195:194]	No	No		No		INPUT
otp_manuf_state_i[197:196]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[198]	No	No		No		INPUT
otp_manuf_state_i[199]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[204:200]	No	No		No		INPUT
otp_manuf_state_i[206:205]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[207]	No	No		No		INPUT
otp_manuf_state_i[208]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[209]	No	No		No		INPUT
otp_manuf_state_i[210]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[211]	No	No		No		INPUT
otp_manuf_state_i[214:212]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[218:215]	No	No		No		INPUT
otp_manuf_state_i[221:219]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[224:222]	No	No		No		INPUT
otp_manuf_state_i[227:225]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[228]	No	No		No		INPUT
otp_manuf_state_i[229]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[231:230]	No	No		No		INPUT
otp_manuf_state_i[233:232]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[234]	No	No		No		INPUT
otp_manuf_state_i[237:235]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[245:238]	No	No		No		INPUT
otp_manuf_state_i[246]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[247]	No	No		No		INPUT
otp_manuf_state_i[249:248]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[250]	No	No		No		INPUT
otp_manuf_state_i[251]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[253:252]	No	No		No		INPUT
otp_manuf_state_i[254]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[255]	No	No		No		INPUT
hw_rev_o.reserved[23:0]	No	No		No		OUTPUT
hw_rev_o.revision_id[7:0]	No	No		No		OUTPUT
hw_rev_o.product_id[15:0]	No	No		No		OUTPUT
hw_rev_o.silicon_creator_id[15:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
IF	344	3	3	100.00
IF	378	3	3	100.00
IF	389	18	18	100.00
IF	464	3	3	100.00
IF	666	2	2	100.00
IF	523	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	344	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-2-:	353	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T1,T3,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	378	if ((prim_mubi_pkg::mubi8_test_false_loose(sw_claim_transition_if_q) && tap_reg2hw.claim_transition_if.qe))
-2-:	382	if ((prim_mubi_pkg::mubi8_test_false_loose(tap_claim_transition_if_q) && reg2hw.claim_transition_if.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T1,T3,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if (lc_idle_d)
-2-:	391	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-3-:	395	if (tap_reg2hw.transition_ctrl.ext_clock_en.qe)
-4-:	404	if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-5-:	415	if (tap_reg2hw.transition_target.qe)
-6-:	422	if (tap_reg2hw.otp_vendor_test_ctrl.qe)
-7-:	425	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))
-8-:	429	if (reg2hw.transition_ctrl.ext_clock_en.qe)
-9-:	438	if (reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-10-:	449	if (reg2hw.transition_target.qe)
-11-:	456	if (reg2hw.otp_vendor_test_ctrl.qe)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T25
1	1	0	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	1	-	-	-	-	-	-	-	Covered	T2,T5,T25
1	1	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	-	1	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	-	0	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	-	-	1	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T5
1	0	-	-	-	-	1	1	-	-	-	Covered	T3,T10,T12
1	0	-	-	-	-	1	0	-	-	-	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	1	-	-	Covered	T3,T10,T12
1	0	-	-	-	-	1	-	0	-	-	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	-	1	-	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	-	0	-	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	-	-	1	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	-	-	0	Covered	T1,T3,T9
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	489	if (((SecVolatileRawUnlockEn && transition_cmd) && (!volatile_raw_unlock_q)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	666	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	523	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	27	84.38
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	27	84.38

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	145284390	141995440	0	0
DecLcCountWidthCheck_A	795	795	0	0
DecLcIdStateWidthCheck_A	795	795	0	0
DecLcStateWidthCheck_A	795	795	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	141861700	0	0	0
FpvSecCmCtrlLcCntCheck_A	138671950	0	0	0
FpvSecCmCtrlLcFsmCheck_A	142967940	0	0	0
FpvSecCmCtrlLcStateCheck_A	138473540	0	0	0
FpvSecCmRegWeOnehotCheck_A	145284390	100	0	0
FpvSecCmTapRegWeOnehotCheck_A	145284390	0	0	0
LcCheckBypassEnKnown_A	145284390	141995440	0	0
LcClkBypReqKnown_A	145284390	141995440	0	0
LcCpuEnKnown_A	145284390	141995440	0	0
LcCreatorSwRwEn_A	145284390	141995440	0	0
LcDftEnKnown_A	145284390	141995440	0	0
LcEscalateEnKnown_A	145284390	141995440	0	0
LcFlashRmaReqKnown_A	145284390	141995440	0	0
LcFlashRmaSeedKnown_A	145284390	141995440	0	0
LcHwDebugEnKnown_A	145284390	141995440	0	0
LcIsoSwRwEn_A	145284390	141995440	0	0
LcIsoSwWrEn_A	145284390	141995440	0	0
LcKeymgrDiv_A	145284390	141995440	0	0
LcKeymgrEnKnown_A	145284390	141995440	0	0
LcNvmDebugEnKnown_A	145284390	141995440	0	0
LcOtpProgramKnown_A	145284390	141995440	0	0
LcOtpTokenKnown_A	145284390	141995440	0	0
LcOwnerSwRwEn_A	145284390	141995440	0	0
LcSeedHwRdEn_A	145284390	141995440	0	0
NumTokenWordsCheck_A	795	795	0	0
OtpTestCtrlWidth_A	795	795	0	0
PwrLcKnown_A	145284390	141995440	0	0
TlOKnown	145284390	141995440	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141861700	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138671950	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142967940	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138473540	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	100	0	0
T63	21642	20	0	0
T64	21642	20	0	0
T65	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	2362	0	0	0
T85	2362	0	0	0
T86	16312	0	0	0
T87	27280	0	0	0
T88	16312	0	0	0
T89	8921	0	0	0
T90	56567	0	0	0
T91	75534	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
ALWAYS	315	41	41	100.00
ALWAYS	366	41	41	100.00
ALWAYS	464	33	33	100.00
ALWAYS	523	3	3	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	565	1	1	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
ALWAYS	666	5	5	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	676	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
213	1	1
266	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
339	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
373	1	1
378	1	1
380	1	1
382	1	1
384	1	1
			MISSING_ELSE
389	1	1
391	1	1
392	1	1
395	1	1
396	1	1
			MISSING_ELSE
404	1	1
405	1	1
			MISSING_ELSE
409	1	1
410	1	1
411	1	1
			MISSING_ELSE
415	1	1
416	1	1
417	1	1
			MISSING_ELSE
422	1	1
423	1	1
			MISSING_ELSE
425	1	1
426	1	1
429	1	1
430	1	1
			MISSING_ELSE
438	1	1
439	1	1
			MISSING_ELSE
443	1	1
444	1	1
445	1	1
			MISSING_ELSE
449	1	1
450	1	1
451	1	1
			MISSING_ELSE
456	1	1
457	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
478	1	1
479	1	1
489	1	1
490	1	1
492	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
511	1	1
523	1	1
524	1	1
526	1	1
536	1	1
552	1	1
554	1	1
565	1	1
571	1	1
580	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
675	1	1
676	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	71	59	83.10
Logical	71	59	83.10
Non-Logical	0	0
Event	0	0

 LINE       213
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       240
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       240
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       392
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       426
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       489
 EXPRESSION (SecVolatileRawUnlockEn && transition_cmd && ((!volatile_raw_unlock_q)))
             -----------1----------    -------2------    -------------3------------

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T10,T12,T13
-	1	1	Covered	T1,T2,T3

 LINE       492
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9

 LINE       495
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T5,T15
1	0	Covered	T11,T5,T15

 LINE       496
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       497
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T21,T22
1	0	Covered	T11,T21,T22

 LINE       498
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T22,T5
1	0	Covered	T11,T22,T5

 LINE       499
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T19
1	0	Covered	T1,T11,T19

 LINE       500
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T42,T22
1	0	Covered	T4,T42,T22

 LINE       501
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T26
1	0	Covered	T11,T5,T15

 LINE       502
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Covered	T63,T64,T65
1	0	0	Covered	T63,T64,T65

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T66,T67,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T66,T67,T68

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T66,T67,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T66,T67,T68

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T66,T67,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T66,T67,T68

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Not Covered

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Not Covered

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Not Covered

 LINE       593
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T66,T67,T68

 LINE       593
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T66,T67,T68

 LINE       593
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T66,T67,T68

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	106	93	87.74
Total Bits	7434	6528	87.81
Total Bits 0->1	3717	3264	87.81
Total Bits 1->0	3717	3264	87.81

Ports	106	93	87.74
Port Bits	7434	6528	87.81
Port Bits 0->1	3717	3264	87.81
Port Bits 1->0	3717	3264	87.81

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
rst_ni	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
clk_kmac_i	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
rst_kmac_ni	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.d_ready	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_address[31:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_source[7:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_size[1:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_i.a_valid	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
tl_o.a_ready	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_error	Yes	Yes	T69,T71,T72	Yes	T69,T73,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T46,T69,*T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T73,T71	Yes	T69,T73,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
jtag_i.tdi	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
jtag_i.trst_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
jtag_i.tms	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
jtag_i.tck	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
jtag_o.tdo_oe	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
jtag_o.tdo	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
scan_rst_ni	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T46,T70,T74	Yes	T46,T70,T74	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T46,T70,T74	Yes	T46,T70,T74	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
strap_en_override_o	No	No		No		OUTPUT
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.status[1:0]	No	No		No		INPUT
lc_otp_vendor_test_i.status[2]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[3]	No	No		No		INPUT
lc_otp_vendor_test_i.status[4]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[6:5]	No	No		No		INPUT
lc_otp_vendor_test_i.status[9:7]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[13:10]	No	No		No		INPUT
lc_otp_vendor_test_i.status[20:14]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[21]	No	No		No		INPUT
lc_otp_vendor_test_i.status[22]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
lc_otp_vendor_test_i.status[23]	No	No		No		INPUT
lc_otp_vendor_test_i.status[31:24]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
lc_otp_program_o.count[4:0]	Yes	Yes	T10,T12,T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[5]	No	No		No		OUTPUT
lc_otp_program_o.count[7:6]	Yes	Yes	T10,T12,T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[8]	No	No		No		OUTPUT
lc_otp_program_o.count[10:9]	Yes	Yes	T10,T12,T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[11]	No	No		No		OUTPUT
lc_otp_program_o.count[13:12]	Yes	Yes	T10,T12,T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[14]	No	No		No		OUTPUT
lc_otp_program_o.count[51:15]	Yes	Yes	*T10,*T12,*T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[52]	No	No		No		OUTPUT
lc_otp_program_o.count[55:53]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
lc_otp_program_o.count[56]	No	No		No		OUTPUT
lc_otp_program_o.count[59:57]	Yes	Yes	T10,T12,T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[61:60]	No	No		No		OUTPUT
lc_otp_program_o.count[159:62]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[160]	No	No		No		OUTPUT
lc_otp_program_o.count[162:161]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[163]	No	No		No		OUTPUT
lc_otp_program_o.count[167:164]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[168]	No	No		No		OUTPUT
lc_otp_program_o.count[169]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[170]	No	No		No		OUTPUT
lc_otp_program_o.count[174:171]	Yes	Yes	*T42,*T28,*T77	Yes	T42,T28,T77	OUTPUT
lc_otp_program_o.count[175]	No	No		No		OUTPUT
lc_otp_program_o.count[196:176]	Yes	Yes	*T10,*T12,*T13	Yes	T42,T5,T15	OUTPUT
lc_otp_program_o.count[197]	No	No		No		OUTPUT
lc_otp_program_o.count[200:198]	Yes	Yes	*T10,*T12,*T13	Yes	T5,T15,T26	OUTPUT
lc_otp_program_o.count[201]	No	No		No		OUTPUT
lc_otp_program_o.count[205:202]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.count[206]	No	No		No		OUTPUT
lc_otp_program_o.count[209:207]	Yes	Yes	*T10,*T12,*T13	Yes	T42,T28,T16	OUTPUT
lc_otp_program_o.count[211:210]	No	No		No		OUTPUT
lc_otp_program_o.count[213:212]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[214]	No	No		No		OUTPUT
lc_otp_program_o.count[215]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.count[218:216]	No	No		No		OUTPUT
lc_otp_program_o.count[220:219]	Yes	Yes	T46,T70,T75	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.count[222:221]	No	No		No		OUTPUT
lc_otp_program_o.count[274:223]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[275]	No	No		No		OUTPUT
lc_otp_program_o.count[278:276]	Yes	Yes	T10,T12,T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[280:279]	No	No		No		OUTPUT
lc_otp_program_o.count[281]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[282]	No	No		No		OUTPUT
lc_otp_program_o.count[283]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.count[285:284]	No	No		No		OUTPUT
lc_otp_program_o.count[305:286]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[306]	No	No		No		OUTPUT
lc_otp_program_o.count[307]	Yes	Yes	*T10,*T12,*T13	Yes	T5,T15,T26	OUTPUT
lc_otp_program_o.count[308]	No	No		No		OUTPUT
lc_otp_program_o.count[310:309]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.count[311]	No	No		No		OUTPUT
lc_otp_program_o.count[370:312]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.count[372:371]	No	No		No		OUTPUT
lc_otp_program_o.count[375:373]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.count[376]	No	No		No		OUTPUT
lc_otp_program_o.count[380:377]	Yes	Yes	*T10,*T12,*T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.count[381]	No	No		No		OUTPUT
lc_otp_program_o.count[383:382]	Yes	Yes	T10,T12,T13	Yes	T16,T17,T18	OUTPUT
lc_otp_program_o.state[31:0]	Yes	Yes	*T5,*T15,*T26	Yes	T5,T15,T26	OUTPUT
lc_otp_program_o.state[32]	No	No		No		OUTPUT
lc_otp_program_o.state[41:33]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[42]	No	No		No		OUTPUT
lc_otp_program_o.state[46:43]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[47]	No	No		No		OUTPUT
lc_otp_program_o.state[85:48]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[86]	No	No		No		OUTPUT
lc_otp_program_o.state[88:87]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[89]	No	No		No		OUTPUT
lc_otp_program_o.state[240:90]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[241]	No	No		No		OUTPUT
lc_otp_program_o.state[243:242]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[244]	No	No		No		OUTPUT
lc_otp_program_o.state[251:245]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	OUTPUT
lc_otp_program_o.state[252]	No	No		No		OUTPUT
lc_otp_program_o.state[254:253]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
lc_otp_program_o.state[255]	No	No		No		OUTPUT
lc_otp_program_o.state[319:256]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_otp_program_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_otp_program_i.err	Yes	Yes	T5,T15,T26	Yes	T5,T15,T26	INPUT
kmac_data_i.error	Yes	Yes	T11,T5,T15	Yes	T11,T5,T15	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
kmac_data_i.done	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
kmac_data_i.ready	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
kmac_data_o.last	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
kmac_data_o.valid	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T69,T71,T72	Yes	T46,T69,T70	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T22,T40,T45	Yes	T22,T40,T45	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T46,T70,T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T46,T70,T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T22,T40,T45	Yes	T22,T40,T45	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T22,T40,T45	Yes	T22,T40,T45	INPUT
otp_lc_data_i.count[4:0]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[5]	No	No		No		INPUT
otp_lc_data_i.count[7:6]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[8]	No	No		No		INPUT
otp_lc_data_i.count[10:9]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[11]	No	No		No		INPUT
otp_lc_data_i.count[13:12]	Yes	Yes	T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[14]	No	No		No		INPUT
otp_lc_data_i.count[51:15]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[52]	No	No		No		INPUT
otp_lc_data_i.count[55:53]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
otp_lc_data_i.count[56]	No	No		No		INPUT
otp_lc_data_i.count[59:57]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[61:60]	No	No		No		INPUT
otp_lc_data_i.count[159:62]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[160]	No	No		No		INPUT
otp_lc_data_i.count[162:161]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[163]	No	No		No		INPUT
otp_lc_data_i.count[165:164]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[166]	No	No		No		INPUT
otp_lc_data_i.count[167]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[168]	No	No		No		INPUT
otp_lc_data_i.count[169]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[171:170]	No	No		No		INPUT
otp_lc_data_i.count[174:172]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[175]	No	No		No		INPUT
otp_lc_data_i.count[195:176]	Yes	Yes	*T42,*T5,*T15	Yes	T42,T5,T15	INPUT
otp_lc_data_i.count[197:196]	No	No		No		INPUT
otp_lc_data_i.count[198]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[199]	No	No		No		INPUT
otp_lc_data_i.count[200]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[201]	No	No		No		INPUT
otp_lc_data_i.count[205:202]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[206]	No	No		No		INPUT
otp_lc_data_i.count[209:207]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[211:210]	No	No		No		INPUT
otp_lc_data_i.count[213:212]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[214]	No	No		No		INPUT
otp_lc_data_i.count[215]	Yes	Yes	*T46,*T70,*T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[218:216]	No	No		No		INPUT
otp_lc_data_i.count[220:219]	Yes	Yes	T46,T70,T75	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[222:221]	No	No		No		INPUT
otp_lc_data_i.count[274:223]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[275]	No	No		No		INPUT
otp_lc_data_i.count[278:276]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[280:279]	No	No		No		INPUT
otp_lc_data_i.count[281]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[282]	No	No		No		INPUT
otp_lc_data_i.count[283]	Yes	Yes	*T69,*T71,*T75	Yes	T69,T71,T75	INPUT
otp_lc_data_i.count[285:284]	No	No		No		INPUT
otp_lc_data_i.count[303:286]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[304]	No	No		No		INPUT
otp_lc_data_i.count[305]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[306]	No	No		No		INPUT
otp_lc_data_i.count[307]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[308]	No	No		No		INPUT
otp_lc_data_i.count[310:309]	Yes	Yes	*T75,*T81,*T78	Yes	T75,T81,T78	INPUT
otp_lc_data_i.count[311]	No	No		No		INPUT
otp_lc_data_i.count[314:312]	Yes	Yes	T75,T81,T78	Yes	T75,T81,T78	INPUT
otp_lc_data_i.count[315]	No	No		No		INPUT
otp_lc_data_i.count[370:316]	Yes	Yes	*T75,*T81,*T78	Yes	T75,T81,T78	INPUT
otp_lc_data_i.count[372:371]	No	No		No		INPUT
otp_lc_data_i.count[375:373]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.count[376]	No	No		No		INPUT
otp_lc_data_i.count[380:377]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.count[381]	No	No		No		INPUT
otp_lc_data_i.count[383:382]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
otp_lc_data_i.state[31:0]	Yes	Yes	*T5,*T15,*T26	Yes	T5,T15,T26	INPUT
otp_lc_data_i.state[32]	No	No		No		INPUT
otp_lc_data_i.state[41:33]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[42]	No	No		No		INPUT
otp_lc_data_i.state[46:43]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[47]	No	No		No		INPUT
otp_lc_data_i.state[84:48]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[86:85]	No	No		No		INPUT
otp_lc_data_i.state[88:87]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[89]	No	No		No		INPUT
otp_lc_data_i.state[240:90]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[241]	No	No		No		INPUT
otp_lc_data_i.state[243:242]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[245:244]	No	No		No		INPUT
otp_lc_data_i.state[251:246]	Yes	Yes	*T1,*T2,*T3	Yes	T69,T71,T72	INPUT
otp_lc_data_i.state[252]	No	No		No		INPUT
otp_lc_data_i.state[254:253]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
otp_lc_data_i.state[255]	No	No		No		INPUT
otp_lc_data_i.state[319:256]	Yes	Yes	T78,T79,T80	Yes	T69,T71,T72	INPUT
otp_lc_data_i.error	Yes	Yes	T11,T5,T15	Yes	T11,T5,T15	INPUT
otp_lc_data_i.valid	Yes	Yes	T4,T42,T24	Yes	T4,T42,T24	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T75	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T1,T9,T4	Yes	T78,T79,T80	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T2,T3,T11	Yes	T2,T3,T11	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
lc_flash_rma_ack_i[3:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T69,T71,T72	Yes	T69,T71,T72	OUTPUT
otp_device_id_i[1:0]	No	No		No		INPUT
otp_device_id_i[2]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[3]	No	No		No		INPUT
otp_device_id_i[5:4]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[9:6]	No	No		No		INPUT
otp_device_id_i[11:10]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[12]	No	No		No		INPUT
otp_device_id_i[13]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[18:14]	No	No		No		INPUT
otp_device_id_i[19]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[21:20]	No	No		No		INPUT
otp_device_id_i[23:22]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[25:24]	No	No		No		INPUT
otp_device_id_i[26]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[29:27]	No	No		No		INPUT
otp_device_id_i[30]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[31]	No	No		No		INPUT
otp_device_id_i[32]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[35:33]	No	No		No		INPUT
otp_device_id_i[36]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[38:37]	No	No		No		INPUT
otp_device_id_i[40:39]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[41]	No	No		No		INPUT
otp_device_id_i[42]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[43]	No	No		No		INPUT
otp_device_id_i[44]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[45]	No	No		No		INPUT
otp_device_id_i[46]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[49:47]	No	No		No		INPUT
otp_device_id_i[51:50]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[52]	No	No		No		INPUT
otp_device_id_i[55:53]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[58:56]	No	No		No		INPUT
otp_device_id_i[59]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[60]	No	No		No		INPUT
otp_device_id_i[61]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[65:62]	No	No		No		INPUT
otp_device_id_i[69:66]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[71:70]	No	No		No		INPUT
otp_device_id_i[72]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[75:73]	No	No		No		INPUT
otp_device_id_i[78:76]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[79]	No	No		No		INPUT
otp_device_id_i[81:80]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[82]	No	No		No		INPUT
otp_device_id_i[84:83]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[85]	No	No		No		INPUT
otp_device_id_i[86]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[87]	No	No		No		INPUT
otp_device_id_i[88]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[90:89]	No	No		No		INPUT
otp_device_id_i[91]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[92]	No	No		No		INPUT
otp_device_id_i[93]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[94]	No	No		No		INPUT
otp_device_id_i[95]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[96]	No	No		No		INPUT
otp_device_id_i[97]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[100:98]	No	No		No		INPUT
otp_device_id_i[102:101]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[103]	No	No		No		INPUT
otp_device_id_i[104]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[107:105]	No	No		No		INPUT
otp_device_id_i[110:108]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[112:111]	No	No		No		INPUT
otp_device_id_i[113]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[118:114]	No	No		No		INPUT
otp_device_id_i[121:119]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[122]	No	No		No		INPUT
otp_device_id_i[123]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[125:124]	No	No		No		INPUT
otp_device_id_i[131:126]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[133:132]	No	No		No		INPUT
otp_device_id_i[134]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[139:135]	No	No		No		INPUT
otp_device_id_i[140]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[141]	No	No		No		INPUT
otp_device_id_i[142]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[144:143]	No	No		No		INPUT
otp_device_id_i[146:145]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[149:147]	No	No		No		INPUT
otp_device_id_i[150]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[151]	No	No		No		INPUT
otp_device_id_i[152]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[153]	No	No		No		INPUT
otp_device_id_i[154]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[155]	No	No		No		INPUT
otp_device_id_i[157:156]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[158]	No	No		No		INPUT
otp_device_id_i[160:159]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[162:161]	No	No		No		INPUT
otp_device_id_i[164:163]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[165]	No	No		No		INPUT
otp_device_id_i[166]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[167]	No	No		No		INPUT
otp_device_id_i[170:168]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[171]	No	No		No		INPUT
otp_device_id_i[174:172]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[175]	No	No		No		INPUT
otp_device_id_i[177:176]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[179:178]	No	No		No		INPUT
otp_device_id_i[180]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[182:181]	No	No		No		INPUT
otp_device_id_i[185:183]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[192:186]	No	No		No		INPUT
otp_device_id_i[193]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[195:194]	No	No		No		INPUT
otp_device_id_i[197:196]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[198]	No	No		No		INPUT
otp_device_id_i[199]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[200]	No	No		No		INPUT
otp_device_id_i[207:201]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[208]	No	No		No		INPUT
otp_device_id_i[210:209]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[214:211]	No	No		No		INPUT
otp_device_id_i[215]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[216]	No	No		No		INPUT
otp_device_id_i[217]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[218]	No	No		No		INPUT
otp_device_id_i[220:219]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[223:221]	No	No		No		INPUT
otp_device_id_i[225:224]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[226]	No	No		No		INPUT
otp_device_id_i[227]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[228]	No	No		No		INPUT
otp_device_id_i[233:229]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[234]	No	No		No		INPUT
otp_device_id_i[235]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[236]	No	No		No		INPUT
otp_device_id_i[237]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[239:238]	No	No		No		INPUT
otp_device_id_i[240]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[243:241]	No	No		No		INPUT
otp_device_id_i[244]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[246:245]	No	No		No		INPUT
otp_device_id_i[247]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[249:248]	No	No		No		INPUT
otp_device_id_i[250]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[251]	No	No		No		INPUT
otp_device_id_i[254:252]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_device_id_i[255]	No	No		No		INPUT
otp_manuf_state_i[0]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[1]	No	No		No		INPUT
otp_manuf_state_i[5:2]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[6]	No	No		No		INPUT
otp_manuf_state_i[7]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[8]	No	No		No		INPUT
otp_manuf_state_i[9]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[12:10]	No	No		No		INPUT
otp_manuf_state_i[15:13]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[16]	No	No		No		INPUT
otp_manuf_state_i[17]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[20:18]	No	No		No		INPUT
otp_manuf_state_i[21]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[27:22]	No	No		No		INPUT
otp_manuf_state_i[28]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[30:29]	No	No		No		INPUT
otp_manuf_state_i[31]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[32]	No	No		No		INPUT
otp_manuf_state_i[34:33]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[35]	No	No		No		INPUT
otp_manuf_state_i[38:36]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[39]	No	No		No		INPUT
otp_manuf_state_i[41:40]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[43:42]	No	No		No		INPUT
otp_manuf_state_i[44]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[46:45]	No	No		No		INPUT
otp_manuf_state_i[48:47]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[49]	No	No		No		INPUT
otp_manuf_state_i[52:50]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[53]	No	No		No		INPUT
otp_manuf_state_i[55:54]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[57:56]	No	No		No		INPUT
otp_manuf_state_i[59:58]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[62:60]	No	No		No		INPUT
otp_manuf_state_i[63]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[68:64]	No	No		No		INPUT
otp_manuf_state_i[70:69]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[72:71]	No	No		No		INPUT
otp_manuf_state_i[73]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[75:74]	No	No		No		INPUT
otp_manuf_state_i[77:76]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[78]	No	No		No		INPUT
otp_manuf_state_i[80:79]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[82:81]	No	No		No		INPUT
otp_manuf_state_i[83]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[84]	No	No		No		INPUT
otp_manuf_state_i[87:85]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[93:88]	No	No		No		INPUT
otp_manuf_state_i[96:94]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[97]	No	No		No		INPUT
otp_manuf_state_i[99:98]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[100]	No	No		No		INPUT
otp_manuf_state_i[102:101]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[103]	No	No		No		INPUT
otp_manuf_state_i[104]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[105]	No	No		No		INPUT
otp_manuf_state_i[107:106]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[108]	No	No		No		INPUT
otp_manuf_state_i[109]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[110]	No	No		No		INPUT
otp_manuf_state_i[113:111]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[114]	No	No		No		INPUT
otp_manuf_state_i[116:115]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[119:117]	No	No		No		INPUT
otp_manuf_state_i[120]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[121]	No	No		No		INPUT
otp_manuf_state_i[123:122]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[124]	No	No		No		INPUT
otp_manuf_state_i[125]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[126]	No	No		No		INPUT
otp_manuf_state_i[127]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[128]	No	No		No		INPUT
otp_manuf_state_i[129]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[132:130]	No	No		No		INPUT
otp_manuf_state_i[134:133]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[135]	No	No		No		INPUT
otp_manuf_state_i[136]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[138:137]	No	No		No		INPUT
otp_manuf_state_i[139]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[141:140]	No	No		No		INPUT
otp_manuf_state_i[143:142]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[144]	No	No		No		INPUT
otp_manuf_state_i[145]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[147:146]	No	No		No		INPUT
otp_manuf_state_i[149:148]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[151:150]	No	No		No		INPUT
otp_manuf_state_i[153:152]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[159:154]	No	No		No		INPUT
otp_manuf_state_i[160]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[163:161]	No	No		No		INPUT
otp_manuf_state_i[165:164]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[166]	No	No		No		INPUT
otp_manuf_state_i[167]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[170:168]	No	No		No		INPUT
otp_manuf_state_i[171]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[172]	No	No		No		INPUT
otp_manuf_state_i[173]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[176:174]	No	No		No		INPUT
otp_manuf_state_i[178:177]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[179]	No	No		No		INPUT
otp_manuf_state_i[180]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[184:181]	No	No		No		INPUT
otp_manuf_state_i[186:185]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[188:187]	No	No		No		INPUT
otp_manuf_state_i[191:189]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[192]	No	No		No		INPUT
otp_manuf_state_i[193]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[195:194]	No	No		No		INPUT
otp_manuf_state_i[197:196]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[198]	No	No		No		INPUT
otp_manuf_state_i[199]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[204:200]	No	No		No		INPUT
otp_manuf_state_i[206:205]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[207]	No	No		No		INPUT
otp_manuf_state_i[208]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[209]	No	No		No		INPUT
otp_manuf_state_i[210]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[211]	No	No		No		INPUT
otp_manuf_state_i[214:212]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[218:215]	No	No		No		INPUT
otp_manuf_state_i[221:219]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[224:222]	No	No		No		INPUT
otp_manuf_state_i[227:225]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[228]	No	No		No		INPUT
otp_manuf_state_i[229]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[231:230]	No	No		No		INPUT
otp_manuf_state_i[233:232]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[234]	No	No		No		INPUT
otp_manuf_state_i[237:235]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[245:238]	No	No		No		INPUT
otp_manuf_state_i[246]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[247]	No	No		No		INPUT
otp_manuf_state_i[249:248]	Yes	Yes	T46,T69,T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[250]	No	No		No		INPUT
otp_manuf_state_i[251]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[253:252]	No	No		No		INPUT
otp_manuf_state_i[254]	Yes	Yes	*T46,*T69,*T70	Yes	T46,T69,T70	INPUT
otp_manuf_state_i[255]	No	No		No		INPUT
hw_rev_o.reserved[23:0]	No	No		No		OUTPUT
hw_rev_o.revision_id[7:0]	No	No		No		OUTPUT
hw_rev_o.product_id[15:0]	No	No		No		OUTPUT
hw_rev_o.silicon_creator_id[15:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
IF	344	3	3	100.00
IF	378	3	3	100.00
IF	389	18	18	100.00
IF	464	3	3	100.00
IF	666	2	2	100.00
IF	523	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	344	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-2-:	353	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T1,T3,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	378	if ((prim_mubi_pkg::mubi8_test_false_loose(sw_claim_transition_if_q) && tap_reg2hw.claim_transition_if.qe))
-2-:	382	if ((prim_mubi_pkg::mubi8_test_false_loose(tap_claim_transition_if_q) && reg2hw.claim_transition_if.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T1,T3,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if (lc_idle_d)
-2-:	391	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-3-:	395	if (tap_reg2hw.transition_ctrl.ext_clock_en.qe)
-4-:	404	if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-5-:	415	if (tap_reg2hw.transition_target.qe)
-6-:	422	if (tap_reg2hw.otp_vendor_test_ctrl.qe)
-7-:	425	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))
-8-:	429	if (reg2hw.transition_ctrl.ext_clock_en.qe)
-9-:	438	if (reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-10-:	449	if (reg2hw.transition_target.qe)
-11-:	456	if (reg2hw.otp_vendor_test_ctrl.qe)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T25
1	1	0	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	1	-	-	-	-	-	-	-	Covered	T2,T5,T25
1	1	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	-	1	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	-	0	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	-	-	1	-	-	-	-	-	Covered	T2,T4,T5
1	1	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T5
1	0	-	-	-	-	1	1	-	-	-	Covered	T3,T10,T12
1	0	-	-	-	-	1	0	-	-	-	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	1	-	-	Covered	T3,T10,T12
1	0	-	-	-	-	1	-	0	-	-	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	-	1	-	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	-	0	-	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	-	-	1	Covered	T1,T3,T9
1	0	-	-	-	-	1	-	-	-	0	Covered	T1,T3,T9
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	489	if (((SecVolatileRawUnlockEn && transition_cmd) && (!volatile_raw_unlock_q)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	666	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	523	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	27	84.38
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	27	84.38

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	145284390	141995440	0	0
DecLcCountWidthCheck_A	795	795	0	0
DecLcIdStateWidthCheck_A	795	795	0	0
DecLcStateWidthCheck_A	795	795	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	141861700	0	0	0
FpvSecCmCtrlLcCntCheck_A	138671950	0	0	0
FpvSecCmCtrlLcFsmCheck_A	142967940	0	0	0
FpvSecCmCtrlLcStateCheck_A	138473540	0	0	0
FpvSecCmRegWeOnehotCheck_A	145284390	100	0	0
FpvSecCmTapRegWeOnehotCheck_A	145284390	0	0	0
LcCheckBypassEnKnown_A	145284390	141995440	0	0
LcClkBypReqKnown_A	145284390	141995440	0	0
LcCpuEnKnown_A	145284390	141995440	0	0
LcCreatorSwRwEn_A	145284390	141995440	0	0
LcDftEnKnown_A	145284390	141995440	0	0
LcEscalateEnKnown_A	145284390	141995440	0	0
LcFlashRmaReqKnown_A	145284390	141995440	0	0
LcFlashRmaSeedKnown_A	145284390	141995440	0	0
LcHwDebugEnKnown_A	145284390	141995440	0	0
LcIsoSwRwEn_A	145284390	141995440	0	0
LcIsoSwWrEn_A	145284390	141995440	0	0
LcKeymgrDiv_A	145284390	141995440	0	0
LcKeymgrEnKnown_A	145284390	141995440	0	0
LcNvmDebugEnKnown_A	145284390	141995440	0	0
LcOtpProgramKnown_A	145284390	141995440	0	0
LcOtpTokenKnown_A	145284390	141995440	0	0
LcOwnerSwRwEn_A	145284390	141995440	0	0
LcSeedHwRdEn_A	145284390	141995440	0	0
NumTokenWordsCheck_A	795	795	0	0
OtpTestCtrlWidth_A	795	795	0	0
PwrLcKnown_A	145284390	141995440	0	0
TlOKnown	145284390	141995440	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141861700	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138671950	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142967940	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138473540	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	100	0	0
T63	21642	20	0	0
T64	21642	20	0	0
T65	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	2362	0	0	0
T85	2362	0	0	0
T86	16312	0	0	0
T87	27280	0	0	0
T88	16312	0	0	0
T89	8921	0	0	0
T90	56567	0	0	0
T91	75534	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	145284390	141995440	0	0
T1	8921	7511	0	0
T2	75534	74131	0	0
T3	16312	14909	0	0
T4	83514	82566	0	0
T9	35018	30361	0	0
T10	918	862	0	0
T11	54803	49285	0	0
T12	918	862	0	0
T13	918	862	0	0
T14	918	862	0	0