LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.400s	1.733ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.040s	73.400us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	16.469us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.130s	327.136us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.770s	138.087us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.120s	28.355us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	16.469us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	138.087us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.970s	92.774us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.760s	432.267us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	13.732us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.280s	3.673ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.650s	2.991ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_prog_failure	5.280s	3.673ms	50	50	100.00
		lc_ctrl_errors	26.650s	2.991ms	50	50	100.00
		lc_ctrl_security_escalation	14.580s	1.826ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.367m	9.116ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.750s	2.013ms	20	20	100.00
		lc_ctrl_jtag_errors	1.822m	4.002ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.250s	2.376ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.370s	1.298ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.750s	2.013ms	20	20	100.00
		lc_ctrl_jtag_errors	1.822m	4.002ms	20	20	100.00
		lc_ctrl_jtag_access	30.520s	5.357ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.440s	5.552ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.760s	264.751us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.950s	55.730us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.540s	2.426ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.090s	2.368ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.980s	47.300us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.320s	782.165us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.630s	163.319us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	26.980s	1.243ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.400s	20.024us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.387m	71.712ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.300s	28.355us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.780s	130.188us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.780s	130.188us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.040s	73.400us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	16.469us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	138.087us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	45.797us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.040s	73.400us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	16.469us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	138.087us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	45.797us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.130s	450.102us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.130s	450.102us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.760s	432.267us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.180s	1.380ms	50	50	100.00
		lc_ctrl_sec_cm	25.550s	1.313ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.580s	1.826ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.970s	92.774us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.370s	1.298ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.970s	1.707ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.970s	1.707ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.250s	1.554ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.580s	946.684us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.580s	946.684us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.365h	40.859ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.82	95.93	93.31	100.00	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.99496707418679827960195942913610773352648715721339744342331306206173142607965
      Line 367, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 109408715 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 109408715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.30647210858919167486229820126416722548701761980571318642479086311461732486799
      Line 17928, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22940109348 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22940109348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.114917988142710146968369325504213254543941217691440621274741492360021574081338
      Line 18204, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 307890122165 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 307890122165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.lc_ctrl_stress_all_with_rand_reset.107476928448349130387556871289213224903023780774197707184768459166383330224659
      Line 24481, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12578328349 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 12578328349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.110093655741215655209816297249855959347944436445212679048341800812091617490646
      Line 55299, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 42.lc_ctrl_stress_all_with_rand_reset.26059269419680433735927758614086753453310091237609667408840335384492534090701
      Line 39314, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.2052576061028193525329354093012318782059031330456620804176108765744535386556
      Line 13601, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7900608024 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7900608024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.lc_ctrl_stress_all_with_rand_reset.10072027721806256098063754321420291188227005650189091038298594524322384952232
      Line 16091, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17104434589 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 17104434589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 2.lc_ctrl_jtag_priority.18325059598188980793413208466419696906292379113643139489178271392587150493308
      Line 461, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10013739322 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10013739322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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