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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.00 97.92 95.84 93.40 97.62 98.52 99.25 96.47


Total test records in report: 999
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T384 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2328496254 Aug 24 08:42:00 PM UTC 24 Aug 24 08:42:23 PM UTC 24 5794136652 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.3689545717 Aug 24 08:42:10 PM UTC 24 Aug 24 08:42:23 PM UTC 24 297693965 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2775537444 Aug 24 08:41:50 PM UTC 24 Aug 24 08:42:23 PM UTC 24 3546699446 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3396389993 Aug 24 08:41:28 PM UTC 24 Aug 24 08:42:23 PM UTC 24 4986678305 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2776382378 Aug 24 08:42:21 PM UTC 24 Aug 24 08:42:23 PM UTC 24 14708098 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.4115420412 Aug 24 08:42:16 PM UTC 24 Aug 24 08:42:23 PM UTC 24 605829138 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.564328879 Aug 24 08:42:05 PM UTC 24 Aug 24 08:42:23 PM UTC 24 3386497558 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.109535289 Aug 24 08:42:06 PM UTC 24 Aug 24 08:42:24 PM UTC 24 456592869 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3382163406 Aug 24 08:41:32 PM UTC 24 Aug 24 08:42:24 PM UTC 24 2599144234 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3666328204 Aug 24 08:42:12 PM UTC 24 Aug 24 08:42:25 PM UTC 24 606132156 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.954743506 Aug 24 08:41:42 PM UTC 24 Aug 24 08:42:25 PM UTC 24 333306110 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2269512705 Aug 24 08:41:46 PM UTC 24 Aug 24 08:42:25 PM UTC 24 3700009121 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.96310757 Aug 24 08:42:20 PM UTC 24 Aug 24 08:42:25 PM UTC 24 54100830 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.751428388 Aug 24 08:42:22 PM UTC 24 Aug 24 08:42:26 PM UTC 24 72503578 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2988624788 Aug 24 08:42:24 PM UTC 24 Aug 24 08:42:26 PM UTC 24 33002750 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.3484404626 Aug 24 08:42:15 PM UTC 24 Aug 24 08:42:27 PM UTC 24 271435822 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2868620443 Aug 24 08:42:25 PM UTC 24 Aug 24 08:42:27 PM UTC 24 14949548 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.1989709850 Aug 24 08:42:25 PM UTC 24 Aug 24 08:42:28 PM UTC 24 14450379 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.4183824094 Aug 24 08:42:25 PM UTC 24 Aug 24 08:42:29 PM UTC 24 97307300 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3322445134 Aug 24 08:42:24 PM UTC 24 Aug 24 08:42:29 PM UTC 24 1111867431 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.3196222113 Aug 24 08:42:12 PM UTC 24 Aug 24 08:42:30 PM UTC 24 1344946133 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.1802119593 Aug 24 08:42:15 PM UTC 24 Aug 24 08:42:30 PM UTC 24 367575394 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2334021454 Aug 24 08:42:26 PM UTC 24 Aug 24 08:42:31 PM UTC 24 124810216 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3601886629 Aug 24 08:42:12 PM UTC 24 Aug 24 08:42:32 PM UTC 24 781310331 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1994833380 Aug 24 08:42:17 PM UTC 24 Aug 24 08:42:32 PM UTC 24 756696932 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.342302572 Aug 24 08:42:16 PM UTC 24 Aug 24 08:42:32 PM UTC 24 726053112 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.2779112519 Aug 24 08:42:16 PM UTC 24 Aug 24 08:42:33 PM UTC 24 1363767268 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.280627845 Aug 24 08:42:22 PM UTC 24 Aug 24 08:42:34 PM UTC 24 56693662 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.1157931065 Aug 24 08:42:32 PM UTC 24 Aug 24 08:42:34 PM UTC 24 13734958 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1683311937 Aug 24 08:42:19 PM UTC 24 Aug 24 08:42:34 PM UTC 24 245760172 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3500120167 Aug 24 08:42:11 PM UTC 24 Aug 24 08:42:34 PM UTC 24 2864459291 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.1193616579 Aug 24 08:42:22 PM UTC 24 Aug 24 08:42:35 PM UTC 24 3749178022 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.823605292 Aug 24 08:42:33 PM UTC 24 Aug 24 08:42:35 PM UTC 24 14861518 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.2696933829 Aug 24 08:42:24 PM UTC 24 Aug 24 08:42:36 PM UTC 24 651234443 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.692260847 Aug 24 08:42:22 PM UTC 24 Aug 24 08:42:36 PM UTC 24 471574507 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1843051564 Aug 24 08:42:25 PM UTC 24 Aug 24 08:42:36 PM UTC 24 232304400 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1653392182 Aug 24 08:41:14 PM UTC 24 Aug 24 08:42:36 PM UTC 24 5225550723 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.2067621720 Aug 24 08:42:27 PM UTC 24 Aug 24 08:42:36 PM UTC 24 1216656621 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.374730716 Aug 24 08:41:47 PM UTC 24 Aug 24 08:42:37 PM UTC 24 270100309 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1899541763 Aug 24 08:42:24 PM UTC 24 Aug 24 08:42:37 PM UTC 24 968182932 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.1206944083 Aug 24 08:42:43 PM UTC 24 Aug 24 08:42:46 PM UTC 24 44145378 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.1773756482 Aug 24 08:42:24 PM UTC 24 Aug 24 08:42:37 PM UTC 24 261565725 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2066322670 Aug 24 08:42:33 PM UTC 24 Aug 24 08:42:37 PM UTC 24 71581145 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.1005897560 Aug 24 08:41:55 PM UTC 24 Aug 24 08:42:38 PM UTC 24 6050789871 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.252631917 Aug 24 08:42:26 PM UTC 24 Aug 24 08:42:38 PM UTC 24 625642972 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.80861067 Aug 24 08:41:51 PM UTC 24 Aug 24 08:42:38 PM UTC 24 1130432588 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.4142640896 Aug 24 08:42:19 PM UTC 24 Aug 24 08:42:39 PM UTC 24 1351054311 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.3262555258 Aug 24 08:42:35 PM UTC 24 Aug 24 08:42:40 PM UTC 24 72134677 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.2940570802 Aug 24 08:42:38 PM UTC 24 Aug 24 08:42:41 PM UTC 24 18094655 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2078304868 Aug 24 08:42:22 PM UTC 24 Aug 24 08:42:41 PM UTC 24 1456390928 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2188964877 Aug 24 08:42:01 PM UTC 24 Aug 24 08:42:41 PM UTC 24 2149736325 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3786784767 Aug 24 08:42:19 PM UTC 24 Aug 24 08:42:41 PM UTC 24 832757265 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.454140342 Aug 24 08:42:35 PM UTC 24 Aug 24 08:42:41 PM UTC 24 1284080963 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2091672863 Aug 24 08:42:39 PM UTC 24 Aug 24 08:42:41 PM UTC 24 43556048 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3009643596 Aug 24 08:41:59 PM UTC 24 Aug 24 08:42:42 PM UTC 24 817811842 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.4044709778 Aug 24 08:42:38 PM UTC 24 Aug 24 08:42:42 PM UTC 24 364905986 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.996332433 Aug 24 08:42:22 PM UTC 24 Aug 24 08:42:42 PM UTC 24 3601707053 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.3164261427 Aug 24 08:42:25 PM UTC 24 Aug 24 08:42:42 PM UTC 24 1455339755 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.2517488596 Aug 24 08:41:50 PM UTC 24 Aug 24 08:42:42 PM UTC 24 1086063553 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.2641783711 Aug 24 08:42:02 PM UTC 24 Aug 24 08:42:42 PM UTC 24 263189592 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.605713378 Aug 24 08:41:14 PM UTC 24 Aug 24 08:42:43 PM UTC 24 11073345627 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1869170135 Aug 24 08:42:39 PM UTC 24 Aug 24 08:42:43 PM UTC 24 202108424 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.1987222222 Aug 24 08:42:28 PM UTC 24 Aug 24 08:42:44 PM UTC 24 1935128313 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.3822480978 Aug 24 08:42:16 PM UTC 24 Aug 24 08:42:44 PM UTC 24 2247876063 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.3680791938 Aug 24 08:42:38 PM UTC 24 Aug 24 08:42:44 PM UTC 24 97745634 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3086709696 Aug 24 08:41:37 PM UTC 24 Aug 24 08:42:47 PM UTC 24 14866339441 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1016095356 Aug 24 08:41:32 PM UTC 24 Aug 24 08:42:45 PM UTC 24 2659889177 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.157307637 Aug 24 08:41:14 PM UTC 24 Aug 24 08:42:45 PM UTC 24 31761808695 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2761378200 Aug 24 08:42:34 PM UTC 24 Aug 24 08:42:46 PM UTC 24 1784190605 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3719931005 Aug 24 08:42:44 PM UTC 24 Aug 24 08:42:47 PM UTC 24 16410539 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.4023874445 Aug 24 08:42:29 PM UTC 24 Aug 24 08:42:47 PM UTC 24 344479410 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.2732720130 Aug 24 08:42:27 PM UTC 24 Aug 24 08:42:47 PM UTC 24 2502926372 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.4203246762 Aug 24 08:42:44 PM UTC 24 Aug 24 08:42:47 PM UTC 24 125170438 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.4021605606 Aug 24 08:42:44 PM UTC 24 Aug 24 08:42:47 PM UTC 24 117797649 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.2716460156 Aug 24 08:42:06 PM UTC 24 Aug 24 08:42:48 PM UTC 24 1785963312 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2265721721 Aug 24 08:41:27 PM UTC 24 Aug 24 08:42:48 PM UTC 24 3577205030 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1622384520 Aug 24 08:42:41 PM UTC 24 Aug 24 08:42:48 PM UTC 24 363562407 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.1370857158 Aug 24 08:42:43 PM UTC 24 Aug 24 08:42:49 PM UTC 24 1079440396 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.1029635420 Aug 24 08:42:24 PM UTC 24 Aug 24 08:42:49 PM UTC 24 1927863205 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2526422869 Aug 24 08:42:31 PM UTC 24 Aug 24 08:42:49 PM UTC 24 432681045 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3785635386 Aug 24 08:42:46 PM UTC 24 Aug 24 08:42:50 PM UTC 24 70947331 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2067805990 Aug 24 08:42:40 PM UTC 24 Aug 24 08:42:51 PM UTC 24 210086344 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.3272339816 Aug 24 08:42:35 PM UTC 24 Aug 24 08:42:52 PM UTC 24 1132032864 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.2523837781 Aug 24 08:42:38 PM UTC 24 Aug 24 08:42:52 PM UTC 24 465514552 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.2982981770 Aug 24 08:42:50 PM UTC 24 Aug 24 08:42:53 PM UTC 24 197832360 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.790353120 Aug 24 08:42:51 PM UTC 24 Aug 24 08:42:53 PM UTC 24 20653496 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.4156760462 Aug 24 08:41:13 PM UTC 24 Aug 24 08:42:54 PM UTC 24 12159585326 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.2694185583 Aug 24 08:42:50 PM UTC 24 Aug 24 08:42:54 PM UTC 24 149987823 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.1255702136 Aug 24 08:42:12 PM UTC 24 Aug 24 08:42:55 PM UTC 24 3437304974 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.2733979998 Aug 24 08:41:14 PM UTC 24 Aug 24 08:42:55 PM UTC 24 7260570378 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.147720748 Aug 24 08:42:08 PM UTC 24 Aug 24 08:42:55 PM UTC 24 341385490 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.627402501 Aug 24 08:42:16 PM UTC 24 Aug 24 08:42:55 PM UTC 24 8113851026 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.1811615465 Aug 24 08:42:43 PM UTC 24 Aug 24 08:42:55 PM UTC 24 533630946 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.2109051614 Aug 24 08:42:43 PM UTC 24 Aug 24 08:42:55 PM UTC 24 434725928 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.1378163943 Aug 24 08:41:18 PM UTC 24 Aug 24 08:42:56 PM UTC 24 3650963548 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1903163114 Aug 24 08:42:48 PM UTC 24 Aug 24 08:42:56 PM UTC 24 1178045319 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.244387651 Aug 24 08:42:46 PM UTC 24 Aug 24 08:42:56 PM UTC 24 176265061 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.2491844729 Aug 24 08:42:47 PM UTC 24 Aug 24 08:42:56 PM UTC 24 205201667 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.240589119 Aug 24 08:42:38 PM UTC 24 Aug 24 08:42:57 PM UTC 24 944983494 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.1525974681 Aug 24 08:41:30 PM UTC 24 Aug 24 08:42:58 PM UTC 24 3353065929 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.189316773 Aug 24 08:42:43 PM UTC 24 Aug 24 08:42:58 PM UTC 24 2604643865 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.2141278697 Aug 24 08:42:28 PM UTC 24 Aug 24 08:42:58 PM UTC 24 1292397841 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.1461135808 Aug 24 08:42:53 PM UTC 24 Aug 24 08:42:58 PM UTC 24 338899855 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.3854062731 Aug 24 08:42:47 PM UTC 24 Aug 24 08:42:58 PM UTC 24 1141359209 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.972937911 Aug 24 08:42:41 PM UTC 24 Aug 24 08:42:58 PM UTC 24 378846857 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.4119700567 Aug 24 08:41:59 PM UTC 24 Aug 24 08:42:59 PM UTC 24 4503918906 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.207772115 Aug 24 08:42:43 PM UTC 24 Aug 24 08:42:59 PM UTC 24 1171443991 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.1993872749 Aug 24 08:42:38 PM UTC 24 Aug 24 08:42:59 PM UTC 24 487671394 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2727718666 Aug 24 08:42:57 PM UTC 24 Aug 24 08:43:00 PM UTC 24 45964612 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2818541892 Aug 24 08:42:57 PM UTC 24 Aug 24 08:43:00 PM UTC 24 43944328 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.560165431 Aug 24 08:42:48 PM UTC 24 Aug 24 08:43:01 PM UTC 24 740721009 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.3924337917 Aug 24 08:42:57 PM UTC 24 Aug 24 08:43:01 PM UTC 24 40869278 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.4106614901 Aug 24 08:42:35 PM UTC 24 Aug 24 08:43:02 PM UTC 24 749273930 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.860272757 Aug 24 08:42:36 PM UTC 24 Aug 24 08:43:02 PM UTC 24 2511813949 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3486305751 Aug 24 08:41:23 PM UTC 24 Aug 24 08:43:02 PM UTC 24 9362538834 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2588868754 Aug 24 08:43:00 PM UTC 24 Aug 24 08:43:02 PM UTC 24 18369456 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.633168342 Aug 24 08:41:45 PM UTC 24 Aug 24 08:43:02 PM UTC 24 2680090525 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3834833103 Aug 24 08:43:00 PM UTC 24 Aug 24 08:43:03 PM UTC 24 17240530 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2771225454 Aug 24 08:42:57 PM UTC 24 Aug 24 08:43:03 PM UTC 24 114399837 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3074115263 Aug 24 08:42:52 PM UTC 24 Aug 24 08:43:03 PM UTC 24 516337244 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.867563370 Aug 24 08:42:50 PM UTC 24 Aug 24 08:43:03 PM UTC 24 1011155803 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2178433939 Aug 24 08:43:01 PM UTC 24 Aug 24 08:43:04 PM UTC 24 30063740 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3486269924 Aug 24 08:42:44 PM UTC 24 Aug 24 08:43:04 PM UTC 24 1491354991 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.3969258916 Aug 24 08:42:39 PM UTC 24 Aug 24 08:43:05 PM UTC 24 578467790 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.1064227045 Aug 24 08:43:01 PM UTC 24 Aug 24 08:43:05 PM UTC 24 49964319 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2924602973 Aug 24 08:42:48 PM UTC 24 Aug 24 08:43:05 PM UTC 24 370536510 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.2741950367 Aug 24 08:42:43 PM UTC 24 Aug 24 08:43:06 PM UTC 24 428663383 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1156316418 Aug 24 08:42:56 PM UTC 24 Aug 24 08:43:06 PM UTC 24 1978829309 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.783315582 Aug 24 08:42:33 PM UTC 24 Aug 24 08:43:07 PM UTC 24 453125560 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.1591568961 Aug 24 08:43:05 PM UTC 24 Aug 24 08:43:07 PM UTC 24 16209304 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1792581320 Aug 24 08:43:05 PM UTC 24 Aug 24 08:43:07 PM UTC 24 96251096 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.1768088486 Aug 24 08:42:21 PM UTC 24 Aug 24 08:43:08 PM UTC 24 245670674 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.3437471387 Aug 24 08:42:48 PM UTC 24 Aug 24 08:43:08 PM UTC 24 862286382 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3196089996 Aug 24 08:42:25 PM UTC 24 Aug 24 08:43:08 PM UTC 24 868095493 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.1559160975 Aug 24 08:42:57 PM UTC 24 Aug 24 08:43:08 PM UTC 24 181838659 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.553656143 Aug 24 08:43:05 PM UTC 24 Aug 24 08:43:08 PM UTC 24 74488812 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.1810255672 Aug 24 08:42:00 PM UTC 24 Aug 24 08:43:09 PM UTC 24 7060974256 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2350241093 Aug 24 08:42:58 PM UTC 24 Aug 24 08:43:09 PM UTC 24 528730162 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.2053044083 Aug 24 08:43:06 PM UTC 24 Aug 24 08:43:09 PM UTC 24 75459419 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2611962619 Aug 24 08:42:22 PM UTC 24 Aug 24 08:43:10 PM UTC 24 4565459082 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.1523091175 Aug 24 08:42:58 PM UTC 24 Aug 24 08:43:11 PM UTC 24 466882661 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2697035011 Aug 24 08:43:00 PM UTC 24 Aug 24 08:43:11 PM UTC 24 225007060 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1691889375 Aug 24 08:42:54 PM UTC 24 Aug 24 08:43:11 PM UTC 24 373607387 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1781981819 Aug 24 08:42:56 PM UTC 24 Aug 24 08:43:12 PM UTC 24 1085809974 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.4243543366 Aug 24 08:41:50 PM UTC 24 Aug 24 08:43:11 PM UTC 24 14747172176 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.1138835773 Aug 24 08:42:58 PM UTC 24 Aug 24 08:43:11 PM UTC 24 2901677356 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.3175695699 Aug 24 08:43:09 PM UTC 24 Aug 24 08:43:34 PM UTC 24 2078583335 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3616731202 Aug 24 08:41:56 PM UTC 24 Aug 24 08:43:12 PM UTC 24 16477228208 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.920291448 Aug 24 08:43:09 PM UTC 24 Aug 24 08:43:12 PM UTC 24 34614943 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.507213161 Aug 24 08:42:47 PM UTC 24 Aug 24 08:43:12 PM UTC 24 1805172009 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3314667888 Aug 24 08:43:09 PM UTC 24 Aug 24 08:43:12 PM UTC 24 108729954 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.4223714788 Aug 24 08:42:48 PM UTC 24 Aug 24 08:43:12 PM UTC 24 357438286 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3031564536 Aug 24 08:42:53 PM UTC 24 Aug 24 08:43:13 PM UTC 24 429819444 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1098268875 Aug 24 08:43:01 PM UTC 24 Aug 24 08:43:13 PM UTC 24 72007240 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.1057387861 Aug 24 08:43:09 PM UTC 24 Aug 24 08:43:13 PM UTC 24 86845879 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.3400337639 Aug 24 08:43:10 PM UTC 24 Aug 24 08:43:14 PM UTC 24 189328544 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.752635520 Aug 24 08:43:10 PM UTC 24 Aug 24 08:43:15 PM UTC 24 593940037 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.3117041498 Aug 24 08:43:00 PM UTC 24 Aug 24 08:43:16 PM UTC 24 685599673 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1874805270 Aug 24 08:43:04 PM UTC 24 Aug 24 08:43:16 PM UTC 24 355776524 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3230033966 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:16 PM UTC 24 16649785 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.1143286303 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:16 PM UTC 24 16753023 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.2269724021 Aug 24 08:42:57 PM UTC 24 Aug 24 08:43:16 PM UTC 24 436365937 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.1236335740 Aug 24 08:43:06 PM UTC 24 Aug 24 08:43:17 PM UTC 24 107374837 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.1920249355 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:17 PM UTC 24 63824888 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1113558708 Aug 24 08:41:14 PM UTC 24 Aug 24 08:43:17 PM UTC 24 33822704443 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3038347481 Aug 24 08:42:54 PM UTC 24 Aug 24 08:43:18 PM UTC 24 1428571298 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.3695531107 Aug 24 08:43:32 PM UTC 24 Aug 24 08:43:36 PM UTC 24 31831747 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2854363368 Aug 24 08:43:02 PM UTC 24 Aug 24 08:43:18 PM UTC 24 3006817083 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3626146923 Aug 24 08:42:38 PM UTC 24 Aug 24 08:43:18 PM UTC 24 3987211922 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.995863371 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:19 PM UTC 24 228374428 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.768529752 Aug 24 08:42:31 PM UTC 24 Aug 24 08:43:36 PM UTC 24 5881164851 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.2168763065 Aug 24 08:43:04 PM UTC 24 Aug 24 08:43:19 PM UTC 24 567302728 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.527760378 Aug 24 08:43:04 PM UTC 24 Aug 24 08:43:19 PM UTC 24 1061136592 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1376633747 Aug 24 08:43:17 PM UTC 24 Aug 24 08:43:19 PM UTC 24 90771880 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1546099117 Aug 24 08:42:56 PM UTC 24 Aug 24 08:43:20 PM UTC 24 1373543191 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2700752943 Aug 24 08:41:30 PM UTC 24 Aug 24 08:43:20 PM UTC 24 2156412918 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.827004317 Aug 24 08:43:04 PM UTC 24 Aug 24 08:43:20 PM UTC 24 253023092 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1358796977 Aug 24 08:43:18 PM UTC 24 Aug 24 08:43:21 PM UTC 24 14069536 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.924581150 Aug 24 08:43:04 PM UTC 24 Aug 24 08:43:21 PM UTC 24 395763295 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.1723770365 Aug 24 08:43:17 PM UTC 24 Aug 24 08:43:21 PM UTC 24 237079062 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3356868303 Aug 24 08:43:07 PM UTC 24 Aug 24 08:43:21 PM UTC 24 365820933 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.3637761853 Aug 24 08:43:18 PM UTC 24 Aug 24 08:43:21 PM UTC 24 64684093 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.1859509538 Aug 24 08:42:51 PM UTC 24 Aug 24 08:43:22 PM UTC 24 1712987874 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3556732738 Aug 24 08:42:43 PM UTC 24 Aug 24 08:43:23 PM UTC 24 2993661110 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.3441623287 Aug 24 08:43:15 PM UTC 24 Aug 24 08:43:23 PM UTC 24 932693267 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2043433875 Aug 24 08:43:21 PM UTC 24 Aug 24 08:43:24 PM UTC 24 14909001 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.609659717 Aug 24 08:43:21 PM UTC 24 Aug 24 08:43:24 PM UTC 24 37079888 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2954247932 Aug 24 08:42:57 PM UTC 24 Aug 24 08:43:24 PM UTC 24 201924429 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3283201632 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:24 PM UTC 24 181237274 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.1913682340 Aug 24 08:43:11 PM UTC 24 Aug 24 08:43:24 PM UTC 24 213979244 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2085087912 Aug 24 08:43:07 PM UTC 24 Aug 24 08:43:25 PM UTC 24 1379992269 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.751867743 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:25 PM UTC 24 208759151 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3261172973 Aug 24 08:41:54 PM UTC 24 Aug 24 08:43:26 PM UTC 24 1891939983 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3974246302 Aug 24 08:43:21 PM UTC 24 Aug 24 08:43:26 PM UTC 24 169507576 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3285762084 Aug 24 08:43:23 PM UTC 24 Aug 24 08:43:26 PM UTC 24 36486984 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.2158448925 Aug 24 08:43:09 PM UTC 24 Aug 24 08:43:27 PM UTC 24 2006120570 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1123946220 Aug 24 08:43:18 PM UTC 24 Aug 24 08:43:36 PM UTC 24 148557220 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.2637461754 Aug 24 08:43:20 PM UTC 24 Aug 24 08:43:27 PM UTC 24 943443144 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.881873816 Aug 24 08:43:15 PM UTC 24 Aug 24 08:43:28 PM UTC 24 710505217 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.692451221 Aug 24 08:43:25 PM UTC 24 Aug 24 08:43:28 PM UTC 24 97380980 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.4084465233 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:28 PM UTC 24 1227558573 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.45795935 Aug 24 08:43:16 PM UTC 24 Aug 24 08:43:28 PM UTC 24 686748240 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.364636518 Aug 24 08:43:17 PM UTC 24 Aug 24 08:43:29 PM UTC 24 517464387 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3609038328 Aug 24 08:43:26 PM UTC 24 Aug 24 08:43:29 PM UTC 24 43647586 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.4052064587 Aug 24 08:42:27 PM UTC 24 Aug 24 08:43:29 PM UTC 24 6895847859 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.2796338200 Aug 24 08:42:26 PM UTC 24 Aug 24 08:43:29 PM UTC 24 1577364722 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.490796185 Aug 24 08:41:14 PM UTC 24 Aug 24 08:43:29 PM UTC 24 12488422355 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.377679754 Aug 24 08:43:24 PM UTC 24 Aug 24 08:43:29 PM UTC 24 1632805031 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.2095739712 Aug 24 08:43:20 PM UTC 24 Aug 24 08:43:30 PM UTC 24 273302161 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2515358497 Aug 24 08:43:33 PM UTC 24 Aug 24 08:43:36 PM UTC 24 16791172 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.4125470353 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:31 PM UTC 24 3659133798 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.2396215213 Aug 24 08:43:18 PM UTC 24 Aug 24 08:43:36 PM UTC 24 459931466 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.1298795620 Aug 24 08:43:11 PM UTC 24 Aug 24 08:43:31 PM UTC 24 374079609 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.2009560647 Aug 24 08:42:46 PM UTC 24 Aug 24 08:43:31 PM UTC 24 251564064 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2942571392 Aug 24 08:43:31 PM UTC 24 Aug 24 08:43:36 PM UTC 24 276009840 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.140911622 Aug 24 08:42:24 PM UTC 24 Aug 24 08:43:31 PM UTC 24 2824654442 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.3068730070 Aug 24 08:43:26 PM UTC 24 Aug 24 08:43:31 PM UTC 24 272407168 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2332007971 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:32 PM UTC 24 1278525254 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3725404976 Aug 24 08:43:27 PM UTC 24 Aug 24 08:43:32 PM UTC 24 58669079 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3446126993 Aug 24 08:41:33 PM UTC 24 Aug 24 08:43:32 PM UTC 24 5493764831 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1658884321 Aug 24 08:43:30 PM UTC 24 Aug 24 08:43:33 PM UTC 24 44527819 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2180929137 Aug 24 08:43:06 PM UTC 24 Aug 24 08:43:33 PM UTC 24 3326411457 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.4287798151 Aug 24 08:43:30 PM UTC 24 Aug 24 08:43:33 PM UTC 24 24556606 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.3379011013 Aug 24 08:43:30 PM UTC 24 Aug 24 08:43:35 PM UTC 24 109815411 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.1483787431 Aug 24 08:43:33 PM UTC 24 Aug 24 08:43:36 PM UTC 24 54444698 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.3282820708 Aug 24 08:43:20 PM UTC 24 Aug 24 08:43:36 PM UTC 24 997539017 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1412906485 Aug 24 08:43:01 PM UTC 24 Aug 24 08:43:37 PM UTC 24 523794349 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3299800865 Aug 24 08:43:29 PM UTC 24 Aug 24 08:43:37 PM UTC 24 262014813 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2705275312 Aug 24 08:43:20 PM UTC 24 Aug 24 08:43:37 PM UTC 24 264296732 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.714420952 Aug 24 08:43:15 PM UTC 24 Aug 24 08:43:37 PM UTC 24 808224257 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.1501391312 Aug 24 08:43:23 PM UTC 24 Aug 24 08:43:37 PM UTC 24 210256322 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.2849071353 Aug 24 08:42:11 PM UTC 24 Aug 24 08:43:38 PM UTC 24 1615065964 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1590609559 Aug 24 08:43:23 PM UTC 24 Aug 24 08:43:38 PM UTC 24 1124290154 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.4152799322 Aug 24 08:43:36 PM UTC 24 Aug 24 08:43:39 PM UTC 24 95827366 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2170810033 Aug 24 08:43:37 PM UTC 24 Aug 24 08:43:40 PM UTC 24 20485518 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.480281702 Aug 24 08:43:33 PM UTC 24 Aug 24 08:43:40 PM UTC 24 150283988 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.1623749083 Aug 24 08:43:32 PM UTC 24 Aug 24 08:43:41 PM UTC 24 255330945 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.1921082075 Aug 24 08:43:29 PM UTC 24 Aug 24 08:43:41 PM UTC 24 910394092 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1209641477 Aug 24 08:43:26 PM UTC 24 Aug 24 08:43:41 PM UTC 24 269336368 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.675664982 Aug 24 08:43:39 PM UTC 24 Aug 24 08:43:41 PM UTC 24 20011962 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3243627426 Aug 24 08:43:37 PM UTC 24 Aug 24 08:43:41 PM UTC 24 154304041 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3744915068 Aug 24 08:43:29 PM UTC 24 Aug 24 08:43:42 PM UTC 24 407660018 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2994155369 Aug 24 08:41:20 PM UTC 24 Aug 24 08:43:42 PM UTC 24 6448446101 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.3646315116 Aug 24 08:43:20 PM UTC 24 Aug 24 08:43:43 PM UTC 24 2324163424 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.3929386808 Aug 24 08:42:05 PM UTC 24 Aug 24 08:43:43 PM UTC 24 3950900978 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.127967908 Aug 24 08:43:24 PM UTC 24 Aug 24 08:43:43 PM UTC 24 389590431 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.3366156572 Aug 24 08:43:39 PM UTC 24 Aug 24 08:43:44 PM UTC 24 240388389 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.2471081434 Aug 24 08:43:24 PM UTC 24 Aug 24 08:43:44 PM UTC 24 7485496831 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.3923959802 Aug 24 08:43:10 PM UTC 24 Aug 24 08:43:44 PM UTC 24 437963533 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.836701051 Aug 24 08:43:32 PM UTC 24 Aug 24 08:43:44 PM UTC 24 486069685 ps
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