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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.00 97.92 95.84 93.40 97.62 98.52 99.25 96.47


Total test records in report: 999
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T605 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.4097552285 Aug 24 08:42:43 PM UTC 24 Aug 24 08:43:44 PM UTC 24 4934596624 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.483384383 Aug 24 08:43:42 PM UTC 24 Aug 24 08:43:44 PM UTC 24 19507448 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.726101968 Aug 24 08:43:32 PM UTC 24 Aug 24 08:43:44 PM UTC 24 683684860 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.2881531576 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:45 PM UTC 24 6111200109 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.1452212185 Aug 24 08:43:32 PM UTC 24 Aug 24 08:43:45 PM UTC 24 229176923 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.4091547691 Aug 24 08:43:07 PM UTC 24 Aug 24 08:43:45 PM UTC 24 1351505475 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1178761261 Aug 24 08:43:25 PM UTC 24 Aug 24 08:43:45 PM UTC 24 1978545158 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2891004677 Aug 24 08:43:53 PM UTC 24 Aug 24 08:43:57 PM UTC 24 35066779 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.1195849578 Aug 24 08:43:27 PM UTC 24 Aug 24 08:43:45 PM UTC 24 691107910 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3233571987 Aug 24 08:43:32 PM UTC 24 Aug 24 08:43:46 PM UTC 24 1448857775 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4050002144 Aug 24 08:43:43 PM UTC 24 Aug 24 08:43:46 PM UTC 24 13837159 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.1259988171 Aug 24 08:43:25 PM UTC 24 Aug 24 08:43:46 PM UTC 24 2837395550 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.3370797650 Aug 24 08:42:36 PM UTC 24 Aug 24 08:43:47 PM UTC 24 1696417496 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.618873826 Aug 24 08:43:27 PM UTC 24 Aug 24 08:43:47 PM UTC 24 750113132 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.2338871099 Aug 24 08:43:41 PM UTC 24 Aug 24 08:43:47 PM UTC 24 197506103 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3893025685 Aug 24 08:41:14 PM UTC 24 Aug 24 08:43:47 PM UTC 24 18594427804 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.4024734919 Aug 24 08:43:29 PM UTC 24 Aug 24 08:43:48 PM UTC 24 1613865670 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3846632574 Aug 24 08:43:43 PM UTC 24 Aug 24 08:43:48 PM UTC 24 36996636 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.3104662528 Aug 24 08:42:19 PM UTC 24 Aug 24 08:43:48 PM UTC 24 4034964057 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.3984257743 Aug 24 08:43:18 PM UTC 24 Aug 24 08:43:49 PM UTC 24 4260560518 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.1625817622 Aug 24 08:43:47 PM UTC 24 Aug 24 08:43:49 PM UTC 24 35570090 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.865919344 Aug 24 08:43:47 PM UTC 24 Aug 24 08:43:49 PM UTC 24 34436624 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.1743574327 Aug 24 08:43:36 PM UTC 24 Aug 24 08:43:50 PM UTC 24 280786765 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.1616943736 Aug 24 08:43:32 PM UTC 24 Aug 24 08:43:50 PM UTC 24 869569386 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2687917426 Aug 24 08:43:47 PM UTC 24 Aug 24 08:43:51 PM UTC 24 131953237 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1439547673 Aug 24 08:42:12 PM UTC 24 Aug 24 08:43:51 PM UTC 24 2387541500 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.692662713 Aug 24 08:43:26 PM UTC 24 Aug 24 08:43:51 PM UTC 24 601176663 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.737611101 Aug 24 08:43:45 PM UTC 24 Aug 24 08:43:51 PM UTC 24 371205592 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.79469329 Aug 24 08:43:51 PM UTC 24 Aug 24 08:43:57 PM UTC 24 69695266 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.1185248808 Aug 24 08:43:00 PM UTC 24 Aug 24 08:43:51 PM UTC 24 2063852816 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.822623987 Aug 24 08:43:45 PM UTC 24 Aug 24 08:43:52 PM UTC 24 74490410 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3483422819 Aug 24 08:43:39 PM UTC 24 Aug 24 08:43:52 PM UTC 24 134199817 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2017537398 Aug 24 08:43:50 PM UTC 24 Aug 24 08:43:52 PM UTC 24 14956901 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2487500189 Aug 24 08:43:50 PM UTC 24 Aug 24 08:43:52 PM UTC 24 22131870 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.3038979494 Aug 24 08:43:50 PM UTC 24 Aug 24 08:43:52 PM UTC 24 68853523 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.1320271988 Aug 24 08:42:16 PM UTC 24 Aug 24 08:43:53 PM UTC 24 10852573665 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2857865188 Aug 24 08:43:48 PM UTC 24 Aug 24 08:43:53 PM UTC 24 112929049 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3673115322 Aug 24 08:43:37 PM UTC 24 Aug 24 08:43:54 PM UTC 24 259921650 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.3754755724 Aug 24 08:43:47 PM UTC 24 Aug 24 08:43:54 PM UTC 24 100229485 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2646756749 Aug 24 08:43:05 PM UTC 24 Aug 24 08:43:54 PM UTC 24 1768957272 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.4108648459 Aug 24 08:42:47 PM UTC 24 Aug 24 08:43:54 PM UTC 24 5137603415 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2341946888 Aug 24 08:43:37 PM UTC 24 Aug 24 08:43:54 PM UTC 24 897786914 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.2576969674 Aug 24 08:43:13 PM UTC 24 Aug 24 08:43:55 PM UTC 24 1260797968 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.2647872425 Aug 24 08:43:37 PM UTC 24 Aug 24 08:43:55 PM UTC 24 399073845 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.227274660 Aug 24 08:43:42 PM UTC 24 Aug 24 08:43:55 PM UTC 24 277089913 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.3817424823 Aug 24 08:43:47 PM UTC 24 Aug 24 08:43:55 PM UTC 24 813953706 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3081551858 Aug 24 08:43:37 PM UTC 24 Aug 24 08:43:55 PM UTC 24 1614458528 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.3130629680 Aug 24 08:43:37 PM UTC 24 Aug 24 08:43:55 PM UTC 24 2155334261 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.222271534 Aug 24 08:43:53 PM UTC 24 Aug 24 08:43:56 PM UTC 24 35508170 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3648758916 Aug 24 08:44:02 PM UTC 24 Aug 24 08:44:25 PM UTC 24 573907823 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2507948490 Aug 24 08:43:45 PM UTC 24 Aug 24 08:43:56 PM UTC 24 965976543 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.3881175274 Aug 24 08:43:37 PM UTC 24 Aug 24 08:43:56 PM UTC 24 1699275467 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2153816494 Aug 24 08:43:53 PM UTC 24 Aug 24 08:43:56 PM UTC 24 34101752 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.865547494 Aug 24 08:43:42 PM UTC 24 Aug 24 08:43:56 PM UTC 24 988538569 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.178406687 Aug 24 08:43:45 PM UTC 24 Aug 24 08:43:56 PM UTC 24 1324625202 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.1954105944 Aug 24 08:43:45 PM UTC 24 Aug 24 08:43:57 PM UTC 24 354600313 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.272394084 Aug 24 08:43:52 PM UTC 24 Aug 24 08:43:57 PM UTC 24 1353487552 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.2497259363 Aug 24 08:43:48 PM UTC 24 Aug 24 08:43:58 PM UTC 24 3757785288 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3433671620 Aug 24 08:43:45 PM UTC 24 Aug 24 08:43:59 PM UTC 24 655345554 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3928612563 Aug 24 08:43:39 PM UTC 24 Aug 24 08:43:59 PM UTC 24 433570357 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1814922579 Aug 24 08:43:57 PM UTC 24 Aug 24 08:43:59 PM UTC 24 14650813 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.1987850951 Aug 24 08:42:56 PM UTC 24 Aug 24 08:43:59 PM UTC 24 1492370006 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.4031425503 Aug 24 08:43:45 PM UTC 24 Aug 24 08:44:00 PM UTC 24 1506226770 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.1968761691 Aug 24 08:43:55 PM UTC 24 Aug 24 08:44:00 PM UTC 24 205899106 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.193003902 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:00 PM UTC 24 27796327 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.1098554124 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:00 PM UTC 24 49914979 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.4246944551 Aug 24 08:43:40 PM UTC 24 Aug 24 08:44:00 PM UTC 24 384488322 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.149706137 Aug 24 08:43:48 PM UTC 24 Aug 24 08:44:01 PM UTC 24 1635629905 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.925177593 Aug 24 08:43:41 PM UTC 24 Aug 24 08:44:01 PM UTC 24 1119959854 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.469909692 Aug 24 08:42:48 PM UTC 24 Aug 24 08:44:01 PM UTC 24 1995388934 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.2144442337 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:01 PM UTC 24 35134118 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.2818511039 Aug 24 08:43:48 PM UTC 24 Aug 24 08:44:02 PM UTC 24 748450150 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1878269421 Aug 24 08:43:30 PM UTC 24 Aug 24 08:44:02 PM UTC 24 159696714 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2971116581 Aug 24 08:44:00 PM UTC 24 Aug 24 08:44:02 PM UTC 24 14276941 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2119658540 Aug 24 08:44:00 PM UTC 24 Aug 24 08:44:02 PM UTC 24 38104910 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.730687582 Aug 24 08:43:58 PM UTC 24 Aug 24 08:44:02 PM UTC 24 208697414 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.3750173765 Aug 24 08:44:00 PM UTC 24 Aug 24 08:44:03 PM UTC 24 165760105 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3673688604 Aug 24 08:43:47 PM UTC 24 Aug 24 08:44:03 PM UTC 24 262666243 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.4264484363 Aug 24 08:43:51 PM UTC 24 Aug 24 08:44:04 PM UTC 24 99629209 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.2327109425 Aug 24 08:43:45 PM UTC 24 Aug 24 08:44:04 PM UTC 24 1748742046 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.3559864872 Aug 24 08:43:23 PM UTC 24 Aug 24 08:44:04 PM UTC 24 1224806569 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1154779541 Aug 24 08:44:03 PM UTC 24 Aug 24 08:44:05 PM UTC 24 13993584 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3977819725 Aug 24 08:44:02 PM UTC 24 Aug 24 08:44:05 PM UTC 24 17160499 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.2556317322 Aug 24 08:44:01 PM UTC 24 Aug 24 08:44:06 PM UTC 24 262750356 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2492247240 Aug 24 08:43:48 PM UTC 24 Aug 24 08:44:07 PM UTC 24 390319542 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.1533444570 Aug 24 08:43:55 PM UTC 24 Aug 24 08:44:07 PM UTC 24 470282582 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.3409996775 Aug 24 08:43:52 PM UTC 24 Aug 24 08:44:07 PM UTC 24 2224102640 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.3266445366 Aug 24 08:43:52 PM UTC 24 Aug 24 08:44:08 PM UTC 24 1711054428 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.3431362942 Aug 24 08:43:53 PM UTC 24 Aug 24 08:44:08 PM UTC 24 502852496 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.1160713536 Aug 24 08:43:52 PM UTC 24 Aug 24 08:44:08 PM UTC 24 267328761 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1333924436 Aug 24 08:43:58 PM UTC 24 Aug 24 08:44:09 PM UTC 24 327597550 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.2034319322 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:09 PM UTC 24 670893192 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3510111855 Aug 24 08:43:58 PM UTC 24 Aug 24 08:44:24 PM UTC 24 5485726762 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3245972541 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:09 PM UTC 24 1483050440 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.3852928621 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:10 PM UTC 24 132305791 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.4228319230 Aug 24 08:44:04 PM UTC 24 Aug 24 08:44:10 PM UTC 24 161411388 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.142618431 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:11 PM UTC 24 426127686 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3856621843 Aug 24 08:44:01 PM UTC 24 Aug 24 08:44:11 PM UTC 24 515468808 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.3864046501 Aug 24 08:44:01 PM UTC 24 Aug 24 08:44:11 PM UTC 24 190459764 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3032079907 Aug 24 08:44:09 PM UTC 24 Aug 24 08:44:11 PM UTC 24 15524889 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.898910693 Aug 24 08:44:09 PM UTC 24 Aug 24 08:44:11 PM UTC 24 67906358 ps
T701 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.188306100 Aug 24 08:43:34 PM UTC 24 Aug 24 08:44:11 PM UTC 24 689746476 ps
T702 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3565411732 Aug 24 08:43:52 PM UTC 24 Aug 24 08:44:12 PM UTC 24 592094477 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3514001989 Aug 24 08:44:09 PM UTC 24 Aug 24 08:44:12 PM UTC 24 48254435 ps
T704 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.3608100046 Aug 24 08:44:05 PM UTC 24 Aug 24 08:44:24 PM UTC 24 581826153 ps
T705 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.204722468 Aug 24 08:44:02 PM UTC 24 Aug 24 08:44:14 PM UTC 24 155240185 ps
T706 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3450771098 Aug 24 08:43:52 PM UTC 24 Aug 24 08:44:14 PM UTC 24 349083593 ps
T707 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3464348309 Aug 24 08:44:04 PM UTC 24 Aug 24 08:44:14 PM UTC 24 267091241 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.1356715818 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:14 PM UTC 24 552228234 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2050214184 Aug 24 08:44:13 PM UTC 24 Aug 24 08:44:15 PM UTC 24 101723398 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2638211675 Aug 24 08:44:13 PM UTC 24 Aug 24 08:44:15 PM UTC 24 21815327 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.4025616913 Aug 24 08:44:10 PM UTC 24 Aug 24 08:44:15 PM UTC 24 196799469 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3671642418 Aug 24 08:44:01 PM UTC 24 Aug 24 08:44:16 PM UTC 24 443749063 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.3637960763 Aug 24 08:44:01 PM UTC 24 Aug 24 08:44:17 PM UTC 24 404155377 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2498711696 Aug 24 08:44:05 PM UTC 24 Aug 24 08:44:17 PM UTC 24 785893839 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.451766678 Aug 24 08:43:43 PM UTC 24 Aug 24 08:44:17 PM UTC 24 1806288793 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.85756422 Aug 24 08:44:02 PM UTC 24 Aug 24 08:44:17 PM UTC 24 335531579 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2480273813 Aug 24 08:42:20 PM UTC 24 Aug 24 08:44:18 PM UTC 24 2955935940 ps
T717 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.3204672716 Aug 24 08:43:55 PM UTC 24 Aug 24 08:44:18 PM UTC 24 4761775150 ps
T718 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.2285981482 Aug 24 08:44:13 PM UTC 24 Aug 24 08:44:18 PM UTC 24 62733103 ps
T719 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.4153535601 Aug 24 08:44:11 PM UTC 24 Aug 24 08:44:18 PM UTC 24 234964144 ps
T720 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.2468120281 Aug 24 08:44:06 PM UTC 24 Aug 24 08:44:20 PM UTC 24 2248085203 ps
T721 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.3124715289 Aug 24 08:44:15 PM UTC 24 Aug 24 08:44:20 PM UTC 24 82313149 ps
T722 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.1335056249 Aug 24 08:43:58 PM UTC 24 Aug 24 08:44:21 PM UTC 24 830661612 ps
T723 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3206746098 Aug 24 08:44:19 PM UTC 24 Aug 24 08:44:21 PM UTC 24 13927512 ps
T724 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.1409627427 Aug 24 08:43:58 PM UTC 24 Aug 24 08:44:21 PM UTC 24 903019992 ps
T725 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1236385693 Aug 24 08:44:19 PM UTC 24 Aug 24 08:44:21 PM UTC 24 20813843 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.296830149 Aug 24 08:44:01 PM UTC 24 Aug 24 08:44:21 PM UTC 24 2366796762 ps
T727 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.227609571 Aug 24 08:44:19 PM UTC 24 Aug 24 08:44:21 PM UTC 24 14309737 ps
T728 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.375453303 Aug 24 08:44:07 PM UTC 24 Aug 24 08:44:22 PM UTC 24 1504536034 ps
T729 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.4294356261 Aug 24 08:44:10 PM UTC 24 Aug 24 08:44:22 PM UTC 24 452763133 ps
T730 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1075235847 Aug 24 08:44:20 PM UTC 24 Aug 24 08:44:23 PM UTC 24 50778130 ps
T731 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2596197766 Aug 24 08:44:06 PM UTC 24 Aug 24 08:44:23 PM UTC 24 4534976289 ps
T732 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.281932655 Aug 24 08:43:32 PM UTC 24 Aug 24 08:44:24 PM UTC 24 8376680919 ps
T733 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2474551992 Aug 24 08:44:10 PM UTC 24 Aug 24 08:44:24 PM UTC 24 1599194461 ps
T734 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.4235279747 Aug 24 08:43:58 PM UTC 24 Aug 24 08:44:25 PM UTC 24 715511058 ps
T735 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2916636392 Aug 24 08:43:52 PM UTC 24 Aug 24 08:44:25 PM UTC 24 1066905642 ps
T736 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1554387596 Aug 24 08:44:23 PM UTC 24 Aug 24 08:44:25 PM UTC 24 35826732 ps
T737 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.3064472377 Aug 24 08:44:23 PM UTC 24 Aug 24 08:44:25 PM UTC 24 23097911 ps
T738 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.1573302424 Aug 24 08:44:11 PM UTC 24 Aug 24 08:44:25 PM UTC 24 955591694 ps
T739 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.2817507525 Aug 24 08:44:23 PM UTC 24 Aug 24 08:44:26 PM UTC 24 21956395 ps
T740 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.3395920088 Aug 24 08:43:04 PM UTC 24 Aug 24 08:44:26 PM UTC 24 2232483636 ps
T741 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.635774464 Aug 24 08:44:15 PM UTC 24 Aug 24 08:44:27 PM UTC 24 296394675 ps
T742 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.2380687746 Aug 24 08:44:15 PM UTC 24 Aug 24 08:44:27 PM UTC 24 833859593 ps
T743 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.4036325391 Aug 24 08:43:53 PM UTC 24 Aug 24 08:44:27 PM UTC 24 1121143266 ps
T744 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.292353914 Aug 24 08:44:05 PM UTC 24 Aug 24 08:44:29 PM UTC 24 10106011982 ps
T745 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1902097092 Aug 24 08:43:42 PM UTC 24 Aug 24 08:44:29 PM UTC 24 1471886059 ps
T746 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.811495016 Aug 24 08:44:27 PM UTC 24 Aug 24 08:44:29 PM UTC 24 21605399 ps
T747 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.272509474 Aug 24 08:44:27 PM UTC 24 Aug 24 08:44:29 PM UTC 24 26652005 ps
T748 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.4157755797 Aug 24 08:44:15 PM UTC 24 Aug 24 08:44:30 PM UTC 24 74875478 ps
T749 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.312907776 Aug 24 08:44:25 PM UTC 24 Aug 24 08:44:30 PM UTC 24 98946904 ps
T750 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.3386462297 Aug 24 08:44:11 PM UTC 24 Aug 24 08:44:30 PM UTC 24 358734591 ps
T751 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.987389885 Aug 24 08:43:39 PM UTC 24 Aug 24 08:44:30 PM UTC 24 1081084014 ps
T752 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1501744364 Aug 24 08:44:27 PM UTC 24 Aug 24 08:44:30 PM UTC 24 147960198 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.3832224461 Aug 24 08:44:20 PM UTC 24 Aug 24 08:44:30 PM UTC 24 214071390 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.815299821 Aug 24 08:43:50 PM UTC 24 Aug 24 08:44:31 PM UTC 24 284430887 ps
T755 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2292760351 Aug 24 08:44:29 PM UTC 24 Aug 24 08:44:50 PM UTC 24 2798148971 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.931785268 Aug 24 08:44:10 PM UTC 24 Aug 24 08:44:33 PM UTC 24 516256668 ps
T756 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.3438861070 Aug 24 08:44:29 PM UTC 24 Aug 24 08:44:33 PM UTC 24 31197970 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.3102621312 Aug 24 08:44:15 PM UTC 24 Aug 24 08:44:33 PM UTC 24 1597719995 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3793171663 Aug 24 08:42:24 PM UTC 24 Aug 24 08:44:33 PM UTC 24 52346091387 ps
T759 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.259186475 Aug 24 08:44:21 PM UTC 24 Aug 24 08:44:33 PM UTC 24 1402389473 ps
T760 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1816878996 Aug 24 08:44:31 PM UTC 24 Aug 24 08:44:34 PM UTC 24 22203009 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.4227576803 Aug 24 08:44:31 PM UTC 24 Aug 24 08:44:34 PM UTC 24 152454802 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.803136368 Aug 24 08:44:29 PM UTC 24 Aug 24 08:44:34 PM UTC 24 228750952 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3793944289 Aug 24 08:44:16 PM UTC 24 Aug 24 08:44:35 PM UTC 24 582938952 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.1281876730 Aug 24 08:44:16 PM UTC 24 Aug 24 08:44:35 PM UTC 24 431126776 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.1588257686 Aug 24 08:44:21 PM UTC 24 Aug 24 08:44:35 PM UTC 24 250466010 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.4196665411 Aug 24 08:44:27 PM UTC 24 Aug 24 08:44:36 PM UTC 24 293414123 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.1676893266 Aug 24 08:44:21 PM UTC 24 Aug 24 08:44:36 PM UTC 24 1445661585 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.811137551 Aug 24 08:44:30 PM UTC 24 Aug 24 08:44:36 PM UTC 24 246080392 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.1915612565 Aug 24 08:44:23 PM UTC 24 Aug 24 08:44:36 PM UTC 24 1551411369 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.369163427 Aug 24 08:44:25 PM UTC 24 Aug 24 08:44:37 PM UTC 24 443013076 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3937809419 Aug 24 08:44:01 PM UTC 24 Aug 24 08:44:37 PM UTC 24 4344854799 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.3925476993 Aug 24 08:44:31 PM UTC 24 Aug 24 08:44:38 PM UTC 24 752633182 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1323515389 Aug 24 08:44:34 PM UTC 24 Aug 24 08:44:38 PM UTC 24 95912516 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3705773140 Aug 24 08:43:47 PM UTC 24 Aug 24 08:44:38 PM UTC 24 3052050169 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1523562128 Aug 24 08:44:36 PM UTC 24 Aug 24 08:44:38 PM UTC 24 25882025 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1034071673 Aug 24 08:44:11 PM UTC 24 Aug 24 08:44:39 PM UTC 24 874937357 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.3625159093 Aug 24 08:44:25 PM UTC 24 Aug 24 08:44:39 PM UTC 24 1640346014 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1934849257 Aug 24 08:44:26 PM UTC 24 Aug 24 08:44:39 PM UTC 24 200494301 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3036570024 Aug 24 08:44:37 PM UTC 24 Aug 24 08:44:39 PM UTC 24 12367714 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.826822889 Aug 24 08:44:34 PM UTC 24 Aug 24 08:44:40 PM UTC 24 121459555 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2082122153 Aug 24 08:44:30 PM UTC 24 Aug 24 08:44:41 PM UTC 24 2384077251 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.668051180 Aug 24 08:44:20 PM UTC 24 Aug 24 08:44:41 PM UTC 24 1471128076 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1399308037 Aug 24 08:44:37 PM UTC 24 Aug 24 08:44:41 PM UTC 24 68778946 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2359124093 Aug 24 08:44:39 PM UTC 24 Aug 24 08:44:42 PM UTC 24 60079382 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1447234162 Aug 24 08:44:40 PM UTC 24 Aug 24 08:44:50 PM UTC 24 217110429 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.1822412011 Aug 24 08:44:25 PM UTC 24 Aug 24 08:44:42 PM UTC 24 1742198381 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1366189022 Aug 24 08:44:25 PM UTC 24 Aug 24 08:44:42 PM UTC 24 1797386944 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2364571424 Aug 24 08:42:07 PM UTC 24 Aug 24 08:44:43 PM UTC 24 9107712883 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.386542259 Aug 24 08:44:36 PM UTC 24 Aug 24 08:44:43 PM UTC 24 469284692 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.2897689451 Aug 24 08:44:30 PM UTC 24 Aug 24 08:44:43 PM UTC 24 271809176 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.4137289343 Aug 24 08:42:12 PM UTC 24 Aug 24 08:44:43 PM UTC 24 22247471950 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2924202836 Aug 24 08:44:31 PM UTC 24 Aug 24 08:44:44 PM UTC 24 309384395 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.73997047 Aug 24 08:44:38 PM UTC 24 Aug 24 08:44:44 PM UTC 24 406274526 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.413794108 Aug 24 08:44:42 PM UTC 24 Aug 24 08:44:44 PM UTC 24 18097265 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.618836335 Aug 24 08:44:30 PM UTC 24 Aug 24 08:44:46 PM UTC 24 1108899205 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.773030114 Aug 24 08:44:04 PM UTC 24 Aug 24 08:44:46 PM UTC 24 3766999297 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.2889002690 Aug 24 08:44:26 PM UTC 24 Aug 24 08:44:46 PM UTC 24 312634115 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.206017752 Aug 24 08:44:16 PM UTC 24 Aug 24 08:44:47 PM UTC 24 764404538 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2633367061 Aug 24 08:44:45 PM UTC 24 Aug 24 08:44:47 PM UTC 24 117093777 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.925092395 Aug 24 08:44:36 PM UTC 24 Aug 24 08:44:50 PM UTC 24 201888144 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.450103325 Aug 24 08:43:57 PM UTC 24 Aug 24 08:44:47 PM UTC 24 339852263 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2656052779 Aug 24 08:44:34 PM UTC 24 Aug 24 08:44:47 PM UTC 24 296623719 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.81957568 Aug 24 08:44:45 PM UTC 24 Aug 24 08:44:47 PM UTC 24 16898476 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1021457057 Aug 24 08:44:35 PM UTC 24 Aug 24 08:44:47 PM UTC 24 235984225 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3044495673 Aug 24 08:44:45 PM UTC 24 Aug 24 08:44:48 PM UTC 24 18034176 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2771596759 Aug 24 08:44:34 PM UTC 24 Aug 24 08:44:48 PM UTC 24 1183742980 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.119511950 Aug 24 08:44:37 PM UTC 24 Aug 24 08:44:48 PM UTC 24 151148242 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.4209682106 Aug 24 08:44:22 PM UTC 24 Aug 24 08:44:49 PM UTC 24 1645947860 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.1373942229 Aug 24 08:44:34 PM UTC 24 Aug 24 08:44:49 PM UTC 24 102596328 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.3875904794 Aug 24 08:44:26 PM UTC 24 Aug 24 08:44:49 PM UTC 24 1394526710 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1951175419 Aug 24 08:44:13 PM UTC 24 Aug 24 08:45:58 PM UTC 24 3250553499 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.272596488 Aug 24 08:44:14 PM UTC 24 Aug 24 08:44:51 PM UTC 24 1013664398 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.3704258976 Aug 24 08:44:34 PM UTC 24 Aug 24 08:44:51 PM UTC 24 579530397 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.1453232143 Aug 24 08:44:39 PM UTC 24 Aug 24 08:44:51 PM UTC 24 331597309 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.2191417246 Aug 24 08:44:46 PM UTC 24 Aug 24 08:44:51 PM UTC 24 323299592 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2588199412 Aug 24 08:44:49 PM UTC 24 Aug 24 08:44:51 PM UTC 24 27312435 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.59028881 Aug 24 08:44:49 PM UTC 24 Aug 24 08:44:51 PM UTC 24 66495745 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.1710393624 Aug 24 08:44:38 PM UTC 24 Aug 24 08:44:52 PM UTC 24 203927191 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.2728790359 Aug 24 08:44:43 PM UTC 24 Aug 24 08:44:52 PM UTC 24 148822725 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.210311250 Aug 24 08:44:49 PM UTC 24 Aug 24 08:44:52 PM UTC 24 193868666 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.1085408970 Aug 24 08:44:38 PM UTC 24 Aug 24 08:44:54 PM UTC 24 273634477 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.927600025 Aug 24 08:44:47 PM UTC 24 Aug 24 08:44:54 PM UTC 24 117467318 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2424786334 Aug 24 08:42:44 PM UTC 24 Aug 24 08:44:54 PM UTC 24 3502073993 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.3877378148 Aug 24 08:42:50 PM UTC 24 Aug 24 08:44:54 PM UTC 24 12963324526 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.907940359 Aug 24 08:44:49 PM UTC 24 Aug 24 08:44:54 PM UTC 24 739270311 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.323219239 Aug 24 08:44:39 PM UTC 24 Aug 24 08:44:55 PM UTC 24 4393030534 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.2359537141 Aug 24 08:44:50 PM UTC 24 Aug 24 08:44:55 PM UTC 24 48510147 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.2757120168 Aug 24 08:44:52 PM UTC 24 Aug 24 08:44:55 PM UTC 24 24760110 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1288913237 Aug 24 08:44:43 PM UTC 24 Aug 24 08:44:56 PM UTC 24 270089560 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2788470375 Aug 24 08:44:53 PM UTC 24 Aug 24 08:44:56 PM UTC 24 42679602 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.2270815487 Aug 24 08:44:10 PM UTC 24 Aug 24 08:44:57 PM UTC 24 268892934 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.579636953 Aug 24 08:44:36 PM UTC 24 Aug 24 08:45:52 PM UTC 24 43716288561 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.822313613 Aug 24 08:44:52 PM UTC 24 Aug 24 08:44:57 PM UTC 24 211402966 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.3248448324 Aug 24 08:44:43 PM UTC 24 Aug 24 08:44:57 PM UTC 24 835642647 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2950378921 Aug 24 08:44:43 PM UTC 24 Aug 24 08:44:57 PM UTC 24 39575754 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.1306872813 Aug 24 08:44:13 PM UTC 24 Aug 24 08:45:52 PM UTC 24 7145733549 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.4059189850 Aug 24 08:44:55 PM UTC 24 Aug 24 08:44:59 PM UTC 24 131443394 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.4164356918 Aug 24 08:43:48 PM UTC 24 Aug 24 08:44:59 PM UTC 24 8115878453 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.2809856765 Aug 24 08:44:43 PM UTC 24 Aug 24 08:44:59 PM UTC 24 1385634505 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.334672126 Aug 24 08:44:57 PM UTC 24 Aug 24 08:44:59 PM UTC 24 57439886 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3390786058 Aug 24 08:44:43 PM UTC 24 Aug 24 08:45:00 PM UTC 24 6960749542 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.921221776 Aug 24 08:44:50 PM UTC 24 Aug 24 08:45:00 PM UTC 24 231404267 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.3497631586 Aug 24 08:44:17 PM UTC 24 Aug 24 08:45:53 PM UTC 24 3186498445 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3715866259 Aug 24 08:44:47 PM UTC 24 Aug 24 08:45:01 PM UTC 24 272859331 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.353794055 Aug 24 08:44:19 PM UTC 24 Aug 24 08:45:01 PM UTC 24 340963872 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.3704036472 Aug 24 08:44:39 PM UTC 24 Aug 24 08:45:01 PM UTC 24 3046494281 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.415909451 Aug 24 08:44:49 PM UTC 24 Aug 24 08:45:01 PM UTC 24 963069093 ps
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