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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.00 97.92 95.84 93.40 97.62 98.52 99.25 96.47


Total test records in report: 999
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T835 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1350165668 Aug 24 08:44:49 PM UTC 24 Aug 24 08:45:01 PM UTC 24 409680694 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3587112997 Aug 24 08:43:37 PM UTC 24 Aug 24 08:45:02 PM UTC 24 23467318145 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.701202184 Aug 24 08:43:17 PM UTC 24 Aug 24 08:45:02 PM UTC 24 2918999359 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3130078599 Aug 24 08:43:42 PM UTC 24 Aug 24 08:45:03 PM UTC 24 3853815032 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.1252416453 Aug 24 08:44:24 PM UTC 24 Aug 24 08:45:04 PM UTC 24 252364508 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.272729944 Aug 24 08:44:43 PM UTC 24 Aug 24 08:45:04 PM UTC 24 406753371 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.3287712424 Aug 24 08:44:37 PM UTC 24 Aug 24 08:45:05 PM UTC 24 727202253 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2892614213 Aug 24 08:44:53 PM UTC 24 Aug 24 08:45:05 PM UTC 24 64652897 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2135410571 Aug 24 08:44:52 PM UTC 24 Aug 24 08:45:05 PM UTC 24 626044248 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.1928565253 Aug 24 08:44:55 PM UTC 24 Aug 24 08:45:06 PM UTC 24 296085889 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1238493816 Aug 24 08:44:55 PM UTC 24 Aug 24 08:45:06 PM UTC 24 719090334 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1363916093 Aug 24 08:44:52 PM UTC 24 Aug 24 08:45:07 PM UTC 24 5559811021 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.962772949 Aug 24 08:44:52 PM UTC 24 Aug 24 08:45:08 PM UTC 24 278382203 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3257799996 Aug 24 08:44:52 PM UTC 24 Aug 24 08:45:08 PM UTC 24 5069590106 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.641165869 Aug 24 08:42:50 PM UTC 24 Aug 24 08:45:08 PM UTC 24 16164157328 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.3717042552 Aug 24 08:44:55 PM UTC 24 Aug 24 08:45:08 PM UTC 24 278800687 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2407002161 Aug 24 08:44:56 PM UTC 24 Aug 24 08:45:09 PM UTC 24 1251322532 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2239974333 Aug 24 08:44:52 PM UTC 24 Aug 24 08:45:10 PM UTC 24 276202625 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2069790512 Aug 24 08:44:43 PM UTC 24 Aug 24 08:45:10 PM UTC 24 495375103 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.576726568 Aug 24 08:44:52 PM UTC 24 Aug 24 08:45:11 PM UTC 24 1565089820 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1414467337 Aug 24 08:43:32 PM UTC 24 Aug 24 08:45:11 PM UTC 24 8277146032 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.667240266 Aug 24 08:44:47 PM UTC 24 Aug 24 08:45:11 PM UTC 24 397966282 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2840376434 Aug 24 08:44:56 PM UTC 24 Aug 24 08:45:12 PM UTC 24 3983462807 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2049800152 Aug 24 08:44:55 PM UTC 24 Aug 24 08:45:13 PM UTC 24 477261400 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.394580324 Aug 24 08:44:49 PM UTC 24 Aug 24 08:45:14 PM UTC 24 1642295889 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.3799752709 Aug 24 08:44:32 PM UTC 24 Aug 24 08:45:14 PM UTC 24 188439052 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.3324900533 Aug 24 08:41:33 PM UTC 24 Aug 24 08:45:16 PM UTC 24 6517733404 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.3528116070 Aug 24 08:44:42 PM UTC 24 Aug 24 08:45:18 PM UTC 24 442347703 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3816175869 Aug 24 08:44:28 PM UTC 24 Aug 24 08:45:19 PM UTC 24 294010819 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2597978386 Aug 24 08:43:57 PM UTC 24 Aug 24 08:45:24 PM UTC 24 1908813199 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1532613441 Aug 24 08:44:45 PM UTC 24 Aug 24 08:45:24 PM UTC 24 921147092 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3877570654 Aug 24 08:44:50 PM UTC 24 Aug 24 08:45:27 PM UTC 24 1278239392 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.1237005093 Aug 24 08:43:48 PM UTC 24 Aug 24 08:45:27 PM UTC 24 4295666073 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.710576886 Aug 24 08:44:31 PM UTC 24 Aug 24 08:45:28 PM UTC 24 1348663986 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.2442783601 Aug 24 08:43:13 PM UTC 24 Aug 24 08:45:29 PM UTC 24 29413591760 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2039821259 Aug 24 08:43:30 PM UTC 24 Aug 24 08:45:29 PM UTC 24 14913509492 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3933046294 Aug 24 08:44:57 PM UTC 24 Aug 24 08:45:31 PM UTC 24 7816901951 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.1271660132 Aug 24 08:44:53 PM UTC 24 Aug 24 08:45:32 PM UTC 24 700318846 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.3073799998 Aug 24 08:42:38 PM UTC 24 Aug 24 08:45:34 PM UTC 24 54803879102 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3602212265 Aug 24 08:44:39 PM UTC 24 Aug 24 08:45:37 PM UTC 24 10248563799 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3139404187 Aug 24 08:44:45 PM UTC 24 Aug 24 08:45:48 PM UTC 24 15887053869 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2649948425 Aug 24 08:44:23 PM UTC 24 Aug 24 08:46:01 PM UTC 24 1979986570 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.844161978 Aug 24 08:43:00 PM UTC 24 Aug 24 08:46:04 PM UTC 24 4007772656 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.320903887 Aug 24 08:44:31 PM UTC 24 Aug 24 08:46:16 PM UTC 24 4426608045 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2384101333 Aug 24 08:44:23 PM UTC 24 Aug 24 08:46:16 PM UTC 24 2602578985 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.1510150770 Aug 24 08:43:09 PM UTC 24 Aug 24 08:46:16 PM UTC 24 91529232636 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3377105888 Aug 24 08:41:14 PM UTC 24 Aug 24 08:46:24 PM UTC 24 44104954994 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2584763729 Aug 24 08:44:39 PM UTC 24 Aug 24 08:46:26 PM UTC 24 6991862615 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.1696717682 Aug 24 08:43:47 PM UTC 24 Aug 24 08:46:29 PM UTC 24 8395077482 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.1853391789 Aug 24 08:43:25 PM UTC 24 Aug 24 08:46:30 PM UTC 24 7271213071 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2429938394 Aug 24 08:44:52 PM UTC 24 Aug 24 08:46:33 PM UTC 24 10686995254 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3079435498 Aug 24 08:44:45 PM UTC 24 Aug 24 08:46:58 PM UTC 24 18218328274 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3959284384 Aug 24 08:41:50 PM UTC 24 Aug 24 08:47:02 PM UTC 24 21155298669 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.4239769054 Aug 24 08:41:56 PM UTC 24 Aug 24 08:47:13 PM UTC 24 35599389628 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2042515131 Aug 24 08:42:01 PM UTC 24 Aug 24 08:47:19 PM UTC 24 9404634494 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1171606277 Aug 24 08:44:02 PM UTC 24 Aug 24 08:47:24 PM UTC 24 5209242601 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2519093301 Aug 24 08:44:56 PM UTC 24 Aug 24 08:47:26 PM UTC 24 26871796494 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.750541402 Aug 24 08:43:58 PM UTC 24 Aug 24 08:47:29 PM UTC 24 25544538999 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2984950771 Aug 24 08:44:09 PM UTC 24 Aug 24 08:47:41 PM UTC 24 41850337382 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3786820704 Aug 24 08:44:00 PM UTC 24 Aug 24 08:47:44 PM UTC 24 25674449142 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1018846392 Aug 24 08:41:47 PM UTC 24 Aug 24 08:47:53 PM UTC 24 46477723293 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.2011797314 Aug 24 08:43:20 PM UTC 24 Aug 24 08:48:39 PM UTC 24 46202287544 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.506906948 Aug 24 08:44:36 PM UTC 24 Aug 24 08:48:44 PM UTC 24 80564642653 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.1046189697 Aug 24 08:44:49 PM UTC 24 Aug 24 08:49:02 PM UTC 24 16203064867 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1257524574 Aug 24 08:44:58 PM UTC 24 Aug 24 08:45:01 PM UTC 24 16292044 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3298978674 Aug 24 08:45:00 PM UTC 24 Aug 24 08:45:02 PM UTC 24 49870381 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4015621906 Aug 24 08:45:01 PM UTC 24 Aug 24 08:45:03 PM UTC 24 35603168 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2078558895 Aug 24 08:44:58 PM UTC 24 Aug 24 08:45:03 PM UTC 24 1011941775 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2522294580 Aug 24 08:45:01 PM UTC 24 Aug 24 08:45:03 PM UTC 24 15976863 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.858314431 Aug 24 08:44:59 PM UTC 24 Aug 24 08:45:03 PM UTC 24 110839455 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3790396751 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:17 PM UTC 24 15272280 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3574026096 Aug 24 08:44:58 PM UTC 24 Aug 24 08:45:04 PM UTC 24 1861281321 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.200153499 Aug 24 08:45:01 PM UTC 24 Aug 24 08:45:05 PM UTC 24 261798225 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1838320061 Aug 24 08:45:02 PM UTC 24 Aug 24 08:45:05 PM UTC 24 76078638 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4103599705 Aug 24 08:45:02 PM UTC 24 Aug 24 08:45:05 PM UTC 24 30393962 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.509841089 Aug 24 08:45:01 PM UTC 24 Aug 24 08:45:05 PM UTC 24 318444361 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.11515358 Aug 24 08:45:03 PM UTC 24 Aug 24 08:45:06 PM UTC 24 41020592 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4263424058 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:15 PM UTC 24 1263516618 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1275695362 Aug 24 08:45:02 PM UTC 24 Aug 24 08:45:06 PM UTC 24 408559313 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3156801928 Aug 24 08:45:02 PM UTC 24 Aug 24 08:45:06 PM UTC 24 63488695 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3153229152 Aug 24 08:45:02 PM UTC 24 Aug 24 08:45:06 PM UTC 24 46303149 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4294416271 Aug 24 08:45:04 PM UTC 24 Aug 24 08:45:06 PM UTC 24 33232038 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3850342828 Aug 24 08:45:04 PM UTC 24 Aug 24 08:45:06 PM UTC 24 28580222 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.866817880 Aug 24 08:45:04 PM UTC 24 Aug 24 08:45:07 PM UTC 24 91172391 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3695529716 Aug 24 08:45:01 PM UTC 24 Aug 24 08:45:07 PM UTC 24 104069085 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.147162048 Aug 24 08:45:04 PM UTC 24 Aug 24 08:45:07 PM UTC 24 386479934 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2183583914 Aug 24 08:45:04 PM UTC 24 Aug 24 08:45:08 PM UTC 24 94008318 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3986510217 Aug 24 08:45:04 PM UTC 24 Aug 24 08:45:08 PM UTC 24 373714829 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.492336885 Aug 24 08:45:05 PM UTC 24 Aug 24 08:45:08 PM UTC 24 45913107 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2807796713 Aug 24 08:45:05 PM UTC 24 Aug 24 08:45:08 PM UTC 24 21247988 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3527475483 Aug 24 08:45:05 PM UTC 24 Aug 24 08:45:08 PM UTC 24 16111290 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3431819843 Aug 24 08:45:05 PM UTC 24 Aug 24 08:45:09 PM UTC 24 51821007 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1158027298 Aug 24 08:45:06 PM UTC 24 Aug 24 08:45:09 PM UTC 24 55360418 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1498641408 Aug 24 08:45:06 PM UTC 24 Aug 24 08:45:09 PM UTC 24 44303350 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4172301230 Aug 24 08:45:05 PM UTC 24 Aug 24 08:45:09 PM UTC 24 123913560 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.181357969 Aug 24 08:44:58 PM UTC 24 Aug 24 08:45:09 PM UTC 24 3406329188 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1940047331 Aug 24 08:45:06 PM UTC 24 Aug 24 08:45:09 PM UTC 24 28021338 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3224294643 Aug 24 08:44:58 PM UTC 24 Aug 24 08:45:10 PM UTC 24 619203197 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3336840083 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:10 PM UTC 24 12203112 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2842227223 Aug 24 08:45:06 PM UTC 24 Aug 24 08:45:10 PM UTC 24 380235613 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.935274793 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:10 PM UTC 24 23307536 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4212358500 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:11 PM UTC 24 172713069 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3647264881 Aug 24 08:45:04 PM UTC 24 Aug 24 08:45:11 PM UTC 24 127130194 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3147282893 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:11 PM UTC 24 55352649 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3992865075 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:11 PM UTC 24 32109676 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.249831342 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:11 PM UTC 24 72889476 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2052861026 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:12 PM UTC 24 124106345 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2062697943 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:12 PM UTC 24 16605657 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3926454474 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:12 PM UTC 24 12795723 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3943459944 Aug 24 08:45:06 PM UTC 24 Aug 24 08:45:12 PM UTC 24 286914381 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.404744871 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:12 PM UTC 24 23179697 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3259620823 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:12 PM UTC 24 25660967 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.11317512 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:12 PM UTC 24 20485608 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3798707334 Aug 24 08:45:10 PM UTC 24 Aug 24 08:45:13 PM UTC 24 24945235 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3899344765 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:13 PM UTC 24 123751330 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.451864122 Aug 24 08:45:10 PM UTC 24 Aug 24 08:45:13 PM UTC 24 849537614 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.992023346 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:13 PM UTC 24 31593185 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2080363130 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:14 PM UTC 24 45004492 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1687986836 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:14 PM UTC 24 56057964 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2998787180 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:14 PM UTC 24 58454562 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2510678013 Aug 24 08:45:06 PM UTC 24 Aug 24 08:45:14 PM UTC 24 1041938516 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.351768766 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:15 PM UTC 24 119397101 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1408098908 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:15 PM UTC 24 23265948 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2999833494 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:15 PM UTC 24 201812140 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2378571513 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:15 PM UTC 24 17225566 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3643631060 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:15 PM UTC 24 22312121 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.658900444 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:15 PM UTC 24 343342564 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2222205777 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:15 PM UTC 24 55491577 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3331664018 Aug 24 08:45:09 PM UTC 24 Aug 24 08:45:15 PM UTC 24 696478204 ps
T901 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3995577139 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:15 PM UTC 24 164985025 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1817912360 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:15 PM UTC 24 32934906 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1989065210 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:15 PM UTC 24 229899619 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3875920731 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:16 PM UTC 24 79922139 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.541744924 Aug 24 08:45:13 PM UTC 24 Aug 24 08:45:16 PM UTC 24 14148667 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.416122005 Aug 24 08:45:06 PM UTC 24 Aug 24 08:45:16 PM UTC 24 445557233 ps
T906 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3235677289 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:16 PM UTC 24 281547924 ps
T907 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2702457085 Aug 24 08:45:14 PM UTC 24 Aug 24 08:45:16 PM UTC 24 13208478 ps
T908 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2460037697 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:16 PM UTC 24 82035859 ps
T909 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3280337180 Aug 24 08:45:14 PM UTC 24 Aug 24 08:45:17 PM UTC 24 21345489 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3408411080 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:19 PM UTC 24 15124604 ps
T910 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2621953264 Aug 24 08:45:13 PM UTC 24 Aug 24 08:45:17 PM UTC 24 463971709 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.12936716 Aug 24 08:45:13 PM UTC 24 Aug 24 08:45:18 PM UTC 24 44665510 ps
T911 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1499062607 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:18 PM UTC 24 1972474540 ps
T912 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.708513273 Aug 24 08:45:14 PM UTC 24 Aug 24 08:45:18 PM UTC 24 66898655 ps
T913 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.806163036 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:18 PM UTC 24 51490326 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2484416861 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:26 PM UTC 24 46374084 ps
T914 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4038236563 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:18 PM UTC 24 65063302 ps
T915 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3838559770 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:18 PM UTC 24 50101612 ps
T916 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4156674840 Aug 24 08:45:02 PM UTC 24 Aug 24 08:45:19 PM UTC 24 514638204 ps
T917 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4062044788 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:19 PM UTC 24 236209438 ps
T918 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3076856972 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:19 PM UTC 24 188141504 ps
T919 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3205840933 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:19 PM UTC 24 44417339 ps
T920 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3517258182 Aug 24 08:45:14 PM UTC 24 Aug 24 08:45:19 PM UTC 24 130693871 ps
T921 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4285336968 Aug 24 08:45:13 PM UTC 24 Aug 24 08:45:19 PM UTC 24 219188857 ps
T922 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2475778775 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:19 PM UTC 24 55416869 ps
T923 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1156729005 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:19 PM UTC 24 25107529 ps
T924 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.722711446 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:19 PM UTC 24 861278368 ps
T925 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3617327248 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:20 PM UTC 24 370405302 ps
T926 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2536173445 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:20 PM UTC 24 149102162 ps
T927 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2322140133 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:20 PM UTC 24 244174852 ps
T928 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2278318587 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:20 PM UTC 24 86693027 ps
T929 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.682770302 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:20 PM UTC 24 50832426 ps
T930 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.894604133 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:20 PM UTC 24 690460999 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.463637180 Aug 24 08:45:22 PM UTC 24 Aug 24 08:45:26 PM UTC 24 45556747 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4052889245 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:20 PM UTC 24 610428349 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2159634325 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:20 PM UTC 24 268318178 ps
T931 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2281080321 Aug 24 08:45:18 PM UTC 24 Aug 24 08:45:21 PM UTC 24 446070359 ps
T932 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4062843992 Aug 24 08:45:18 PM UTC 24 Aug 24 08:45:21 PM UTC 24 247400454 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2325195221 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:21 PM UTC 24 11919402 ps
T933 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3926523554 Aug 24 08:45:18 PM UTC 24 Aug 24 08:45:21 PM UTC 24 97695116 ps
T934 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2285056161 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:21 PM UTC 24 197844247 ps
T935 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4018365362 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:21 PM UTC 24 462394864 ps
T936 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1494643146 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:22 PM UTC 24 83301605 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.153378289 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:22 PM UTC 24 138953558 ps
T937 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1942047336 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:22 PM UTC 24 36156992 ps
T938 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1206553093 Aug 24 08:45:06 PM UTC 24 Aug 24 08:45:22 PM UTC 24 1933905983 ps
T939 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1386282082 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:22 PM UTC 24 36030504 ps
T940 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2587575287 Aug 24 08:45:08 PM UTC 24 Aug 24 08:45:22 PM UTC 24 518079443 ps
T941 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1812296649 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:22 PM UTC 24 18938952 ps
T942 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2387972558 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:23 PM UTC 24 42802768 ps
T943 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1804292106 Aug 24 08:45:13 PM UTC 24 Aug 24 08:45:23 PM UTC 24 135396471 ps
T944 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.536868830 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:23 PM UTC 24 34835855 ps
T945 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1136626930 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:23 PM UTC 24 134131141 ps
T946 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3413560682 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:23 PM UTC 24 48986494 ps
T947 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.20363210 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:23 PM UTC 24 132416187 ps
T948 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1523130544 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:23 PM UTC 24 18697683 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2246131063 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:23 PM UTC 24 461645861 ps
T949 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3143846735 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:23 PM UTC 24 333076392 ps
T950 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1240818014 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:23 PM UTC 24 105612544 ps
T951 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1189494755 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:23 PM UTC 24 111063500 ps
T952 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2877865450 Aug 24 08:45:15 PM UTC 24 Aug 24 08:45:24 PM UTC 24 3705521172 ps
T953 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.821419580 Aug 24 08:45:21 PM UTC 24 Aug 24 08:45:24 PM UTC 24 58810141 ps
T954 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1297033807 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:24 PM UTC 24 28359515 ps
T955 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2622973057 Aug 24 08:45:21 PM UTC 24 Aug 24 08:45:24 PM UTC 24 16734545 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1969009821 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:24 PM UTC 24 75653550 ps
T956 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3873806614 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:24 PM UTC 24 53303181 ps
T957 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3910557085 Aug 24 08:45:21 PM UTC 24 Aug 24 08:45:24 PM UTC 24 47484327 ps
T958 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.945277027 Aug 24 08:45:21 PM UTC 24 Aug 24 08:45:24 PM UTC 24 43061978 ps
T959 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4919808 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:24 PM UTC 24 144790003 ps
T960 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.335251186 Aug 24 08:45:21 PM UTC 24 Aug 24 08:45:25 PM UTC 24 172926899 ps
T961 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4090140599 Aug 24 08:45:22 PM UTC 24 Aug 24 08:45:25 PM UTC 24 17204542 ps
T962 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2425769882 Aug 24 08:45:22 PM UTC 24 Aug 24 08:45:25 PM UTC 24 22851976 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4237371888 Aug 24 08:45:21 PM UTC 24 Aug 24 08:45:25 PM UTC 24 52697911 ps
T963 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.998453512 Aug 24 08:45:22 PM UTC 24 Aug 24 08:45:25 PM UTC 24 88969425 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.747352965 Aug 24 08:45:21 PM UTC 24 Aug 24 08:45:25 PM UTC 24 61506141 ps
T964 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1320248985 Aug 24 08:45:22 PM UTC 24 Aug 24 08:45:25 PM UTC 24 28766459 ps
T965 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.95000188 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:30 PM UTC 24 15074436 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4164860473 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:26 PM UTC 24 311656536 ps
T966 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3301259326 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:26 PM UTC 24 1166713007 ps
T967 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1030675212 Aug 24 08:45:21 PM UTC 24 Aug 24 08:45:26 PM UTC 24 677566123 ps
T968 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3248570649 Aug 24 08:45:22 PM UTC 24 Aug 24 08:45:26 PM UTC 24 100088153 ps
T969 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1768878491 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:26 PM UTC 24 24075841 ps
T970 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.746451810 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:26 PM UTC 24 61760155 ps
T971 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1716950813 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:26 PM UTC 24 12209949 ps
T972 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2876220867 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:26 PM UTC 24 17878598 ps
T973 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1037881468 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:27 PM UTC 24 88541321 ps
T974 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1184709832 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:26 PM UTC 24 31472251 ps
T975 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3654598673 Aug 24 08:45:20 PM UTC 24 Aug 24 08:45:26 PM UTC 24 189433661 ps
T976 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1746545784 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:27 PM UTC 24 138433364 ps
T977 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.545376173 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:27 PM UTC 24 143208976 ps
T978 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2402024427 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:27 PM UTC 24 45696373 ps
T979 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4248196926 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:27 PM UTC 24 1958927723 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3363941748 Aug 24 08:45:22 PM UTC 24 Aug 24 08:45:27 PM UTC 24 114567799 ps
T980 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.554084551 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:28 PM UTC 24 144621884 ps
T981 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3167112795 Aug 24 08:45:11 PM UTC 24 Aug 24 08:45:28 PM UTC 24 4342125357 ps
T982 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1212556371 Aug 24 08:45:19 PM UTC 24 Aug 24 08:45:28 PM UTC 24 485134133 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.759988912 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:29 PM UTC 24 320440748 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2106585809 Aug 24 08:45:24 PM UTC 24 Aug 24 08:45:29 PM UTC 24 376928715 ps
T983 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3167017827 Aug 24 08:45:02 PM UTC 24 Aug 24 08:45:29 PM UTC 24 7925895139 ps
T984 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3398283514 Aug 24 08:45:16 PM UTC 24 Aug 24 08:45:29 PM UTC 24 2606698841 ps
T985 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3474533083 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:30 PM UTC 24 129311888 ps
T986 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3146191830 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:31 PM UTC 24 16429843 ps
T987 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2230788776 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:31 PM UTC 24 15475237 ps
T988 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3502677891 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:31 PM UTC 24 76517345 ps
T989 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.865051702 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:31 PM UTC 24 18407909 ps
T990 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1539765364 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:31 PM UTC 24 21768355 ps
T991 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2782037493 Aug 24 08:45:18 PM UTC 24 Aug 24 08:45:31 PM UTC 24 700881246 ps
T992 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.883086864 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:31 PM UTC 24 21420186 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4201475209 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:31 PM UTC 24 56678251 ps
T993 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.908574797 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:31 PM UTC 24 58789152 ps
T994 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3651203371 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:32 PM UTC 24 230225460 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2497540772 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:32 PM UTC 24 385372078 ps
T995 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3442200390 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:32 PM UTC 24 315230119 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3014267770 Aug 24 08:45:25 PM UTC 24 Aug 24 08:45:32 PM UTC 24 108210686 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3055092558 Aug 24 08:45:26 PM UTC 24 Aug 24 08:45:35 PM UTC 24 19012371 ps
T996 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2377348878 Aug 24 08:45:26 PM UTC 24 Aug 24 08:45:35 PM UTC 24 138872800 ps
T997 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.865464859 Aug 24 08:45:26 PM UTC 24 Aug 24 08:45:36 PM UTC 24 28428017 ps
T998 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.70700843 Aug 24 08:45:12 PM UTC 24 Aug 24 08:45:43 PM UTC 24 1244041364 ps
T999 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3345801353 Aug 24 08:45:18 PM UTC 24 Aug 24 08:45:43 PM UTC 24 2084555096 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4235671488
Short name T16
Test name
Test status
Simulation time 26129740 ps
CPU time 1.38 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:18 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235671488 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_volatile_unlock_smoke.4235671488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3843295830
Short name T7
Test name
Test status
Simulation time 641966618 ps
CPU time 6.11 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:23 PM UTC 24
Peak memory 229680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843295830
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_smoke.3843295830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2420166048
Short name T20
Test name
Test status
Simulation time 228021558 ps
CPU time 3.16 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:19 PM UTC 24
Peak memory 229880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420166048 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2420166048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2305264605
Short name T40
Test name
Test status
Simulation time 771268965 ps
CPU time 11.56 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:27 PM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305264605 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2305264605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.374374357
Short name T58
Test name
Test status
Simulation time 786741238 ps
CPU time 10.88 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:27 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374374357 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.374374357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1767954016
Short name T25
Test name
Test status
Simulation time 3125736570 ps
CPU time 6.4 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:23 PM UTC 24
Peak memory 230520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767954016 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_toke
n_mux.1767954016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3835307199
Short name T29
Test name
Test status
Simulation time 102596975 ps
CPU time 4.33 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:21 PM UTC 24
Peak memory 234508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835307199 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3835307199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.605713378
Short name T110
Test name
Test status
Simulation time 11073345627 ps
CPU time 85.42 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:42:43 PM UTC 24
Peak memory 265044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605713378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.605713378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.66489138
Short name T190
Test name
Test status
Simulation time 455218607 ps
CPU time 18.66 seconds
Started Aug 24 08:41:54 PM UTC 24
Finished Aug 24 08:42:14 PM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66489138 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.66489138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2532005212
Short name T33
Test name
Test status
Simulation time 496682764 ps
CPU time 11.95 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:28 PM UTC 24
Peak memory 229052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532005212 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2532005212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.4162720495
Short name T9
Test name
Test status
Simulation time 295501515 ps
CPU time 6.62 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:23 PM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162720495 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.4162720495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.509841089
Short name T142
Test name
Test status
Simulation time 318444361 ps
CPU time 3.59 seconds
Started Aug 24 08:45:01 PM UTC 24
Finished Aug 24 08:45:05 PM UTC 24
Peak memory 235712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509841089 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl
_intg_err.509841089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4293389633
Short name T4
Test name
Test status
Simulation time 51858898 ps
CPU time 2.02 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:18 PM UTC 24
Peak memory 230956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293389633
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_jtag_prog_failure.4293389633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.102752663
Short name T112
Test name
Test status
Simulation time 322812714 ps
CPU time 30.72 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:47 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102752663 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.102752663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3062244770
Short name T78
Test name
Test status
Simulation time 428508318 ps
CPU time 38.22 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:55 PM UTC 24
Peak memory 289840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062244770 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3062244770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3095236484
Short name T195
Test name
Test status
Simulation time 241367782 ps
CPU time 9.36 seconds
Started Aug 24 08:42:04 PM UTC 24
Finished Aug 24 08:42:14 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095236484 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3095236484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3377105888
Short name T215
Test name
Test status
Simulation time 44104954994 ps
CPU time 303.92 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:46:24 PM UTC 24
Peak memory 287564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3377105888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 1.lc_ctrl_stress_all.3377105888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4263424058
Short name T143
Test name
Test status
Simulation time 1263516618 ps
CPU time 3.08 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 235456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263424058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4263424058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.931785268
Short name T213
Test name
Test status
Simulation time 516256668 ps
CPU time 21.18 seconds
Started Aug 24 08:44:10 PM UTC 24
Finished Aug 24 08:44:33 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931785268 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.931785268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.859636960
Short name T80
Test name
Test status
Simulation time 24804402 ps
CPU time 1.64 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:18 PM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859636960 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.859636960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1653392182
Short name T418
Test name
Test status
Simulation time 5225550723 ps
CPU time 79.14 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:42:36 PM UTC 24
Peak memory 283480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653392182
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_c
trl_jtag_state_failure.1653392182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3790396751
Short name T152
Test name
Test status
Simulation time 15272280 ps
CPU time 1.26 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:17 PM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790396751 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3790396751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.4050046385
Short name T113
Test name
Test status
Simulation time 479267507 ps
CPU time 40.6 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:57 PM UTC 24
Peak memory 262524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050046385 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.4050046385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.297837383
Short name T104
Test name
Test status
Simulation time 929682804 ps
CPU time 13.65 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:30 PM UTC 24
Peak memory 234800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297837383
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc
_ctrl_jtag_state_post_trans.297837383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.1532325414
Short name T64
Test name
Test status
Simulation time 589905541 ps
CPU time 12.84 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:29 PM UTC 24
Peak memory 231416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532325414 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1532325414
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2999833494
Short name T155
Test name
Test status
Simulation time 201812140 ps
CPU time 4.19 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 229500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999833494 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2999833494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.12936716
Short name T163
Test name
Test status
Simulation time 44665510 ps
CPU time 2.77 seconds
Started Aug 24 08:45:13 PM UTC 24
Finished Aug 24 08:45:18 PM UTC 24
Peak memory 233408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12936716 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_
intg_err.12936716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.329237397
Short name T327
Test name
Test status
Simulation time 1750816628 ps
CPU time 33.72 seconds
Started Aug 24 08:41:25 PM UTC 24
Finished Aug 24 08:42:00 PM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329237397 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.329237397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.641165869
Short name T118
Test name
Test status
Simulation time 16164157328 ps
CPU time 135.15 seconds
Started Aug 24 08:42:50 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 295772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641165869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.641165869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3363941748
Short name T156
Test name
Test status
Simulation time 114567799 ps
CPU time 3.73 seconds
Started Aug 24 08:45:22 PM UTC 24
Finished Aug 24 08:45:27 PM UTC 24
Peak memory 235632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363941748 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
tl_intg_err.3363941748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.211084564
Short name T24
Test name
Test status
Simulation time 31155030 ps
CPU time 2.94 seconds
Started Aug 24 08:41:18 PM UTC 24
Finished Aug 24 08:41:22 PM UTC 24
Peak memory 234504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211084564 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.211084564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.490796185
Short name T562
Test name
Test status
Simulation time 12488422355 ps
CPU time 131.19 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:43:29 PM UTC 24
Peak memory 262996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=490796185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.lc_ctrl_stress_all.490796185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3574026096
Short name T179
Test name
Test status
Simulation time 1861281321 ps
CPU time 4.77 seconds
Started Aug 24 08:44:58 PM UTC 24
Finished Aug 24 08:45:04 PM UTC 24
Peak memory 219168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3574026096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_csr_rw.3574026096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.747352965
Short name T158
Test name
Test status
Simulation time 61506141 ps
CPU time 2.93 seconds
Started Aug 24 08:45:21 PM UTC 24
Finished Aug 24 08:45:25 PM UTC 24
Peak memory 233736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747352965 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_t
l_intg_err.747352965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2246131063
Short name T165
Test name
Test status
Simulation time 461645861 ps
CPU time 2.98 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 233588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246131063 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_t
l_intg_err.2246131063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3612809075
Short name T13
Test name
Test status
Simulation time 45305104 ps
CPU time 1.13 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:17 PM UTC 24
Peak memory 217796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612809075 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3612809075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.200153499
Short name T201
Test name
Test status
Simulation time 261798225 ps
CPU time 2.7 seconds
Started Aug 24 08:45:01 PM UTC 24
Finished Aug 24 08:45:05 PM UTC 24
Peak memory 219248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200153499 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_b
it_bash.200153499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3786820704
Short name T128
Test name
Test status
Simulation time 25674449142 ps
CPU time 221.55 seconds
Started Aug 24 08:44:00 PM UTC 24
Finished Aug 24 08:47:44 PM UTC 24
Peak memory 404240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786820704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3786820704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.579335778
Short name T3
Test name
Test status
Simulation time 14334159 ps
CPU time 1.19 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:17 PM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579335778 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.579335778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.4021791940
Short name T10
Test name
Test status
Simulation time 1716742509 ps
CPU time 8.47 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:25 PM UTC 24
Peak memory 228796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021791940 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.4021791940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3944083940
Short name T41
Test name
Test status
Simulation time 135394111 ps
CPU time 7.29 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:24 PM UTC 24
Peak memory 261164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944083940 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3944083940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2145497412
Short name T84
Test name
Test status
Simulation time 1232913016 ps
CPU time 10.64 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:27 PM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145497412 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2145497412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2106585809
Short name T167
Test name
Test status
Simulation time 376928715 ps
CPU time 4.08 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:29 PM UTC 24
Peak memory 229640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106585809 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
tl_intg_err.2106585809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2497540772
Short name T174
Test name
Test status
Simulation time 385372078 ps
CPU time 2.54 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:32 PM UTC 24
Peak memory 229476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497540772 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
tl_intg_err.2497540772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3598902793
Short name T19
Test name
Test status
Simulation time 10917616 ps
CPU time 1.05 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:18 PM UTC 24
Peak memory 217056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598902793 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3598902793
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3847331538
Short name T256
Test name
Test status
Simulation time 12972998 ps
CPU time 1.45 seconds
Started Aug 24 08:41:27 PM UTC 24
Finished Aug 24 08:41:30 PM UTC 24
Peak memory 217304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847331538 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3847331538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.350039121
Short name T257
Test name
Test status
Simulation time 23085605 ps
CPU time 1.3 seconds
Started Aug 24 08:41:36 PM UTC 24
Finished Aug 24 08:41:38 PM UTC 24
Peak memory 218480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350039121 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.350039121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.80861067
Short name T427
Test name
Test status
Simulation time 1130432588 ps
CPU time 45.41 seconds
Started Aug 24 08:41:51 PM UTC 24
Finished Aug 24 08:42:38 PM UTC 24
Peak memory 260772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80861067 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.80861067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.759988912
Short name T176
Test name
Test status
Simulation time 320440748 ps
CPU time 3.72 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:29 PM UTC 24
Peak memory 235712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759988912 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_t
l_intg_err.759988912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3331664018
Short name T170
Test name
Test status
Simulation time 696478204 ps
CPU time 4.28 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 235440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331664018 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_t
l_intg_err.3331664018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2159634325
Short name T169
Test name
Test status
Simulation time 268318178 ps
CPU time 4.29 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:20 PM UTC 24
Peak memory 223348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159634325 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_t
l_intg_err.2159634325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.153378289
Short name T175
Test name
Test status
Simulation time 138953558 ps
CPU time 4.43 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:22 PM UTC 24
Peak memory 228680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153378289 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl
_intg_err.153378289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2984950771
Short name T73
Test name
Test status
Simulation time 41850337382 ps
CPU time 209.7 seconds
Started Aug 24 08:44:09 PM UTC 24
Finished Aug 24 08:47:41 PM UTC 24
Peak memory 299776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2984950771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 38.lc_ctrl_stress_all.2984950771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2429938394
Short name T70
Test name
Test status
Simulation time 10686995254 ps
CPU time 98.48 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:46:33 PM UTC 24
Peak memory 273184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2429938394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 48.lc_ctrl_stress_all.2429938394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1452604597
Short name T43
Test name
Test status
Simulation time 1653599984 ps
CPU time 9.58 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:26 PM UTC 24
Peak memory 231400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452604597
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_jtag_prog_failure.1452604597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1838320061
Short name T241
Test name
Test status
Simulation time 76078638 ps
CPU time 1.5 seconds
Started Aug 24 08:45:02 PM UTC 24
Finished Aug 24 08:45:05 PM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838320061 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_
aliasing.1838320061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4015621906
Short name T151
Test name
Test status
Simulation time 35603168 ps
CPU time 1.18 seconds
Started Aug 24 08:45:01 PM UTC 24
Finished Aug 24 08:45:03 PM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015621906 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_
hw_reset.4015621906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3153229152
Short name T144
Test name
Test status
Simulation time 46303149 ps
CPU time 2.64 seconds
Started Aug 24 08:45:02 PM UTC 24
Finished Aug 24 08:45:06 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3153229152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3153229152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2522294580
Short name T178
Test name
Test status
Simulation time 15976863 ps
CPU time 1.36 seconds
Started Aug 24 08:45:01 PM UTC 24
Finished Aug 24 08:45:03 PM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522294580 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2522294580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3298978674
Short name T184
Test name
Test status
Simulation time 49870381 ps
CPU time 1.66 seconds
Started Aug 24 08:45:00 PM UTC 24
Finished Aug 24 08:45:02 PM UTC 24
Peak memory 218660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=3298978674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3298978674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3224294643
Short name T882
Test name
Test status
Simulation time 619203197 ps
CPU time 10.21 seconds
Started Aug 24 08:44:58 PM UTC 24
Finished Aug 24 08:45:10 PM UTC 24
Peak memory 219236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3224294643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3224294643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.181357969
Short name T881
Test name
Test status
Simulation time 3406329188 ps
CPU time 9.73 seconds
Started Aug 24 08:44:58 PM UTC 24
Finished Aug 24 08:45:09 PM UTC 24
Peak memory 219148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=181357969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.181357969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2078558895
Short name T157
Test name
Test status
Simulation time 1011941775 ps
CPU time 3.68 seconds
Started Aug 24 08:44:58 PM UTC 24
Finished Aug 24 08:45:03 PM UTC 24
Peak memory 221344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2078558895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2078558895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.858314431
Short name T183
Test name
Test status
Simulation time 110839455 ps
CPU time 2.88 seconds
Started Aug 24 08:44:59 PM UTC 24
Finished Aug 24 08:45:03 PM UTC 24
Peak memory 229688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858314431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_di
sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.858314431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1257524574
Short name T150
Test name
Test status
Simulation time 16292044 ps
CPU time 1.4 seconds
Started Aug 24 08:44:58 PM UTC 24
Finished Aug 24 08:45:01 PM UTC 24
Peak memory 218984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1257524574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1257524574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4103599705
Short name T202
Test name
Test status
Simulation time 30393962 ps
CPU time 1.76 seconds
Started Aug 24 08:45:02 PM UTC 24
Finished Aug 24 08:45:05 PM UTC 24
Peak memory 218436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41035
99705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
lc_ctrl_same_csr_outstanding.4103599705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3695529716
Short name T149
Test name
Test status
Simulation time 104069085 ps
CPU time 5.17 seconds
Started Aug 24 08:45:01 PM UTC 24
Finished Aug 24 08:45:07 PM UTC 24
Peak memory 229824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695529716 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3695529716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.492336885
Short name T877
Test name
Test status
Simulation time 45913107 ps
CPU time 1.52 seconds
Started Aug 24 08:45:05 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492336885 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_a
liasing.492336885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3986510217
Short name T203
Test name
Test status
Simulation time 373714829 ps
CPU time 2.71 seconds
Started Aug 24 08:45:04 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 219376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986510217 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_
bit_bash.3986510217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4294416271
Short name T242
Test name
Test status
Simulation time 33232038 ps
CPU time 1.27 seconds
Started Aug 24 08:45:04 PM UTC 24
Finished Aug 24 08:45:06 PM UTC 24
Peak memory 220092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294416271 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_
hw_reset.4294416271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2807796713
Short name T227
Test name
Test status
Simulation time 21247988 ps
CPU time 1.51 seconds
Started Aug 24 08:45:05 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 226688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2807796713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2807796713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3850342828
Short name T875
Test name
Test status
Simulation time 28580222 ps
CPU time 1.39 seconds
Started Aug 24 08:45:04 PM UTC 24
Finished Aug 24 08:45:06 PM UTC 24
Peak memory 218668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850342828 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3850342828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.866817880
Short name T876
Test name
Test status
Simulation time 91172391 ps
CPU time 2.03 seconds
Started Aug 24 08:45:04 PM UTC 24
Finished Aug 24 08:45:07 PM UTC 24
Peak memory 217988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=866817880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.866817880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4156674840
Short name T916
Test name
Test status
Simulation time 514638204 ps
CPU time 14.82 seconds
Started Aug 24 08:45:02 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 218492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=4156674840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4156674840
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3167017827
Short name T983
Test name
Test status
Simulation time 7925895139 ps
CPU time 25.27 seconds
Started Aug 24 08:45:02 PM UTC 24
Finished Aug 24 08:45:29 PM UTC 24
Peak memory 219244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3167017827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3167017827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1275695362
Short name T874
Test name
Test status
Simulation time 408559313 ps
CPU time 2.17 seconds
Started Aug 24 08:45:02 PM UTC 24
Finished Aug 24 08:45:06 PM UTC 24
Peak memory 221204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1275695362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1275695362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.147162048
Short name T161
Test name
Test status
Simulation time 386479934 ps
CPU time 2.4 seconds
Started Aug 24 08:45:04 PM UTC 24
Finished Aug 24 08:45:07 PM UTC 24
Peak memory 233084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147162048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_di
sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.147162048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3156801928
Short name T180
Test name
Test status
Simulation time 63488695 ps
CPU time 2.58 seconds
Started Aug 24 08:45:02 PM UTC 24
Finished Aug 24 08:45:06 PM UTC 24
Peak memory 219512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3156801928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_csr_rw.3156801928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.11515358
Short name T250
Test name
Test status
Simulation time 41020592 ps
CPU time 1.93 seconds
Started Aug 24 08:45:03 PM UTC 24
Finished Aug 24 08:45:06 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=11515358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.11515358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3527475483
Short name T251
Test name
Test status
Simulation time 16111290 ps
CPU time 1.75 seconds
Started Aug 24 08:45:05 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35274
75483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
lc_ctrl_same_csr_outstanding.3527475483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2183583914
Short name T160
Test name
Test status
Simulation time 94008318 ps
CPU time 2.66 seconds
Started Aug 24 08:45:04 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183583914 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2183583914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3647264881
Short name T148
Test name
Test status
Simulation time 127130194 ps
CPU time 5.76 seconds
Started Aug 24 08:45:04 PM UTC 24
Finished Aug 24 08:45:11 PM UTC 24
Peak memory 229804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647264881 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_t
l_intg_err.3647264881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1189494755
Short name T951
Test name
Test status
Simulation time 111063500 ps
CPU time 2.07 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 231852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1189494755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1189494755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1812296649
Short name T941
Test name
Test status
Simulation time 18938952 ps
CPU time 1.2 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:22 PM UTC 24
Peak memory 218124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812296649 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1812296649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.536868830
Short name T944
Test name
Test status
Simulation time 34835855 ps
CPU time 1.35 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 218600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53686
8830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
lc_ctrl_same_csr_outstanding.536868830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3873806614
Short name T956
Test name
Test status
Simulation time 53303181 ps
CPU time 2.87 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 229356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873806614 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3873806614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1969009821
Short name T173
Test name
Test status
Simulation time 75653550 ps
CPU time 2.67 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 223416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969009821 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
tl_intg_err.1969009821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.945277027
Short name T958
Test name
Test status
Simulation time 43061978 ps
CPU time 1.83 seconds
Started Aug 24 08:45:21 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 232408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=945277027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.945277027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2622973057
Short name T955
Test name
Test status
Simulation time 16734545 ps
CPU time 1.58 seconds
Started Aug 24 08:45:21 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 218512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622973057 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2622973057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3910557085
Short name T957
Test name
Test status
Simulation time 47484327 ps
CPU time 1.75 seconds
Started Aug 24 08:45:21 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 220600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39105
57085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.lc_ctrl_same_csr_outstanding.3910557085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.335251186
Short name T960
Test name
Test status
Simulation time 172926899 ps
CPU time 2.42 seconds
Started Aug 24 08:45:21 PM UTC 24
Finished Aug 24 08:45:25 PM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335251186 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.335251186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2425769882
Short name T962
Test name
Test status
Simulation time 22851976 ps
CPU time 1.48 seconds
Started Aug 24 08:45:22 PM UTC 24
Finished Aug 24 08:45:25 PM UTC 24
Peak memory 232408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2425769882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2425769882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.821419580
Short name T953
Test name
Test status
Simulation time 58810141 ps
CPU time 1.37 seconds
Started Aug 24 08:45:21 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 218100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821419580 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.821419580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1320248985
Short name T964
Test name
Test status
Simulation time 28766459 ps
CPU time 1.97 seconds
Started Aug 24 08:45:22 PM UTC 24
Finished Aug 24 08:45:25 PM UTC 24
Peak memory 218520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13202
48985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.lc_ctrl_same_csr_outstanding.1320248985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1030675212
Short name T967
Test name
Test status
Simulation time 677566123 ps
CPU time 3.5 seconds
Started Aug 24 08:45:21 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030675212 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1030675212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4237371888
Short name T166
Test name
Test status
Simulation time 52697911 ps
CPU time 2.74 seconds
Started Aug 24 08:45:21 PM UTC 24
Finished Aug 24 08:45:25 PM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237371888 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
tl_intg_err.4237371888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3248570649
Short name T968
Test name
Test status
Simulation time 100088153 ps
CPU time 2.32 seconds
Started Aug 24 08:45:22 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3248570649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3248570649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4090140599
Short name T961
Test name
Test status
Simulation time 17204542 ps
CPU time 1.35 seconds
Started Aug 24 08:45:22 PM UTC 24
Finished Aug 24 08:45:25 PM UTC 24
Peak memory 218512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090140599 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4090140599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.998453512
Short name T963
Test name
Test status
Simulation time 88969425 ps
CPU time 1.53 seconds
Started Aug 24 08:45:22 PM UTC 24
Finished Aug 24 08:45:25 PM UTC 24
Peak memory 218544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99845
3512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
lc_ctrl_same_csr_outstanding.998453512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.463637180
Short name T159
Test name
Test status
Simulation time 45556747 ps
CPU time 2.71 seconds
Started Aug 24 08:45:22 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463637180 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.463637180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.746451810
Short name T970
Test name
Test status
Simulation time 61760155 ps
CPU time 1.4 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=746451810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.746451810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1768878491
Short name T969
Test name
Test status
Simulation time 24075841 ps
CPU time 1.16 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 217936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768878491 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1768878491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1184709832
Short name T974
Test name
Test status
Simulation time 31472251 ps
CPU time 1.5 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 218544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11847
09832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.lc_ctrl_same_csr_outstanding.1184709832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.545376173
Short name T977
Test name
Test status
Simulation time 143208976 ps
CPU time 2.29 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:27 PM UTC 24
Peak memory 229256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545376173 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.545376173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2876220867
Short name T972
Test name
Test status
Simulation time 17878598 ps
CPU time 1.25 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2876220867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2876220867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2484416861
Short name T247
Test name
Test status
Simulation time 46374084 ps
CPU time 1.57 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 218124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484416861 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2484416861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1746545784
Short name T976
Test name
Test status
Simulation time 138433364 ps
CPU time 1.83 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:27 PM UTC 24
Peak memory 218492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17465
45784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.lc_ctrl_same_csr_outstanding.1746545784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.554084551
Short name T980
Test name
Test status
Simulation time 144621884 ps
CPU time 2.9 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:28 PM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554084551 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.554084551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2402024427
Short name T978
Test name
Test status
Simulation time 45696373 ps
CPU time 2.25 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:27 PM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402024427 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
tl_intg_err.2402024427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1539765364
Short name T990
Test name
Test status
Simulation time 21768355 ps
CPU time 1.75 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 234456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1539765364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1539765364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1716950813
Short name T971
Test name
Test status
Simulation time 12209949 ps
CPU time 1.2 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 218124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716950813 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1716950813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3474533083
Short name T985
Test name
Test status
Simulation time 129311888 ps
CPU time 1.25 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:30 PM UTC 24
Peak memory 218492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34745
33083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.lc_ctrl_same_csr_outstanding.3474533083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1037881468
Short name T973
Test name
Test status
Simulation time 88541321 ps
CPU time 1.84 seconds
Started Aug 24 08:45:24 PM UTC 24
Finished Aug 24 08:45:27 PM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037881468 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1037881468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3146191830
Short name T986
Test name
Test status
Simulation time 16429843 ps
CPU time 1.2 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3146191830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3146191830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.95000188
Short name T965
Test name
Test status
Simulation time 15074436 ps
CPU time 1.05 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:30 PM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95000188 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.95000188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.865051702
Short name T989
Test name
Test status
Simulation time 18407909 ps
CPU time 1.68 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 218500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86505
1702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
lc_ctrl_same_csr_outstanding.865051702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.908574797
Short name T993
Test name
Test status
Simulation time 58789152 ps
CPU time 2.1 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908574797 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.908574797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3014267770
Short name T171
Test name
Test status
Simulation time 108210686 ps
CPU time 3.07 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:32 PM UTC 24
Peak memory 235704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014267770 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
tl_intg_err.3014267770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3502677891
Short name T988
Test name
Test status
Simulation time 76517345 ps
CPU time 1.35 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3502677891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3502677891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2230788776
Short name T987
Test name
Test status
Simulation time 15475237 ps
CPU time 1.32 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 218052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230788776 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2230788776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.883086864
Short name T992
Test name
Test status
Simulation time 21420186 ps
CPU time 1.64 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88308
6864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
lc_ctrl_same_csr_outstanding.883086864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3651203371
Short name T994
Test name
Test status
Simulation time 230225460 ps
CPU time 2.17 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:32 PM UTC 24
Peak memory 229492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651203371 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3651203371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2377348878
Short name T996
Test name
Test status
Simulation time 138872800 ps
CPU time 1.62 seconds
Started Aug 24 08:45:26 PM UTC 24
Finished Aug 24 08:45:35 PM UTC 24
Peak memory 234456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2377348878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2377348878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3055092558
Short name T249
Test name
Test status
Simulation time 19012371 ps
CPU time 0.96 seconds
Started Aug 24 08:45:26 PM UTC 24
Finished Aug 24 08:45:35 PM UTC 24
Peak memory 216292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055092558 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3055092558
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.865464859
Short name T997
Test name
Test status
Simulation time 28428017 ps
CPU time 1.49 seconds
Started Aug 24 08:45:26 PM UTC 24
Finished Aug 24 08:45:36 PM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86546
4859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
lc_ctrl_same_csr_outstanding.865464859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3442200390
Short name T995
Test name
Test status
Simulation time 315230119 ps
CPU time 2.88 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:32 PM UTC 24
Peak memory 229492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442200390 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3442200390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4201475209
Short name T177
Test name
Test status
Simulation time 56678251 ps
CPU time 1.74 seconds
Started Aug 24 08:45:25 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 234512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201475209 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
tl_intg_err.4201475209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.935274793
Short name T884
Test name
Test status
Simulation time 23307536 ps
CPU time 1.56 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:10 PM UTC 24
Peak memory 218000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935274793 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_a
liasing.935274793
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.249831342
Short name T886
Test name
Test status
Simulation time 72889476 ps
CPU time 2.47 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:11 PM UTC 24
Peak memory 219296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249831342 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_b
it_bash.249831342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1158027298
Short name T879
Test name
Test status
Simulation time 55360418 ps
CPU time 1.41 seconds
Started Aug 24 08:45:06 PM UTC 24
Finished Aug 24 08:45:09 PM UTC 24
Peak memory 220176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158027298 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_
hw_reset.1158027298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3992865075
Short name T162
Test name
Test status
Simulation time 32109676 ps
CPU time 2.02 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:11 PM UTC 24
Peak memory 229828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3992865075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3992865075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3336840083
Short name T883
Test name
Test status
Simulation time 12203112 ps
CPU time 1.2 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:10 PM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336840083 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3336840083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1498641408
Short name T880
Test name
Test status
Simulation time 44303350 ps
CPU time 1.6 seconds
Started Aug 24 08:45:06 PM UTC 24
Finished Aug 24 08:45:09 PM UTC 24
Peak memory 218660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=1498641408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1498641408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.416122005
Short name T905
Test name
Test status
Simulation time 445557233 ps
CPU time 8.22 seconds
Started Aug 24 08:45:06 PM UTC 24
Finished Aug 24 08:45:16 PM UTC 24
Peak memory 218996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=416122005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.416122005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1206553093
Short name T938
Test name
Test status
Simulation time 1933905983 ps
CPU time 14.73 seconds
Started Aug 24 08:45:06 PM UTC 24
Finished Aug 24 08:45:22 PM UTC 24
Peak memory 218404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1206553093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1206553093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4172301230
Short name T181
Test name
Test status
Simulation time 123913560 ps
CPU time 2.88 seconds
Started Aug 24 08:45:05 PM UTC 24
Finished Aug 24 08:45:09 PM UTC 24
Peak memory 219984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=4172301230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4172301230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2510678013
Short name T896
Test name
Test status
Simulation time 1041938516 ps
CPU time 6.73 seconds
Started Aug 24 08:45:06 PM UTC 24
Finished Aug 24 08:45:14 PM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510678013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2510678013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3431819843
Short name T878
Test name
Test status
Simulation time 51821007 ps
CPU time 2.3 seconds
Started Aug 24 08:45:05 PM UTC 24
Finished Aug 24 08:45:09 PM UTC 24
Peak memory 219156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3431819843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_csr_rw.3431819843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1940047331
Short name T252
Test name
Test status
Simulation time 28021338 ps
CPU time 1.97 seconds
Started Aug 24 08:45:06 PM UTC 24
Finished Aug 24 08:45:09 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1940047331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1940047331
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4212358500
Short name T204
Test name
Test status
Simulation time 172713069 ps
CPU time 1.64 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:11 PM UTC 24
Peak memory 218548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42123
58500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
lc_ctrl_same_csr_outstanding.4212358500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3943459944
Short name T154
Test name
Test status
Simulation time 286914381 ps
CPU time 4.44 seconds
Started Aug 24 08:45:06 PM UTC 24
Finished Aug 24 08:45:12 PM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943459944 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3943459944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2842227223
Short name T147
Test name
Test status
Simulation time 380235613 ps
CPU time 2.72 seconds
Started Aug 24 08:45:06 PM UTC 24
Finished Aug 24 08:45:10 PM UTC 24
Peak memory 233716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842227223 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_t
l_intg_err.2842227223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3259620823
Short name T890
Test name
Test status
Simulation time 25660967 ps
CPU time 1.68 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:12 PM UTC 24
Peak memory 218548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259620823 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_
aliasing.3259620823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3899344765
Short name T892
Test name
Test status
Simulation time 123751330 ps
CPU time 2.59 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:13 PM UTC 24
Peak memory 218684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899344765 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_
bit_bash.3899344765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3926454474
Short name T889
Test name
Test status
Simulation time 12795723 ps
CPU time 1.48 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:12 PM UTC 24
Peak memory 220176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926454474 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_
hw_reset.3926454474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3798707334
Short name T891
Test name
Test status
Simulation time 24945235 ps
CPU time 2.18 seconds
Started Aug 24 08:45:10 PM UTC 24
Finished Aug 24 08:45:13 PM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3798707334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3798707334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2052861026
Short name T887
Test name
Test status
Simulation time 124106345 ps
CPU time 1.18 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:12 PM UTC 24
Peak memory 218032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052861026 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2052861026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2062697943
Short name T888
Test name
Test status
Simulation time 16605657 ps
CPU time 1.5 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:12 PM UTC 24
Peak memory 218520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=2062697943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2062697943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2587575287
Short name T940
Test name
Test status
Simulation time 518079443 ps
CPU time 13.41 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:22 PM UTC 24
Peak memory 218632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2587575287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2587575287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1499062607
Short name T911
Test name
Test status
Simulation time 1972474540 ps
CPU time 8.59 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:18 PM UTC 24
Peak memory 219212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1499062607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1499062607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3995577139
Short name T901
Test name
Test status
Simulation time 164985025 ps
CPU time 6.02 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 221224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3995577139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3995577139
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.351768766
Short name T897
Test name
Test status
Simulation time 119397101 ps
CPU time 4.11 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 235720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351768766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_di
sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.351768766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3147282893
Short name T885
Test name
Test status
Simulation time 55352649 ps
CPU time 1.92 seconds
Started Aug 24 08:45:08 PM UTC 24
Finished Aug 24 08:45:11 PM UTC 24
Peak memory 218012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3147282893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_csr_rw.3147282893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.404744871
Short name T253
Test name
Test status
Simulation time 23179697 ps
CPU time 1.83 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:12 PM UTC 24
Peak memory 220180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=404744871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.404744871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.11317512
Short name T254
Test name
Test status
Simulation time 20485608 ps
CPU time 1.77 seconds
Started Aug 24 08:45:09 PM UTC 24
Finished Aug 24 08:45:12 PM UTC 24
Peak memory 228772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11317
512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc
_ctrl_same_csr_outstanding.11317512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1408098908
Short name T244
Test name
Test status
Simulation time 23265948 ps
CPU time 1.47 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 218792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408098908 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_
aliasing.1408098908
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3643631060
Short name T245
Test name
Test status
Simulation time 22312121 ps
CPU time 1.55 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 218544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643631060 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_
bit_bash.3643631060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1687986836
Short name T895
Test name
Test status
Simulation time 56057964 ps
CPU time 1.66 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:14 PM UTC 24
Peak memory 220176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687986836 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_
hw_reset.1687986836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2378571513
Short name T898
Test name
Test status
Simulation time 17225566 ps
CPU time 1.46 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2378571513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2378571513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.992023346
Short name T243
Test name
Test status
Simulation time 31593185 ps
CPU time 1.36 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:13 PM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992023346 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.992023346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2080363130
Short name T894
Test name
Test status
Simulation time 45004492 ps
CPU time 1.58 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:14 PM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=2080363130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2080363130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.894604133
Short name T930
Test name
Test status
Simulation time 690460999 ps
CPU time 8.28 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:20 PM UTC 24
Peak memory 218268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=894604133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.894604133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3167112795
Short name T981
Test name
Test status
Simulation time 4342125357 ps
CPU time 15.75 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:28 PM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3167112795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3167112795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.451864122
Short name T893
Test name
Test status
Simulation time 849537614 ps
CPU time 2.56 seconds
Started Aug 24 08:45:10 PM UTC 24
Finished Aug 24 08:45:13 PM UTC 24
Peak memory 221492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=451864122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.451864122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.658900444
Short name T899
Test name
Test status
Simulation time 343342564 ps
CPU time 2.9 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 219192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=658900444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_rw.658900444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2998787180
Short name T255
Test name
Test status
Simulation time 58454562 ps
CPU time 1.95 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:14 PM UTC 24
Peak memory 218544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2998787180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2998787180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2222205777
Short name T900
Test name
Test status
Simulation time 55491577 ps
CPU time 1.57 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 218156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22222
05777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
lc_ctrl_same_csr_outstanding.2222205777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3235677289
Short name T906
Test name
Test status
Simulation time 281547924 ps
CPU time 3.85 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:16 PM UTC 24
Peak memory 229488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235677289 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3235677289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3875920731
Short name T172
Test name
Test status
Simulation time 79922139 ps
CPU time 3.6 seconds
Started Aug 24 08:45:11 PM UTC 24
Finished Aug 24 08:45:16 PM UTC 24
Peak memory 235628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875920731 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_t
l_intg_err.3875920731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2702457085
Short name T907
Test name
Test status
Simulation time 13208478 ps
CPU time 1.36 seconds
Started Aug 24 08:45:14 PM UTC 24
Finished Aug 24 08:45:16 PM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2702457085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2702457085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.541744924
Short name T904
Test name
Test status
Simulation time 14148667 ps
CPU time 1.11 seconds
Started Aug 24 08:45:13 PM UTC 24
Finished Aug 24 08:45:16 PM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541744924 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.541744924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2621953264
Short name T910
Test name
Test status
Simulation time 463971709 ps
CPU time 2.8 seconds
Started Aug 24 08:45:13 PM UTC 24
Finished Aug 24 08:45:17 PM UTC 24
Peak memory 219180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=2621953264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2621953264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3617327248
Short name T925
Test name
Test status
Simulation time 370405302 ps
CPU time 6.11 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:20 PM UTC 24
Peak memory 219024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3617327248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3617327248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.70700843
Short name T998
Test name
Test status
Simulation time 1244041364 ps
CPU time 29.56 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:43 PM UTC 24
Peak memory 219088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=70700843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.70700843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2460037697
Short name T908
Test name
Test status
Simulation time 82035859 ps
CPU time 3.13 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:16 PM UTC 24
Peak memory 220392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2460037697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2460037697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4285336968
Short name T921
Test name
Test status
Simulation time 219188857 ps
CPU time 4.61 seconds
Started Aug 24 08:45:13 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 229948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285336968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4285336968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1989065210
Short name T903
Test name
Test status
Simulation time 229899619 ps
CPU time 1.99 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 218488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1989065210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_csr_rw.1989065210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1817912360
Short name T902
Test name
Test status
Simulation time 32934906 ps
CPU time 1.71 seconds
Started Aug 24 08:45:12 PM UTC 24
Finished Aug 24 08:45:15 PM UTC 24
Peak memory 218488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1817912360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1817912360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3280337180
Short name T909
Test name
Test status
Simulation time 21345489 ps
CPU time 1.91 seconds
Started Aug 24 08:45:14 PM UTC 24
Finished Aug 24 08:45:17 PM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32803
37180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
lc_ctrl_same_csr_outstanding.3280337180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1804292106
Short name T943
Test name
Test status
Simulation time 135396471 ps
CPU time 7.88 seconds
Started Aug 24 08:45:13 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 229404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804292106 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1804292106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2475778775
Short name T922
Test name
Test status
Simulation time 55416869 ps
CPU time 2.16 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 231672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2475778775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2475778775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4038236563
Short name T914
Test name
Test status
Simulation time 65063302 ps
CPU time 1.98 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:18 PM UTC 24
Peak memory 218660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=4038236563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.4038236563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3143846735
Short name T949
Test name
Test status
Simulation time 333076392 ps
CPU time 7.04 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 219072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3143846735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3143846735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2877865450
Short name T952
Test name
Test status
Simulation time 3705521172 ps
CPU time 7.8 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 218288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2877865450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2877865450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3517258182
Short name T920
Test name
Test status
Simulation time 130693871 ps
CPU time 4.29 seconds
Started Aug 24 08:45:14 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 221304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3517258182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3517258182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.722711446
Short name T924
Test name
Test status
Simulation time 861278368 ps
CPU time 3.54 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 229600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722711446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_di
sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.722711446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.708513273
Short name T912
Test name
Test status
Simulation time 66898655 ps
CPU time 3.03 seconds
Started Aug 24 08:45:14 PM UTC 24
Finished Aug 24 08:45:18 PM UTC 24
Peak memory 219188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=708513273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_rw.708513273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3076856972
Short name T918
Test name
Test status
Simulation time 188141504 ps
CPU time 2.79 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3076856972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3076856972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.806163036
Short name T913
Test name
Test status
Simulation time 51490326 ps
CPU time 1.91 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:18 PM UTC 24
Peak memory 218464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80616
3036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.l
c_ctrl_same_csr_outstanding.806163036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4052889245
Short name T168
Test name
Test status
Simulation time 610428349 ps
CPU time 4.4 seconds
Started Aug 24 08:45:15 PM UTC 24
Finished Aug 24 08:45:20 PM UTC 24
Peak memory 231536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052889245 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4052889245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1156729005
Short name T923
Test name
Test status
Simulation time 25107529 ps
CPU time 1.89 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1156729005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1156729005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3408411080
Short name T246
Test name
Test status
Simulation time 15124604 ps
CPU time 1.43 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 218048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408411080 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3408411080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2536173445
Short name T926
Test name
Test status
Simulation time 149102162 ps
CPU time 2.4 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:20 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=2536173445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2536173445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3301259326
Short name T966
Test name
Test status
Simulation time 1166713007 ps
CPU time 8.28 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 219056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3301259326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3301259326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3398283514
Short name T984
Test name
Test status
Simulation time 2606698841 ps
CPU time 11.92 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:29 PM UTC 24
Peak memory 218600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3398283514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3398283514
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2322140133
Short name T927
Test name
Test status
Simulation time 244174852 ps
CPU time 2.63 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:20 PM UTC 24
Peak memory 221132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2322140133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2322140133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.682770302
Short name T929
Test name
Test status
Simulation time 50832426 ps
CPU time 3.03 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:20 PM UTC 24
Peak memory 236028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682770302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_di
sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.682770302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4062044788
Short name T917
Test name
Test status
Simulation time 236209438 ps
CPU time 1.63 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 218656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4062044788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_csr_rw.4062044788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3838559770
Short name T915
Test name
Test status
Simulation time 50101612 ps
CPU time 1.33 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:18 PM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3838559770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3838559770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3205840933
Short name T919
Test name
Test status
Simulation time 44417339 ps
CPU time 1.51 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 230816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32058
40933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
lc_ctrl_same_csr_outstanding.3205840933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4919808
Short name T959
Test name
Test status
Simulation time 144790003 ps
CPU time 6.83 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 229168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4919808 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4919808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1942047336
Short name T937
Test name
Test status
Simulation time 36156992 ps
CPU time 1.96 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:22 PM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1942047336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1942047336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2325195221
Short name T248
Test name
Test status
Simulation time 11919402 ps
CPU time 1.27 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:21 PM UTC 24
Peak memory 218000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325195221 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2325195221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2281080321
Short name T931
Test name
Test status
Simulation time 446070359 ps
CPU time 2.07 seconds
Started Aug 24 08:45:18 PM UTC 24
Finished Aug 24 08:45:21 PM UTC 24
Peak memory 219356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=2281080321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2281080321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2782037493
Short name T991
Test name
Test status
Simulation time 700881246 ps
CPU time 12.44 seconds
Started Aug 24 08:45:18 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 219020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2782037493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2782037493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3345801353
Short name T999
Test name
Test status
Simulation time 2084555096 ps
CPU time 24.75 seconds
Started Aug 24 08:45:18 PM UTC 24
Finished Aug 24 08:45:43 PM UTC 24
Peak memory 219092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3345801353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3345801353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4018365362
Short name T935
Test name
Test status
Simulation time 462394864 ps
CPU time 4.07 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:21 PM UTC 24
Peak memory 221248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=4018365362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4018365362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4062843992
Short name T932
Test name
Test status
Simulation time 247400454 ps
CPU time 2.16 seconds
Started Aug 24 08:45:18 PM UTC 24
Finished Aug 24 08:45:21 PM UTC 24
Peak memory 231928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062843992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4062843992
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2278318587
Short name T928
Test name
Test status
Simulation time 86693027 ps
CPU time 2.51 seconds
Started Aug 24 08:45:16 PM UTC 24
Finished Aug 24 08:45:20 PM UTC 24
Peak memory 219084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2278318587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_csr_rw.2278318587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3926523554
Short name T933
Test name
Test status
Simulation time 97695116 ps
CPU time 1.69 seconds
Started Aug 24 08:45:18 PM UTC 24
Finished Aug 24 08:45:21 PM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3926523554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3926523554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2285056161
Short name T934
Test name
Test status
Simulation time 197844247 ps
CPU time 1.6 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:21 PM UTC 24
Peak memory 218548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22850
56161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
lc_ctrl_same_csr_outstanding.2285056161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1240818014
Short name T950
Test name
Test status
Simulation time 105612544 ps
CPU time 3.56 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 229500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240818014 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1240818014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1523130544
Short name T948
Test name
Test status
Simulation time 18697683 ps
CPU time 1.52 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 228848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1523130544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1523130544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1386282082
Short name T939
Test name
Test status
Simulation time 36030504 ps
CPU time 1.22 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:22 PM UTC 24
Peak memory 218364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386282082 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1386282082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3413560682
Short name T946
Test name
Test status
Simulation time 48986494 ps
CPU time 1.47 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 217504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=3413560682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3413560682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4248196926
Short name T979
Test name
Test status
Simulation time 1958927723 ps
CPU time 7.37 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:27 PM UTC 24
Peak memory 218892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=4248196926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.4248196926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1212556371
Short name T982
Test name
Test status
Simulation time 485134133 ps
CPU time 7.83 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:28 PM UTC 24
Peak memory 219104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1212556371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1212556371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1494643146
Short name T936
Test name
Test status
Simulation time 83301605 ps
CPU time 1.7 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:22 PM UTC 24
Peak memory 220540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1494643146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1494643146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3654598673
Short name T975
Test name
Test status
Simulation time 189433661 ps
CPU time 5.12 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 235928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654598673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3654598673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.20363210
Short name T947
Test name
Test status
Simulation time 132416187 ps
CPU time 2.77 seconds
Started Aug 24 08:45:19 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 219184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=20363210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_rw.20363210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1136626930
Short name T945
Test name
Test status
Simulation time 134131141 ps
CPU time 1.64 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 220376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1136626930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1136626930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2387972558
Short name T942
Test name
Test status
Simulation time 42802768 ps
CPU time 1.49 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:23 PM UTC 24
Peak memory 228604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23879
72558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
lc_ctrl_same_csr_outstanding.2387972558
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1297033807
Short name T954
Test name
Test status
Simulation time 28359515 ps
CPU time 2.69 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 228972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297033807 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1297033807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4164860473
Short name T164
Test name
Test status
Simulation time 311656536 ps
CPU time 4.23 seconds
Started Aug 24 08:45:20 PM UTC 24
Finished Aug 24 08:45:26 PM UTC 24
Peak memory 223340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164860473 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_t
l_intg_err.4164860473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.831793301
Short name T15
Test name
Test status
Simulation time 19783441 ps
CPU time 1.27 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:18 PM UTC 24
Peak memory 217332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831793301 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.831793301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3893025685
Short name T619
Test name
Test status
Simulation time 18594427804 ps
CPU time 149.07 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:43:47 PM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893025685
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_errors.3893025685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1913468664
Short name T87
Test name
Test status
Simulation time 1469370160 ps
CPU time 31.63 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:48 PM UTC 24
Peak memory 227636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913468664
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.l
c_ctrl_jtag_regwen_during_op.1913468664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3827184129
Short name T38
Test name
Test status
Simulation time 1227878878 ps
CPU time 9.76 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:26 PM UTC 24
Peak memory 228624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827184129
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_smoke.3827184129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.2733979998
Short name T460
Test name
Test status
Simulation time 7260570378 ps
CPU time 97.45 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:42:55 PM UTC 24
Peak memory 289092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733979998
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_c
trl_jtag_state_failure.2733979998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.2771256342
Short name T6
Test name
Test status
Simulation time 168453594 ps
CPU time 3.05 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:19 PM UTC 24
Peak memory 230656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771256342 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2771256342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3056647080
Short name T103
Test name
Test status
Simulation time 718694995 ps
CPU time 17.27 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:34 PM UTC 24
Peak memory 227940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056647080 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3056647080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1506769775
Short name T108
Test name
Test status
Simulation time 123088584 ps
CPU time 36.31 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:53 PM UTC 24
Peak memory 288772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506769775 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1506769775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3138227054
Short name T275
Test name
Test status
Simulation time 248697534 ps
CPU time 14.11 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:31 PM UTC 24
Peak memory 238164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138227054 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_t
oken_digest.3138227054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.3250536157
Short name T262
Test name
Test status
Simulation time 545128257 ps
CPU time 31.18 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:48 PM UTC 24
Peak memory 260832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250536157 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3250536157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.444254049
Short name T57
Test name
Test status
Simulation time 255004482 ps
CPU time 12.38 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:29 PM UTC 24
Peak memory 262328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444254049 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.444254049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2426437644
Short name T14
Test name
Test status
Simulation time 38074119 ps
CPU time 1.25 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:17 PM UTC 24
Peak memory 221116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426437644 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_volatile_unlock_smoke.2426437644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.817278516
Short name T17
Test name
Test status
Simulation time 14546478 ps
CPU time 1.3 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:18 PM UTC 24
Peak memory 217020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817278516 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.817278516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2390725371
Short name T279
Test name
Test status
Simulation time 800794902 ps
CPU time 16.41 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:33 PM UTC 24
Peak memory 231988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390725371 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2390725371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.2657043323
Short name T105
Test name
Test status
Simulation time 1320638206 ps
CPU time 28.43 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:45 PM UTC 24
Peak memory 230896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657043323
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_errors.2657043323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.4283069534
Short name T237
Test name
Test status
Simulation time 1151371526 ps
CPU time 17.35 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:34 PM UTC 24
Peak memory 229888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283069534 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_pri
ority.4283069534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3684864678
Short name T276
Test name
Test status
Simulation time 446876187 ps
CPU time 16.61 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:33 PM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684864678
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_jtag_prog_failure.3684864678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1221265949
Short name T300
Test name
Test status
Simulation time 1438851952 ps
CPU time 28.56 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:45 PM UTC 24
Peak memory 229688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221265949
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.l
c_ctrl_jtag_regwen_during_op.1221265949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3968055664
Short name T45
Test name
Test status
Simulation time 1097206840 ps
CPU time 11.55 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:28 PM UTC 24
Peak memory 227360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968055664
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_smoke.3968055664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.4156760462
Short name T458
Test name
Test status
Simulation time 12159585326 ps
CPU time 96.33 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:42:54 PM UTC 24
Peak memory 288944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156760462
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_c
trl_jtag_state_failure.4156760462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.4063840008
Short name T269
Test name
Test status
Simulation time 2822225759 ps
CPU time 32.08 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:49 PM UTC 24
Peak memory 262608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063840008
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.l
c_ctrl_jtag_state_post_trans.4063840008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.627498813
Short name T5
Test name
Test status
Simulation time 216379758 ps
CPU time 2.19 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:18 PM UTC 24
Peak memory 231276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627498813 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.627498813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.3160098349
Short name T85
Test name
Test status
Simulation time 300264671 ps
CPU time 12.18 seconds
Started Aug 24 08:41:13 PM UTC 24
Finished Aug 24 08:41:29 PM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160098349 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3160098349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2842737911
Short name T107
Test name
Test status
Simulation time 132251360 ps
CPU time 32.73 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:50 PM UTC 24
Peak memory 289080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842737911 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2842737911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2499929859
Short name T153
Test name
Test status
Simulation time 1068290810 ps
CPU time 13.96 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:30 PM UTC 24
Peak memory 237812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499929859 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2499929859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3450227296
Short name T22
Test name
Test status
Simulation time 276248319 ps
CPU time 14.68 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:31 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450227296 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_t
oken_digest.3450227296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.3657271154
Short name T60
Test name
Test status
Simulation time 367074524 ps
CPU time 12.11 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:29 PM UTC 24
Peak memory 230024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657271154 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_toke
n_mux.3657271154
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2633702955
Short name T36
Test name
Test status
Simulation time 649358389 ps
CPU time 9.69 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:26 PM UTC 24
Peak memory 229348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633702955 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2633702955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.999472609
Short name T23
Test name
Test status
Simulation time 110042417 ps
CPU time 4.35 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:21 PM UTC 24
Peak memory 228096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999472609 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.999472609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2118959212
Short name T325
Test name
Test status
Simulation time 266107808 ps
CPU time 1.3 seconds
Started Aug 24 08:41:57 PM UTC 24
Finished Aug 24 08:42:00 PM UTC 24
Peak memory 219008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118959212 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2118959212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1819205769
Short name T62
Test name
Test status
Simulation time 432425690 ps
CPU time 15.9 seconds
Started Aug 24 08:41:54 PM UTC 24
Finished Aug 24 08:42:11 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819205769 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1819205769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.615522643
Short name T53
Test name
Test status
Simulation time 157603294 ps
CPU time 3.72 seconds
Started Aug 24 08:41:55 PM UTC 24
Finished Aug 24 08:42:00 PM UTC 24
Peak memory 229852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615522643 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.615522643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.1005897560
Short name T425
Test name
Test status
Simulation time 6050789871 ps
CPU time 41.27 seconds
Started Aug 24 08:41:55 PM UTC 24
Finished Aug 24 08:42:38 PM UTC 24
Peak memory 232280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005897560
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_errors.1005897560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.3768994560
Short name T343
Test name
Test status
Simulation time 901692875 ps
CPU time 8.89 seconds
Started Aug 24 08:41:55 PM UTC 24
Finished Aug 24 08:42:05 PM UTC 24
Peak memory 232044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768994560
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_jtag_prog_failure.3768994560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1260372114
Short name T321
Test name
Test status
Simulation time 108254272 ps
CPU time 2.96 seconds
Started Aug 24 08:41:54 PM UTC 24
Finished Aug 24 08:41:58 PM UTC 24
Peak memory 230064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260372114
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_smoke.1260372114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3261172973
Short name T548
Test name
Test status
Simulation time 1891939983 ps
CPU time 89.77 seconds
Started Aug 24 08:41:54 PM UTC 24
Finished Aug 24 08:43:26 PM UTC 24
Peak memory 291428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261172973
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_
ctrl_jtag_state_failure.3261172973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.443149549
Short name T363
Test name
Test status
Simulation time 858520091 ps
CPU time 17.24 seconds
Started Aug 24 08:41:54 PM UTC 24
Finished Aug 24 08:42:12 PM UTC 24
Peak memory 262700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443149549
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.l
c_ctrl_jtag_state_post_trans.443149549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1759207164
Short name T308
Test name
Test status
Simulation time 50247142 ps
CPU time 3.33 seconds
Started Aug 24 08:41:53 PM UTC 24
Finished Aug 24 08:41:57 PM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759207164 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1759207164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.968408859
Short name T68
Test name
Test status
Simulation time 1510108890 ps
CPU time 15.15 seconds
Started Aug 24 08:41:55 PM UTC 24
Finished Aug 24 08:42:11 PM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968408859 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.968408859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.2827833468
Short name T366
Test name
Test status
Simulation time 6357124315 ps
CPU time 18.31 seconds
Started Aug 24 08:41:56 PM UTC 24
Finished Aug 24 08:42:16 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827833468 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_
token_digest.2827833468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3396673600
Short name T197
Test name
Test status
Simulation time 2131142154 ps
CPU time 17.62 seconds
Started Aug 24 08:41:56 PM UTC 24
Finished Aug 24 08:42:15 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396673600 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_tok
en_mux.3396673600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.3369234463
Short name T88
Test name
Test status
Simulation time 29528104 ps
CPU time 2.83 seconds
Started Aug 24 08:41:51 PM UTC 24
Finished Aug 24 08:41:55 PM UTC 24
Peak memory 236076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369234463 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3369234463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3548311466
Short name T360
Test name
Test status
Simulation time 534490843 ps
CPU time 17.25 seconds
Started Aug 24 08:41:53 PM UTC 24
Finished Aug 24 08:42:11 PM UTC 24
Peak memory 260696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548311466 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3548311466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.4239769054
Short name T869
Test name
Test status
Simulation time 35599389628 ps
CPU time 312.72 seconds
Started Aug 24 08:41:56 PM UTC 24
Finished Aug 24 08:47:13 PM UTC 24
Peak memory 295672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4239769054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 10.lc_ctrl_stress_all.4239769054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3616731202
Short name T111
Test name
Test status
Simulation time 16477228208 ps
CPU time 73.63 seconds
Started Aug 24 08:41:56 PM UTC 24
Finished Aug 24 08:43:12 PM UTC 24
Peak memory 283424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616731202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3616731202
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2785326883
Short name T316
Test name
Test status
Simulation time 46207406 ps
CPU time 1.41 seconds
Started Aug 24 08:41:51 PM UTC 24
Finished Aug 24 08:41:54 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785326883 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_volatile_unlock_smoke.2785326883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.3987658403
Short name T337
Test name
Test status
Simulation time 89154239 ps
CPU time 1.52 seconds
Started Aug 24 08:42:01 PM UTC 24
Finished Aug 24 08:42:04 PM UTC 24
Peak memory 218680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987658403 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3987658403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.743117220
Short name T196
Test name
Test status
Simulation time 916671253 ps
CPU time 14.39 seconds
Started Aug 24 08:41:59 PM UTC 24
Finished Aug 24 08:42:14 PM UTC 24
Peak memory 232444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743117220 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.743117220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2328496254
Short name T384
Test name
Test status
Simulation time 5794136652 ps
CPU time 21.62 seconds
Started Aug 24 08:42:00 PM UTC 24
Finished Aug 24 08:42:23 PM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328496254 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_acce
ss.2328496254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.1810255672
Short name T63
Test name
Test status
Simulation time 7060974256 ps
CPU time 67.01 seconds
Started Aug 24 08:42:00 PM UTC 24
Finished Aug 24 08:43:09 PM UTC 24
Peak memory 237968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810255672
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_errors.1810255672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.4126510882
Short name T341
Test name
Test status
Simulation time 270544937 ps
CPU time 3.86 seconds
Started Aug 24 08:42:00 PM UTC 24
Finished Aug 24 08:42:05 PM UTC 24
Peak memory 234432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126510882
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_jtag_prog_failure.4126510882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.690520219
Short name T346
Test name
Test status
Simulation time 919263838 ps
CPU time 6.01 seconds
Started Aug 24 08:41:59 PM UTC 24
Finished Aug 24 08:42:06 PM UTC 24
Peak memory 230156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690520219
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_smoke.690520219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.4119700567
Short name T474
Test name
Test status
Simulation time 4503918906 ps
CPU time 58.57 seconds
Started Aug 24 08:41:59 PM UTC 24
Finished Aug 24 08:42:59 PM UTC 24
Peak memory 283508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119700567
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_
ctrl_jtag_state_failure.4119700567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.769401132
Short name T377
Test name
Test status
Simulation time 1983897056 ps
CPU time 20.88 seconds
Started Aug 24 08:41:59 PM UTC 24
Finished Aug 24 08:42:21 PM UTC 24
Peak memory 260772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769401132
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.l
c_ctrl_jtag_state_post_trans.769401132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.841383497
Short name T344
Test name
Test status
Simulation time 105513382 ps
CPU time 5.9 seconds
Started Aug 24 08:41:59 PM UTC 24
Finished Aug 24 08:42:06 PM UTC 24
Peak memory 236472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841383497 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.841383497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.2266165314
Short name T374
Test name
Test status
Simulation time 332211552 ps
CPU time 15.92 seconds
Started Aug 24 08:42:01 PM UTC 24
Finished Aug 24 08:42:18 PM UTC 24
Peak memory 237360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266165314 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2266165314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2188964877
Short name T432
Test name
Test status
Simulation time 2149736325 ps
CPU time 38.33 seconds
Started Aug 24 08:42:01 PM UTC 24
Finished Aug 24 08:42:41 PM UTC 24
Peak memory 232196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188964877 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_
token_digest.2188964877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1022095922
Short name T193
Test name
Test status
Simulation time 672943621 ps
CPU time 15.49 seconds
Started Aug 24 08:42:01 PM UTC 24
Finished Aug 24 08:42:18 PM UTC 24
Peak memory 231936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022095922 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_tok
en_mux.1022095922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.16711511
Short name T192
Test name
Test status
Simulation time 265876822 ps
CPU time 14.18 seconds
Started Aug 24 08:41:59 PM UTC 24
Finished Aug 24 08:42:14 PM UTC 24
Peak memory 232452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16711511 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.16711511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1952092178
Short name T339
Test name
Test status
Simulation time 142758121 ps
CPU time 6.01 seconds
Started Aug 24 08:41:57 PM UTC 24
Finished Aug 24 08:42:04 PM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952092178 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1952092178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3009643596
Short name T436
Test name
Test status
Simulation time 817811842 ps
CPU time 41.51 seconds
Started Aug 24 08:41:59 PM UTC 24
Finished Aug 24 08:42:42 PM UTC 24
Peak memory 262844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009643596 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3009643596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.626925828
Short name T357
Test name
Test status
Simulation time 245777108 ps
CPU time 10.54 seconds
Started Aug 24 08:41:59 PM UTC 24
Finished Aug 24 08:42:10 PM UTC 24
Peak memory 262672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626925828 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.626925828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2042515131
Short name T870
Test name
Test status
Simulation time 9404634494 ps
CPU time 313.33 seconds
Started Aug 24 08:42:01 PM UTC 24
Finished Aug 24 08:47:19 PM UTC 24
Peak memory 279236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2042515131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 11.lc_ctrl_stress_all.2042515131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.755820836
Short name T326
Test name
Test status
Simulation time 22521947 ps
CPU time 1.39 seconds
Started Aug 24 08:41:57 PM UTC 24
Finished Aug 24 08:42:00 PM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755820836 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.lc_ctrl_volatile_unlock_smoke.755820836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.607948369
Short name T356
Test name
Test status
Simulation time 31869432 ps
CPU time 1.43 seconds
Started Aug 24 08:42:07 PM UTC 24
Finished Aug 24 08:42:09 PM UTC 24
Peak memory 216116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607948369 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.607948369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.3787675082
Short name T365
Test name
Test status
Simulation time 805413388 ps
CPU time 10.59 seconds
Started Aug 24 08:42:04 PM UTC 24
Finished Aug 24 08:42:15 PM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787675082 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3787675082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.562925148
Short name T198
Test name
Test status
Simulation time 422094615 ps
CPU time 8.27 seconds
Started Aug 24 08:42:06 PM UTC 24
Finished Aug 24 08:42:15 PM UTC 24
Peak memory 229992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562925148 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.562925148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.2716460156
Short name T446
Test name
Test status
Simulation time 1785963312 ps
CPU time 40.64 seconds
Started Aug 24 08:42:06 PM UTC 24
Finished Aug 24 08:42:48 PM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716460156
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_errors.2716460156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.564328879
Short name T390
Test name
Test status
Simulation time 3386497558 ps
CPU time 17.62 seconds
Started Aug 24 08:42:05 PM UTC 24
Finished Aug 24 08:42:23 PM UTC 24
Peak memory 232304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564328879
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_jtag_prog_failure.564328879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.2916403863
Short name T364
Test name
Test status
Simulation time 325963435 ps
CPU time 8.88 seconds
Started Aug 24 08:42:04 PM UTC 24
Finished Aug 24 08:42:13 PM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916403863
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_smoke.2916403863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.3929386808
Short name T599
Test name
Test status
Simulation time 3950900978 ps
CPU time 96.03 seconds
Started Aug 24 08:42:05 PM UTC 24
Finished Aug 24 08:43:43 PM UTC 24
Peak memory 287324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929386808
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_
ctrl_jtag_state_failure.3929386808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.60271916
Short name T375
Test name
Test status
Simulation time 300766938 ps
CPU time 14.15 seconds
Started Aug 24 08:42:05 PM UTC 24
Finished Aug 24 08:42:20 PM UTC 24
Peak memory 262676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60271916 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc
_ctrl_jtag_state_post_trans.60271916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2521367138
Short name T350
Test name
Test status
Simulation time 26005010 ps
CPU time 2.8 seconds
Started Aug 24 08:42:04 PM UTC 24
Finished Aug 24 08:42:07 PM UTC 24
Peak memory 234232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521367138 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2521367138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.1799274675
Short name T380
Test name
Test status
Simulation time 1491372751 ps
CPU time 14.87 seconds
Started Aug 24 08:42:06 PM UTC 24
Finished Aug 24 08:42:22 PM UTC 24
Peak memory 238156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799274675 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1799274675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.109535289
Short name T391
Test name
Test status
Simulation time 456592869 ps
CPU time 16.48 seconds
Started Aug 24 08:42:06 PM UTC 24
Finished Aug 24 08:42:24 PM UTC 24
Peak memory 237892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109535289 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_t
oken_digest.109535289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.1562272847
Short name T369
Test name
Test status
Simulation time 1168589910 ps
CPU time 11.5 seconds
Started Aug 24 08:42:06 PM UTC 24
Finished Aug 24 08:42:19 PM UTC 24
Peak memory 237968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562272847 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_tok
en_mux.1562272847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2797517990
Short name T338
Test name
Test status
Simulation time 78771391 ps
CPU time 1.99 seconds
Started Aug 24 08:42:01 PM UTC 24
Finished Aug 24 08:42:04 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797517990 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2797517990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.2641783711
Short name T441
Test name
Test status
Simulation time 263189592 ps
CPU time 38.67 seconds
Started Aug 24 08:42:02 PM UTC 24
Finished Aug 24 08:42:42 PM UTC 24
Peak memory 260584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641783711 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2641783711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.2757663149
Short name T373
Test name
Test status
Simulation time 257178561 ps
CPU time 14.13 seconds
Started Aug 24 08:42:02 PM UTC 24
Finished Aug 24 08:42:18 PM UTC 24
Peak memory 262692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757663149 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2757663149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2364571424
Short name T787
Test name
Test status
Simulation time 9107712883 ps
CPU time 152.8 seconds
Started Aug 24 08:42:07 PM UTC 24
Finished Aug 24 08:44:43 PM UTC 24
Peak memory 240360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2364571424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 12.lc_ctrl_stress_all.2364571424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.907633166
Short name T336
Test name
Test status
Simulation time 23042098 ps
CPU time 1.23 seconds
Started Aug 24 08:42:01 PM UTC 24
Finished Aug 24 08:42:04 PM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907633166 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.lc_ctrl_volatile_unlock_smoke.907633166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.3522184610
Short name T368
Test name
Test status
Simulation time 69571450 ps
CPU time 1.6 seconds
Started Aug 24 08:42:13 PM UTC 24
Finished Aug 24 08:42:16 PM UTC 24
Peak memory 218692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522184610 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3522184610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.3689545717
Short name T385
Test name
Test status
Simulation time 297693965 ps
CPU time 11.79 seconds
Started Aug 24 08:42:10 PM UTC 24
Finished Aug 24 08:42:23 PM UTC 24
Peak memory 232432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689545717 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3689545717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.2062913713
Short name T378
Test name
Test status
Simulation time 1595242314 ps
CPU time 7.67 seconds
Started Aug 24 08:42:12 PM UTC 24
Finished Aug 24 08:42:21 PM UTC 24
Peak memory 230104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062913713 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_acce
ss.2062913713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.1255702136
Short name T459
Test name
Test status
Simulation time 3437304974 ps
CPU time 40.83 seconds
Started Aug 24 08:42:12 PM UTC 24
Finished Aug 24 08:42:55 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255702136
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_errors.1255702136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.358253943
Short name T367
Test name
Test status
Simulation time 275684532 ps
CPU time 4.1 seconds
Started Aug 24 08:42:11 PM UTC 24
Finished Aug 24 08:42:16 PM UTC 24
Peak memory 232108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358253943
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_jtag_prog_failure.358253943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.4031698789
Short name T95
Test name
Test status
Simulation time 1632848785 ps
CPU time 10.81 seconds
Started Aug 24 08:42:10 PM UTC 24
Finished Aug 24 08:42:22 PM UTC 24
Peak memory 230048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031698789
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_smoke.4031698789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.2849071353
Short name T586
Test name
Test status
Simulation time 1615065964 ps
CPU time 84.71 seconds
Started Aug 24 08:42:11 PM UTC 24
Finished Aug 24 08:43:38 PM UTC 24
Peak memory 285288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849071353
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_
ctrl_jtag_state_failure.2849071353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3500120167
Short name T412
Test name
Test status
Simulation time 2864459291 ps
CPU time 22.16 seconds
Started Aug 24 08:42:11 PM UTC 24
Finished Aug 24 08:42:34 PM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500120167
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.
lc_ctrl_jtag_state_post_trans.3500120167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.4163908736
Short name T362
Test name
Test status
Simulation time 43420227 ps
CPU time 2.22 seconds
Started Aug 24 08:42:08 PM UTC 24
Finished Aug 24 08:42:12 PM UTC 24
Peak memory 234228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163908736 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4163908736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.3196222113
Short name T403
Test name
Test status
Simulation time 1344946133 ps
CPU time 16.49 seconds
Started Aug 24 08:42:12 PM UTC 24
Finished Aug 24 08:42:30 PM UTC 24
Peak memory 232020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196222113 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3196222113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3601886629
Short name T405
Test name
Test status
Simulation time 781310331 ps
CPU time 18.44 seconds
Started Aug 24 08:42:12 PM UTC 24
Finished Aug 24 08:42:32 PM UTC 24
Peak memory 237976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601886629 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_
token_digest.3601886629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3666328204
Short name T392
Test name
Test status
Simulation time 606132156 ps
CPU time 11.22 seconds
Started Aug 24 08:42:12 PM UTC 24
Finished Aug 24 08:42:25 PM UTC 24
Peak memory 232504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666328204 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_tok
en_mux.3666328204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.3344260308
Short name T379
Test name
Test status
Simulation time 2042877270 ps
CPU time 10.75 seconds
Started Aug 24 08:42:10 PM UTC 24
Finished Aug 24 08:42:22 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344260308 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3344260308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1430319155
Short name T361
Test name
Test status
Simulation time 15306936 ps
CPU time 2.08 seconds
Started Aug 24 08:42:08 PM UTC 24
Finished Aug 24 08:42:12 PM UTC 24
Peak memory 223552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430319155 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1430319155
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.147720748
Short name T461
Test name
Test status
Simulation time 341385490 ps
CPU time 44.74 seconds
Started Aug 24 08:42:08 PM UTC 24
Finished Aug 24 08:42:55 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147720748 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.147720748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2827404084
Short name T376
Test name
Test status
Simulation time 818200936 ps
CPU time 10.95 seconds
Started Aug 24 08:42:08 PM UTC 24
Finished Aug 24 08:42:21 PM UTC 24
Peak memory 258652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827404084 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2827404084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.4137289343
Short name T790
Test name
Test status
Simulation time 22247471950 ps
CPU time 148.01 seconds
Started Aug 24 08:42:12 PM UTC 24
Finished Aug 24 08:44:43 PM UTC 24
Peak memory 295684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4137289343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 13.lc_ctrl_stress_all.4137289343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1439547673
Short name T185
Test name
Test status
Simulation time 2387541500 ps
CPU time 96.21 seconds
Started Aug 24 08:42:12 PM UTC 24
Finished Aug 24 08:43:51 PM UTC 24
Peak memory 281440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439547673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1439547673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2278672905
Short name T359
Test name
Test status
Simulation time 42815745 ps
CPU time 1.17 seconds
Started Aug 24 08:42:08 PM UTC 24
Finished Aug 24 08:42:11 PM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278672905 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_volatile_unlock_smoke.2278672905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.4111322518
Short name T382
Test name
Test status
Simulation time 69798891 ps
CPU time 1.26 seconds
Started Aug 24 08:42:20 PM UTC 24
Finished Aug 24 08:42:22 PM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111322518 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4111322518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.1802119593
Short name T404
Test name
Test status
Simulation time 367575394 ps
CPU time 13.86 seconds
Started Aug 24 08:42:15 PM UTC 24
Finished Aug 24 08:42:30 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802119593 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1802119593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1994833380
Short name T406
Test name
Test status
Simulation time 756696932 ps
CPU time 13.54 seconds
Started Aug 24 08:42:17 PM UTC 24
Finished Aug 24 08:42:32 PM UTC 24
Peak memory 229804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994833380 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_acce
ss.1994833380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.1320271988
Short name T636
Test name
Test status
Simulation time 10852573665 ps
CPU time 93.9 seconds
Started Aug 24 08:42:16 PM UTC 24
Finished Aug 24 08:43:53 PM UTC 24
Peak memory 237904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320271988
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_errors.1320271988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.342302572
Short name T407
Test name
Test status
Simulation time 726053112 ps
CPU time 14.71 seconds
Started Aug 24 08:42:16 PM UTC 24
Finished Aug 24 08:42:32 PM UTC 24
Peak memory 232068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342302572
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_jtag_prog_failure.342302572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.4115420412
Short name T389
Test name
Test status
Simulation time 605829138 ps
CPU time 5.82 seconds
Started Aug 24 08:42:16 PM UTC 24
Finished Aug 24 08:42:23 PM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115420412
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_smoke.4115420412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.627402501
Short name T462
Test name
Test status
Simulation time 8113851026 ps
CPU time 37.06 seconds
Started Aug 24 08:42:16 PM UTC 24
Finished Aug 24 08:42:55 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627402501
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_jtag_state_failure.627402501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.2779112519
Short name T408
Test name
Test status
Simulation time 1363767268 ps
CPU time 14.95 seconds
Started Aug 24 08:42:16 PM UTC 24
Finished Aug 24 08:42:33 PM UTC 24
Peak memory 236496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779112519
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.
lc_ctrl_jtag_state_post_trans.2779112519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.1313374881
Short name T194
Test name
Test status
Simulation time 152323275 ps
CPU time 4.93 seconds
Started Aug 24 08:42:15 PM UTC 24
Finished Aug 24 08:42:21 PM UTC 24
Peak memory 230208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313374881 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1313374881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1683311937
Short name T411
Test name
Test status
Simulation time 245760172 ps
CPU time 14.36 seconds
Started Aug 24 08:42:19 PM UTC 24
Finished Aug 24 08:42:34 PM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683311937 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1683311937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.4142640896
Short name T428
Test name
Test status
Simulation time 1351054311 ps
CPU time 19.44 seconds
Started Aug 24 08:42:19 PM UTC 24
Finished Aug 24 08:42:39 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142640896 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_
token_digest.4142640896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3786784767
Short name T433
Test name
Test status
Simulation time 832757265 ps
CPU time 21.25 seconds
Started Aug 24 08:42:19 PM UTC 24
Finished Aug 24 08:42:41 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786784767 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_tok
en_mux.3786784767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.3822480978
Short name T220
Test name
Test status
Simulation time 2247876063 ps
CPU time 26.06 seconds
Started Aug 24 08:42:16 PM UTC 24
Finished Aug 24 08:42:44 PM UTC 24
Peak memory 232224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822480978 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3822480978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.2796961434
Short name T334
Test name
Test status
Simulation time 146575274 ps
CPU time 3.94 seconds
Started Aug 24 08:42:15 PM UTC 24
Finished Aug 24 08:42:20 PM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796961434 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2796961434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.236316228
Short name T117
Test name
Test status
Simulation time 4106124669 ps
CPU time 29.63 seconds
Started Aug 24 08:42:15 PM UTC 24
Finished Aug 24 08:42:46 PM UTC 24
Peak memory 262788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236316228 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.236316228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.3484404626
Short name T398
Test name
Test status
Simulation time 271435822 ps
CPU time 10.73 seconds
Started Aug 24 08:42:15 PM UTC 24
Finished Aug 24 08:42:27 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484404626 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3484404626
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.3104662528
Short name T622
Test name
Test status
Simulation time 4034964057 ps
CPU time 87.81 seconds
Started Aug 24 08:42:19 PM UTC 24
Finished Aug 24 08:43:48 PM UTC 24
Peak memory 260836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3104662528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 14.lc_ctrl_stress_all.3104662528
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2480273813
Short name T186
Test name
Test status
Simulation time 2955935940 ps
CPU time 115.89 seconds
Started Aug 24 08:42:20 PM UTC 24
Finished Aug 24 08:44:18 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480273813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2480273813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.968248004
Short name T371
Test name
Test status
Simulation time 20782047 ps
CPU time 1.36 seconds
Started Aug 24 08:42:15 PM UTC 24
Finished Aug 24 08:42:17 PM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968248004 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.lc_ctrl_volatile_unlock_smoke.968248004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2988624788
Short name T397
Test name
Test status
Simulation time 33002750 ps
CPU time 1.71 seconds
Started Aug 24 08:42:24 PM UTC 24
Finished Aug 24 08:42:26 PM UTC 24
Peak memory 218812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988624788 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2988624788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2078304868
Short name T431
Test name
Test status
Simulation time 1456390928 ps
CPU time 17.41 seconds
Started Aug 24 08:42:22 PM UTC 24
Finished Aug 24 08:42:41 PM UTC 24
Peak memory 231212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078304868 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2078304868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3322445134
Short name T402
Test name
Test status
Simulation time 1111867431 ps
CPU time 4.88 seconds
Started Aug 24 08:42:24 PM UTC 24
Finished Aug 24 08:42:29 PM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322445134 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_acce
ss.3322445134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.140911622
Short name T571
Test name
Test status
Simulation time 2824654442 ps
CPU time 65.8 seconds
Started Aug 24 08:42:24 PM UTC 24
Finished Aug 24 08:43:31 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140911622
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_errors.140911622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1899541763
Short name T421
Test name
Test status
Simulation time 968182932 ps
CPU time 12.08 seconds
Started Aug 24 08:42:24 PM UTC 24
Finished Aug 24 08:42:37 PM UTC 24
Peak memory 236492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899541763
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_jtag_prog_failure.1899541763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.1193616579
Short name T413
Test name
Test status
Simulation time 3749178022 ps
CPU time 11.19 seconds
Started Aug 24 08:42:22 PM UTC 24
Finished Aug 24 08:42:35 PM UTC 24
Peak memory 230040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193616579
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_smoke.1193616579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2611962619
Short name T507
Test name
Test status
Simulation time 4565459082 ps
CPU time 45.74 seconds
Started Aug 24 08:42:22 PM UTC 24
Finished Aug 24 08:43:10 PM UTC 24
Peak memory 281444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611962619
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_
ctrl_jtag_state_failure.2611962619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.996332433
Short name T438
Test name
Test status
Simulation time 3601707053 ps
CPU time 18.22 seconds
Started Aug 24 08:42:22 PM UTC 24
Finished Aug 24 08:42:42 PM UTC 24
Peak memory 232116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996332433
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.l
c_ctrl_jtag_state_post_trans.996332433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.751428388
Short name T396
Test name
Test status
Simulation time 72503578 ps
CPU time 2.94 seconds
Started Aug 24 08:42:22 PM UTC 24
Finished Aug 24 08:42:26 PM UTC 24
Peak memory 231796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751428388 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.751428388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.1029635420
Short name T450
Test name
Test status
Simulation time 1927863205 ps
CPU time 23.86 seconds
Started Aug 24 08:42:24 PM UTC 24
Finished Aug 24 08:42:49 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029635420 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1029635420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.2696933829
Short name T415
Test name
Test status
Simulation time 651234443 ps
CPU time 11.01 seconds
Started Aug 24 08:42:24 PM UTC 24
Finished Aug 24 08:42:36 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696933829 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_
token_digest.2696933829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.1773756482
Short name T423
Test name
Test status
Simulation time 261565725 ps
CPU time 12.09 seconds
Started Aug 24 08:42:24 PM UTC 24
Finished Aug 24 08:42:37 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773756482 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_tok
en_mux.1773756482
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.692260847
Short name T416
Test name
Test status
Simulation time 471574507 ps
CPU time 12.4 seconds
Started Aug 24 08:42:22 PM UTC 24
Finished Aug 24 08:42:36 PM UTC 24
Peak memory 231424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692260847 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.692260847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.96310757
Short name T395
Test name
Test status
Simulation time 54100830 ps
CPU time 4.16 seconds
Started Aug 24 08:42:20 PM UTC 24
Finished Aug 24 08:42:25 PM UTC 24
Peak memory 226020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96310757 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.96310757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.1768088486
Short name T500
Test name
Test status
Simulation time 245670674 ps
CPU time 45.55 seconds
Started Aug 24 08:42:21 PM UTC 24
Finished Aug 24 08:43:08 PM UTC 24
Peak memory 262788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768088486 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1768088486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.280627845
Short name T409
Test name
Test status
Simulation time 56693662 ps
CPU time 10.17 seconds
Started Aug 24 08:42:22 PM UTC 24
Finished Aug 24 08:42:34 PM UTC 24
Peak memory 260704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280627845 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.280627845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3793171663
Short name T758
Test name
Test status
Simulation time 52346091387 ps
CPU time 126.79 seconds
Started Aug 24 08:42:24 PM UTC 24
Finished Aug 24 08:44:33 PM UTC 24
Peak memory 248476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3793171663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 15.lc_ctrl_stress_all.3793171663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2776382378
Short name T388
Test name
Test status
Simulation time 14708098 ps
CPU time 1.33 seconds
Started Aug 24 08:42:21 PM UTC 24
Finished Aug 24 08:42:23 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776382378 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_volatile_unlock_smoke.2776382378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.1157931065
Short name T410
Test name
Test status
Simulation time 13734958 ps
CPU time 1.18 seconds
Started Aug 24 08:42:32 PM UTC 24
Finished Aug 24 08:42:34 PM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157931065 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1157931065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.3164261427
Short name T439
Test name
Test status
Simulation time 1455339755 ps
CPU time 15.67 seconds
Started Aug 24 08:42:25 PM UTC 24
Finished Aug 24 08:42:42 PM UTC 24
Peak memory 230532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164261427 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3164261427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.1987222222
Short name T219
Test name
Test status
Simulation time 1935128313 ps
CPU time 14.31 seconds
Started Aug 24 08:42:28 PM UTC 24
Finished Aug 24 08:42:44 PM UTC 24
Peak memory 229848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987222222 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_acce
ss.1987222222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.4052064587
Short name T560
Test name
Test status
Simulation time 6895847859 ps
CPU time 59.73 seconds
Started Aug 24 08:42:27 PM UTC 24
Finished Aug 24 08:43:29 PM UTC 24
Peak memory 237968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052064587
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_errors.4052064587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.2067621720
Short name T419
Test name
Test status
Simulation time 1216656621 ps
CPU time 8.01 seconds
Started Aug 24 08:42:27 PM UTC 24
Finished Aug 24 08:42:36 PM UTC 24
Peak memory 236304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067621720
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_jtag_prog_failure.2067621720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2334021454
Short name T96
Test name
Test status
Simulation time 124810216 ps
CPU time 3.45 seconds
Started Aug 24 08:42:26 PM UTC 24
Finished Aug 24 08:42:31 PM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334021454
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_smoke.2334021454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.2796338200
Short name T561
Test name
Test status
Simulation time 1577364722 ps
CPU time 60.97 seconds
Started Aug 24 08:42:26 PM UTC 24
Finished Aug 24 08:43:29 PM UTC 24
Peak memory 285208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796338200
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_
ctrl_jtag_state_failure.2796338200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.2732720130
Short name T443
Test name
Test status
Simulation time 2502926372 ps
CPU time 18.59 seconds
Started Aug 24 08:42:27 PM UTC 24
Finished Aug 24 08:42:47 PM UTC 24
Peak memory 262748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732720130
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.
lc_ctrl_jtag_state_post_trans.2732720130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.4183824094
Short name T401
Test name
Test status
Simulation time 97307300 ps
CPU time 2.97 seconds
Started Aug 24 08:42:25 PM UTC 24
Finished Aug 24 08:42:29 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183824094 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.4183824094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.2141278697
Short name T470
Test name
Test status
Simulation time 1292397841 ps
CPU time 28.34 seconds
Started Aug 24 08:42:28 PM UTC 24
Finished Aug 24 08:42:58 PM UTC 24
Peak memory 232372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141278697 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2141278697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2526422869
Short name T451
Test name
Test status
Simulation time 432681045 ps
CPU time 17.29 seconds
Started Aug 24 08:42:31 PM UTC 24
Finished Aug 24 08:42:49 PM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526422869 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_
token_digest.2526422869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.4023874445
Short name T442
Test name
Test status
Simulation time 344479410 ps
CPU time 16.4 seconds
Started Aug 24 08:42:29 PM UTC 24
Finished Aug 24 08:42:47 PM UTC 24
Peak memory 237904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023874445 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_tok
en_mux.4023874445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.252631917
Short name T426
Test name
Test status
Simulation time 625642972 ps
CPU time 10.85 seconds
Started Aug 24 08:42:26 PM UTC 24
Finished Aug 24 08:42:38 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252631917 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.252631917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.1989709850
Short name T400
Test name
Test status
Simulation time 14450379 ps
CPU time 1.52 seconds
Started Aug 24 08:42:25 PM UTC 24
Finished Aug 24 08:42:28 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989709850 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1989709850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3196089996
Short name T502
Test name
Test status
Simulation time 868095493 ps
CPU time 41.81 seconds
Started Aug 24 08:42:25 PM UTC 24
Finished Aug 24 08:43:08 PM UTC 24
Peak memory 258724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196089996 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3196089996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1843051564
Short name T417
Test name
Test status
Simulation time 232304400 ps
CPU time 9.84 seconds
Started Aug 24 08:42:25 PM UTC 24
Finished Aug 24 08:42:36 PM UTC 24
Peak memory 260696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843051564 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1843051564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.768529752
Short name T527
Test name
Test status
Simulation time 5881164851 ps
CPU time 63.37 seconds
Started Aug 24 08:42:31 PM UTC 24
Finished Aug 24 08:43:36 PM UTC 24
Peak memory 262812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=768529752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.lc_ctrl_stress_all.768529752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2868620443
Short name T399
Test name
Test status
Simulation time 14949548 ps
CPU time 1.27 seconds
Started Aug 24 08:42:25 PM UTC 24
Finished Aug 24 08:42:27 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868620443 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_volatile_unlock_smoke.2868620443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.2940570802
Short name T430
Test name
Test status
Simulation time 18094655 ps
CPU time 1.68 seconds
Started Aug 24 08:42:38 PM UTC 24
Finished Aug 24 08:42:41 PM UTC 24
Peak memory 218752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940570802 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2940570802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.4106614901
Short name T481
Test name
Test status
Simulation time 749273930 ps
CPU time 25.5 seconds
Started Aug 24 08:42:35 PM UTC 24
Finished Aug 24 08:43:02 PM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106614901 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4106614901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.4044709778
Short name T437
Test name
Test status
Simulation time 364905986 ps
CPU time 2.91 seconds
Started Aug 24 08:42:38 PM UTC 24
Finished Aug 24 08:42:42 PM UTC 24
Peak memory 230096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044709778 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_acce
ss.4044709778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3626146923
Short name T525
Test name
Test status
Simulation time 3987211922 ps
CPU time 38.88 seconds
Started Aug 24 08:42:38 PM UTC 24
Finished Aug 24 08:43:18 PM UTC 24
Peak memory 231840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626146923
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_errors.3626146923
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.3680791938
Short name T221
Test name
Test status
Simulation time 97745634 ps
CPU time 5.32 seconds
Started Aug 24 08:42:38 PM UTC 24
Finished Aug 24 08:42:44 PM UTC 24
Peak memory 231724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680791938
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_jtag_prog_failure.3680791938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.454140342
Short name T434
Test name
Test status
Simulation time 1284080963 ps
CPU time 4.88 seconds
Started Aug 24 08:42:35 PM UTC 24
Finished Aug 24 08:42:41 PM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454140342
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_smoke.454140342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.3370797650
Short name T616
Test name
Test status
Simulation time 1696417496 ps
CPU time 68.74 seconds
Started Aug 24 08:42:36 PM UTC 24
Finished Aug 24 08:43:47 PM UTC 24
Peak memory 285476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370797650
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_
ctrl_jtag_state_failure.3370797650
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.860272757
Short name T482
Test name
Test status
Simulation time 2511813949 ps
CPU time 24.98 seconds
Started Aug 24 08:42:36 PM UTC 24
Finished Aug 24 08:43:02 PM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860272757
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.l
c_ctrl_jtag_state_post_trans.860272757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.3262555258
Short name T429
Test name
Test status
Simulation time 72134677 ps
CPU time 3.84 seconds
Started Aug 24 08:42:35 PM UTC 24
Finished Aug 24 08:42:40 PM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262555258 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3262555258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.1993872749
Short name T476
Test name
Test status
Simulation time 487671394 ps
CPU time 20.36 seconds
Started Aug 24 08:42:38 PM UTC 24
Finished Aug 24 08:42:59 PM UTC 24
Peak memory 237892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993872749 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1993872749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.240589119
Short name T468
Test name
Test status
Simulation time 944983494 ps
CPU time 18.25 seconds
Started Aug 24 08:42:38 PM UTC 24
Finished Aug 24 08:42:57 PM UTC 24
Peak memory 230200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240589119 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_t
oken_digest.240589119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.2523837781
Short name T455
Test name
Test status
Simulation time 465514552 ps
CPU time 12.97 seconds
Started Aug 24 08:42:38 PM UTC 24
Finished Aug 24 08:42:52 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523837781 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_tok
en_mux.2523837781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.3272339816
Short name T454
Test name
Test status
Simulation time 1132032864 ps
CPU time 15.43 seconds
Started Aug 24 08:42:35 PM UTC 24
Finished Aug 24 08:42:52 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272339816 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3272339816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2066322670
Short name T424
Test name
Test status
Simulation time 71581145 ps
CPU time 3.2 seconds
Started Aug 24 08:42:33 PM UTC 24
Finished Aug 24 08:42:37 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066322670 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2066322670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.783315582
Short name T497
Test name
Test status
Simulation time 453125560 ps
CPU time 32.32 seconds
Started Aug 24 08:42:33 PM UTC 24
Finished Aug 24 08:43:07 PM UTC 24
Peak memory 258920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783315582 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.783315582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2761378200
Short name T225
Test name
Test status
Simulation time 1784190605 ps
CPU time 10.77 seconds
Started Aug 24 08:42:34 PM UTC 24
Finished Aug 24 08:42:46 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761378200 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2761378200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.3073799998
Short name T858
Test name
Test status
Simulation time 54803879102 ps
CPU time 172.92 seconds
Started Aug 24 08:42:38 PM UTC 24
Finished Aug 24 08:45:34 PM UTC 24
Peak memory 295660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3073799998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 17.lc_ctrl_stress_all.3073799998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.823605292
Short name T414
Test name
Test status
Simulation time 14861518 ps
CPU time 1.52 seconds
Started Aug 24 08:42:33 PM UTC 24
Finished Aug 24 08:42:35 PM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823605292 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.lc_ctrl_volatile_unlock_smoke.823605292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.4203246762
Short name T444
Test name
Test status
Simulation time 125170438 ps
CPU time 1.72 seconds
Started Aug 24 08:42:44 PM UTC 24
Finished Aug 24 08:42:47 PM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203246762 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4203246762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.972937911
Short name T473
Test name
Test status
Simulation time 378846857 ps
CPU time 15.99 seconds
Started Aug 24 08:42:41 PM UTC 24
Finished Aug 24 08:42:58 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972937911 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.972937911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.1206944083
Short name T422
Test name
Test status
Simulation time 44145378 ps
CPU time 1.92 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:42:46 PM UTC 24
Peak memory 229576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206944083 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_acce
ss.1206944083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3556732738
Short name T539
Test name
Test status
Simulation time 2993661110 ps
CPU time 37.91 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:43:23 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556732738
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_errors.3556732738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.1370857158
Short name T449
Test name
Test status
Simulation time 1079440396 ps
CPU time 4.49 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:42:49 PM UTC 24
Peak memory 234432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370857158
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_jtag_prog_failure.1370857158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.2109051614
Short name T464
Test name
Test status
Simulation time 434725928 ps
CPU time 11.04 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:42:55 PM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109051614
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_smoke.2109051614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.4097552285
Short name T605
Test name
Test status
Simulation time 4934596624 ps
CPU time 59.7 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:43:44 PM UTC 24
Peak memory 282956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097552285
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_
ctrl_jtag_state_failure.4097552285
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.2741950367
Short name T495
Test name
Test status
Simulation time 428663383 ps
CPU time 21.83 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:43:06 PM UTC 24
Peak memory 262684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741950367
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.
lc_ctrl_jtag_state_post_trans.2741950367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1622384520
Short name T448
Test name
Test status
Simulation time 363562407 ps
CPU time 5.91 seconds
Started Aug 24 08:42:41 PM UTC 24
Finished Aug 24 08:42:48 PM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622384520 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1622384520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.207772115
Short name T475
Test name
Test status
Simulation time 1171443991 ps
CPU time 14.67 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:42:59 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207772115 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.207772115
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3486269924
Short name T491
Test name
Test status
Simulation time 1491354991 ps
CPU time 18.6 seconds
Started Aug 24 08:42:44 PM UTC 24
Finished Aug 24 08:43:04 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486269924 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_
token_digest.3486269924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.189316773
Short name T469
Test name
Test status
Simulation time 2604643865 ps
CPU time 13.59 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:42:58 PM UTC 24
Peak memory 232232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189316773 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_toke
n_mux.189316773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.1811615465
Short name T463
Test name
Test status
Simulation time 533630946 ps
CPU time 10.92 seconds
Started Aug 24 08:42:43 PM UTC 24
Finished Aug 24 08:42:55 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811615465 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1811615465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1869170135
Short name T218
Test name
Test status
Simulation time 202108424 ps
CPU time 3.28 seconds
Started Aug 24 08:42:39 PM UTC 24
Finished Aug 24 08:42:43 PM UTC 24
Peak memory 229936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869170135 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1869170135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.3969258916
Short name T492
Test name
Test status
Simulation time 578467790 ps
CPU time 24.51 seconds
Started Aug 24 08:42:39 PM UTC 24
Finished Aug 24 08:43:05 PM UTC 24
Peak memory 262896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969258916 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3969258916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2067805990
Short name T453
Test name
Test status
Simulation time 210086344 ps
CPU time 9.78 seconds
Started Aug 24 08:42:40 PM UTC 24
Finished Aug 24 08:42:51 PM UTC 24
Peak memory 262656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067805990 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2067805990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2424786334
Short name T821
Test name
Test status
Simulation time 3502073993 ps
CPU time 126.82 seconds
Started Aug 24 08:42:44 PM UTC 24
Finished Aug 24 08:44:54 PM UTC 24
Peak memory 262800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2424786334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 18.lc_ctrl_stress_all.2424786334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2091672863
Short name T435
Test name
Test status
Simulation time 43556048 ps
CPU time 1.34 seconds
Started Aug 24 08:42:39 PM UTC 24
Finished Aug 24 08:42:41 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091672863 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_volatile_unlock_smoke.2091672863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.2982981770
Short name T456
Test name
Test status
Simulation time 197832360 ps
CPU time 1.57 seconds
Started Aug 24 08:42:50 PM UTC 24
Finished Aug 24 08:42:53 PM UTC 24
Peak memory 218916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982981770 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2982981770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.507213161
Short name T206
Test name
Test status
Simulation time 1805172009 ps
CPU time 23.69 seconds
Started Aug 24 08:42:47 PM UTC 24
Finished Aug 24 08:43:12 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507213161 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.507213161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1903163114
Short name T465
Test name
Test status
Simulation time 1178045319 ps
CPU time 6.35 seconds
Started Aug 24 08:42:48 PM UTC 24
Finished Aug 24 08:42:56 PM UTC 24
Peak memory 230112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903163114 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_acce
ss.1903163114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.469909692
Short name T670
Test name
Test status
Simulation time 1995388934 ps
CPU time 70.86 seconds
Started Aug 24 08:42:48 PM UTC 24
Finished Aug 24 08:44:01 PM UTC 24
Peak memory 230596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469909692
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_errors.469909692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.3437471387
Short name T501
Test name
Test status
Simulation time 862286382 ps
CPU time 18.68 seconds
Started Aug 24 08:42:48 PM UTC 24
Finished Aug 24 08:43:08 PM UTC 24
Peak memory 235960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437471387
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_jtag_prog_failure.3437471387
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.3854062731
Short name T472
Test name
Test status
Simulation time 1141359209 ps
CPU time 10.12 seconds
Started Aug 24 08:42:47 PM UTC 24
Finished Aug 24 08:42:58 PM UTC 24
Peak memory 230204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854062731
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_smoke.3854062731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.4108648459
Short name T641
Test name
Test status
Simulation time 5137603415 ps
CPU time 65.53 seconds
Started Aug 24 08:42:47 PM UTC 24
Finished Aug 24 08:43:54 PM UTC 24
Peak memory 289368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108648459
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_
ctrl_jtag_state_failure.4108648459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.4223714788
Short name T208
Test name
Test status
Simulation time 357438286 ps
CPU time 22.39 seconds
Started Aug 24 08:42:48 PM UTC 24
Finished Aug 24 08:43:12 PM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223714788
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.
lc_ctrl_jtag_state_post_trans.4223714788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3785635386
Short name T452
Test name
Test status
Simulation time 70947331 ps
CPU time 2.98 seconds
Started Aug 24 08:42:46 PM UTC 24
Finished Aug 24 08:42:50 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785635386 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3785635386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2924602973
Short name T494
Test name
Test status
Simulation time 370536510 ps
CPU time 15.94 seconds
Started Aug 24 08:42:48 PM UTC 24
Finished Aug 24 08:43:05 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924602973 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2924602973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.867563370
Short name T489
Test name
Test status
Simulation time 1011155803 ps
CPU time 12.25 seconds
Started Aug 24 08:42:50 PM UTC 24
Finished Aug 24 08:43:03 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867563370 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_t
oken_digest.867563370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.560165431
Short name T479
Test name
Test status
Simulation time 740721009 ps
CPU time 10.92 seconds
Started Aug 24 08:42:48 PM UTC 24
Finished Aug 24 08:43:01 PM UTC 24
Peak memory 230204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560165431 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_toke
n_mux.560165431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.2491844729
Short name T467
Test name
Test status
Simulation time 205201667 ps
CPU time 8.23 seconds
Started Aug 24 08:42:47 PM UTC 24
Finished Aug 24 08:42:56 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491844729 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2491844729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.4021605606
Short name T445
Test name
Test status
Simulation time 117797649 ps
CPU time 1.99 seconds
Started Aug 24 08:42:44 PM UTC 24
Finished Aug 24 08:42:47 PM UTC 24
Peak memory 228852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021605606 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.4021605606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.2009560647
Short name T569
Test name
Test status
Simulation time 251564064 ps
CPU time 43.36 seconds
Started Aug 24 08:42:46 PM UTC 24
Finished Aug 24 08:43:31 PM UTC 24
Peak memory 258796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009560647 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2009560647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.244387651
Short name T466
Test name
Test status
Simulation time 176265061 ps
CPU time 9.22 seconds
Started Aug 24 08:42:46 PM UTC 24
Finished Aug 24 08:42:56 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244387651 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.244387651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.3877378148
Short name T822
Test name
Test status
Simulation time 12963324526 ps
CPU time 121.43 seconds
Started Aug 24 08:42:50 PM UTC 24
Finished Aug 24 08:44:54 PM UTC 24
Peak memory 267004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3877378148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 19.lc_ctrl_stress_all.3877378148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3719931005
Short name T226
Test name
Test status
Simulation time 16410539 ps
CPU time 1.38 seconds
Started Aug 24 08:42:44 PM UTC 24
Finished Aug 24 08:42:47 PM UTC 24
Peak memory 228852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719931005 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_volatile_unlock_smoke.3719931005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.142150555
Short name T1
Test name
Test status
Simulation time 36247814 ps
CPU time 0.89 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:17 PM UTC 24
Peak memory 218164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142150555 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.142150555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.779130432
Short name T21
Test name
Test status
Simulation time 372450336 ps
CPU time 11.95 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:28 PM UTC 24
Peak memory 230204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779130432 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.779130432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.7119632
Short name T12
Test name
Test status
Simulation time 438303602 ps
CPU time 12.25 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:29 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7119632 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.7119632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.501267292
Short name T65
Test name
Test status
Simulation time 4749372639 ps
CPU time 27.12 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:44 PM UTC 24
Peak memory 238100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501267292
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_errors.501267292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1984324283
Short name T239
Test name
Test status
Simulation time 13045320468 ps
CPU time 31.38 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:48 PM UTC 24
Peak memory 230096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984324283 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_pri
ority.1984324283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1971240045
Short name T182
Test name
Test status
Simulation time 1939828997 ps
CPU time 19.7 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:37 PM UTC 24
Peak memory 230048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971240045
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l
c_ctrl_jtag_regwen_during_op.1971240045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1355125949
Short name T267
Test name
Test status
Simulation time 6726839187 ps
CPU time 21.9 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:39 PM UTC 24
Peak memory 238152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355125949
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l
c_ctrl_jtag_state_post_trans.1355125949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.3763019348
Short name T28
Test name
Test status
Simulation time 80406237 ps
CPU time 4.21 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:21 PM UTC 24
Peak memory 232048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763019348 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3763019348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1346869238
Short name T39
Test name
Test status
Simulation time 415064694 ps
CPU time 10.11 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:27 PM UTC 24
Peak memory 231680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346869238 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_t
oken_digest.1346869238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2982058018
Short name T59
Test name
Test status
Simulation time 939842292 ps
CPU time 11.53 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:28 PM UTC 24
Peak memory 232080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982058018 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_toke
n_mux.2982058018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3099229287
Short name T34
Test name
Test status
Simulation time 1040727762 ps
CPU time 10.1 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:27 PM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099229287 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3099229287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1218809189
Short name T27
Test name
Test status
Simulation time 51342502 ps
CPU time 3.09 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:19 PM UTC 24
Peak memory 234444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218809189 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1218809189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.623298386
Short name T56
Test name
Test status
Simulation time 165754972 ps
CPU time 10.68 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:27 PM UTC 24
Peak memory 262732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623298386 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.623298386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1113558708
Short name T521
Test name
Test status
Simulation time 33822704443 ps
CPU time 119.43 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:43:17 PM UTC 24
Peak memory 260304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1113558708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 2.lc_ctrl_stress_all.1113558708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.219922837
Short name T2
Test name
Test status
Simulation time 63646057 ps
CPU time 1.02 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:17 PM UTC 24
Peak memory 221840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219922837 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2
.lc_ctrl_volatile_unlock_smoke.219922837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2818541892
Short name T478
Test name
Test status
Simulation time 43944328 ps
CPU time 1.37 seconds
Started Aug 24 08:42:57 PM UTC 24
Finished Aug 24 08:43:00 PM UTC 24
Peak memory 218912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818541892 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2818541892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3031564536
Short name T209
Test name
Test status
Simulation time 429819444 ps
CPU time 18.43 seconds
Started Aug 24 08:42:53 PM UTC 24
Finished Aug 24 08:43:13 PM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031564536 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3031564536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3038347481
Short name T522
Test name
Test status
Simulation time 1428571298 ps
CPU time 21.73 seconds
Started Aug 24 08:42:54 PM UTC 24
Finished Aug 24 08:43:18 PM UTC 24
Peak memory 229848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038347481 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_acce
ss.3038347481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.1461135808
Short name T471
Test name
Test status
Simulation time 338899855 ps
CPU time 3.8 seconds
Started Aug 24 08:42:53 PM UTC 24
Finished Aug 24 08:42:58 PM UTC 24
Peak memory 236544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461135808 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1461135808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1546099117
Short name T531
Test name
Test status
Simulation time 1373543191 ps
CPU time 22.05 seconds
Started Aug 24 08:42:56 PM UTC 24
Finished Aug 24 08:43:20 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546099117 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1546099117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1781981819
Short name T511
Test name
Test status
Simulation time 1085809974 ps
CPU time 14.89 seconds
Started Aug 24 08:42:56 PM UTC 24
Finished Aug 24 08:43:12 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781981819 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_
token_digest.1781981819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1156316418
Short name T496
Test name
Test status
Simulation time 1978829309 ps
CPU time 9.05 seconds
Started Aug 24 08:42:56 PM UTC 24
Finished Aug 24 08:43:06 PM UTC 24
Peak memory 237892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156316418 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_tok
en_mux.1156316418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1691889375
Short name T510
Test name
Test status
Simulation time 373607387 ps
CPU time 15.22 seconds
Started Aug 24 08:42:54 PM UTC 24
Finished Aug 24 08:43:11 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691889375 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1691889375
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.2694185583
Short name T97
Test name
Test status
Simulation time 149987823 ps
CPU time 2.9 seconds
Started Aug 24 08:42:50 PM UTC 24
Finished Aug 24 08:42:54 PM UTC 24
Peak memory 229928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694185583 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2694185583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.1859509538
Short name T538
Test name
Test status
Simulation time 1712987874 ps
CPU time 30.3 seconds
Started Aug 24 08:42:51 PM UTC 24
Finished Aug 24 08:43:22 PM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859509538 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1859509538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3074115263
Short name T488
Test name
Test status
Simulation time 516337244 ps
CPU time 10.39 seconds
Started Aug 24 08:42:52 PM UTC 24
Finished Aug 24 08:43:03 PM UTC 24
Peak memory 262760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074115263 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3074115263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.1987850951
Short name T662
Test name
Test status
Simulation time 1492370006 ps
CPU time 61.37 seconds
Started Aug 24 08:42:56 PM UTC 24
Finished Aug 24 08:43:59 PM UTC 24
Peak memory 281244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1987850951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 20.lc_ctrl_stress_all.1987850951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.790353120
Short name T457
Test name
Test status
Simulation time 20653496 ps
CPU time 1.15 seconds
Started Aug 24 08:42:51 PM UTC 24
Finished Aug 24 08:42:53 PM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790353120 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.lc_ctrl_volatile_unlock_smoke.790353120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2588868754
Short name T484
Test name
Test status
Simulation time 18369456 ps
CPU time 1.37 seconds
Started Aug 24 08:43:00 PM UTC 24
Finished Aug 24 08:43:02 PM UTC 24
Peak memory 218988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588868754 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2588868754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.2269724021
Short name T519
Test name
Test status
Simulation time 436365937 ps
CPU time 17.75 seconds
Started Aug 24 08:42:57 PM UTC 24
Finished Aug 24 08:43:16 PM UTC 24
Peak memory 238216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269724021 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2269724021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2350241093
Short name T505
Test name
Test status
Simulation time 528730162 ps
CPU time 9.35 seconds
Started Aug 24 08:42:58 PM UTC 24
Finished Aug 24 08:43:09 PM UTC 24
Peak memory 230088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350241093 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_acce
ss.2350241093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2771225454
Short name T487
Test name
Test status
Simulation time 114399837 ps
CPU time 4.37 seconds
Started Aug 24 08:42:57 PM UTC 24
Finished Aug 24 08:43:03 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771225454 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2771225454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.1523091175
Short name T508
Test name
Test status
Simulation time 466882661 ps
CPU time 11.07 seconds
Started Aug 24 08:42:58 PM UTC 24
Finished Aug 24 08:43:11 PM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523091175 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1523091175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.3117041498
Short name T515
Test name
Test status
Simulation time 685599673 ps
CPU time 14.73 seconds
Started Aug 24 08:43:00 PM UTC 24
Finished Aug 24 08:43:16 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117041498 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_
token_digest.3117041498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2697035011
Short name T509
Test name
Test status
Simulation time 225007060 ps
CPU time 9.73 seconds
Started Aug 24 08:43:00 PM UTC 24
Finished Aug 24 08:43:11 PM UTC 24
Peak memory 232156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697035011 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_tok
en_mux.2697035011
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.1138835773
Short name T513
Test name
Test status
Simulation time 2901677356 ps
CPU time 11.6 seconds
Started Aug 24 08:42:58 PM UTC 24
Finished Aug 24 08:43:11 PM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138835773 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1138835773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.3924337917
Short name T480
Test name
Test status
Simulation time 40869278 ps
CPU time 2.89 seconds
Started Aug 24 08:42:57 PM UTC 24
Finished Aug 24 08:43:01 PM UTC 24
Peak memory 225764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924337917 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3924337917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2954247932
Short name T543
Test name
Test status
Simulation time 201924429 ps
CPU time 25.14 seconds
Started Aug 24 08:42:57 PM UTC 24
Finished Aug 24 08:43:24 PM UTC 24
Peak memory 262716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954247932 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2954247932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.1559160975
Short name T503
Test name
Test status
Simulation time 181838659 ps
CPU time 9.85 seconds
Started Aug 24 08:42:57 PM UTC 24
Finished Aug 24 08:43:08 PM UTC 24
Peak memory 262652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559160975 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1559160975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.1185248808
Short name T631
Test name
Test status
Simulation time 2063852816 ps
CPU time 49.77 seconds
Started Aug 24 08:43:00 PM UTC 24
Finished Aug 24 08:43:51 PM UTC 24
Peak memory 230328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1185248808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 21.lc_ctrl_stress_all.1185248808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.844161978
Short name T200
Test name
Test status
Simulation time 4007772656 ps
CPU time 180.87 seconds
Started Aug 24 08:43:00 PM UTC 24
Finished Aug 24 08:46:04 PM UTC 24
Peak memory 295960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844161978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.844161978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2727718666
Short name T477
Test name
Test status
Simulation time 45964612 ps
CPU time 1.34 seconds
Started Aug 24 08:42:57 PM UTC 24
Finished Aug 24 08:43:00 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727718666 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_volatile_unlock_smoke.2727718666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.1591568961
Short name T498
Test name
Test status
Simulation time 16209304 ps
CPU time 1.24 seconds
Started Aug 24 08:43:05 PM UTC 24
Finished Aug 24 08:43:07 PM UTC 24
Peak memory 216924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591568961 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1591568961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2854363368
Short name T524
Test name
Test status
Simulation time 3006817083 ps
CPU time 14.34 seconds
Started Aug 24 08:43:02 PM UTC 24
Finished Aug 24 08:43:18 PM UTC 24
Peak memory 232232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854363368 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2854363368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1874805270
Short name T516
Test name
Test status
Simulation time 355776524 ps
CPU time 11.19 seconds
Started Aug 24 08:43:04 PM UTC 24
Finished Aug 24 08:43:16 PM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874805270 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_acce
ss.1874805270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.1064227045
Short name T493
Test name
Test status
Simulation time 49964319 ps
CPU time 2.85 seconds
Started Aug 24 08:43:01 PM UTC 24
Finished Aug 24 08:43:05 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064227045 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1064227045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.527760378
Short name T529
Test name
Test status
Simulation time 1061136592 ps
CPU time 13.98 seconds
Started Aug 24 08:43:04 PM UTC 24
Finished Aug 24 08:43:19 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527760378 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.527760378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.827004317
Short name T532
Test name
Test status
Simulation time 253023092 ps
CPU time 15.47 seconds
Started Aug 24 08:43:04 PM UTC 24
Finished Aug 24 08:43:20 PM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827004317 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_t
oken_digest.827004317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.2168763065
Short name T528
Test name
Test status
Simulation time 567302728 ps
CPU time 13.89 seconds
Started Aug 24 08:43:04 PM UTC 24
Finished Aug 24 08:43:19 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168763065 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_tok
en_mux.2168763065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.924581150
Short name T534
Test name
Test status
Simulation time 395763295 ps
CPU time 15.85 seconds
Started Aug 24 08:43:04 PM UTC 24
Finished Aug 24 08:43:21 PM UTC 24
Peak memory 232336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924581150 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.924581150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3834833103
Short name T486
Test name
Test status
Simulation time 17240530 ps
CPU time 1.53 seconds
Started Aug 24 08:43:00 PM UTC 24
Finished Aug 24 08:43:03 PM UTC 24
Peak memory 222720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834833103 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3834833103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1412906485
Short name T581
Test name
Test status
Simulation time 523794349 ps
CPU time 33.93 seconds
Started Aug 24 08:43:01 PM UTC 24
Finished Aug 24 08:43:37 PM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412906485 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1412906485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1098268875
Short name T210
Test name
Test status
Simulation time 72007240 ps
CPU time 10.64 seconds
Started Aug 24 08:43:01 PM UTC 24
Finished Aug 24 08:43:13 PM UTC 24
Peak memory 260972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098268875 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1098268875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.3395920088
Short name T740
Test name
Test status
Simulation time 2232483636 ps
CPU time 80 seconds
Started Aug 24 08:43:04 PM UTC 24
Finished Aug 24 08:44:26 PM UTC 24
Peak memory 262736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3395920088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 22.lc_ctrl_stress_all.3395920088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2178433939
Short name T490
Test name
Test status
Simulation time 30063740 ps
CPU time 1.61 seconds
Started Aug 24 08:43:01 PM UTC 24
Finished Aug 24 08:43:04 PM UTC 24
Peak memory 222976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178433939 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_volatile_unlock_smoke.2178433939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3314667888
Short name T207
Test name
Test status
Simulation time 108729954 ps
CPU time 1.74 seconds
Started Aug 24 08:43:09 PM UTC 24
Finished Aug 24 08:43:12 PM UTC 24
Peak memory 218632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314667888 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3314667888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2180929137
Short name T576
Test name
Test status
Simulation time 3326411457 ps
CPU time 25.39 seconds
Started Aug 24 08:43:06 PM UTC 24
Finished Aug 24 08:43:33 PM UTC 24
Peak memory 232232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180929137 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2180929137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.4091547691
Short name T610
Test name
Test status
Simulation time 1351505475 ps
CPU time 36.08 seconds
Started Aug 24 08:43:07 PM UTC 24
Finished Aug 24 08:43:45 PM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091547691 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_acce
ss.4091547691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.2053044083
Short name T506
Test name
Test status
Simulation time 75459419 ps
CPU time 2.21 seconds
Started Aug 24 08:43:06 PM UTC 24
Finished Aug 24 08:43:09 PM UTC 24
Peak memory 234228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053044083 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2053044083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2085087912
Short name T546
Test name
Test status
Simulation time 1379992269 ps
CPU time 15.94 seconds
Started Aug 24 08:43:07 PM UTC 24
Finished Aug 24 08:43:25 PM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085087912 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2085087912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.3175695699
Short name T514
Test name
Test status
Simulation time 2078583335 ps
CPU time 23.36 seconds
Started Aug 24 08:43:09 PM UTC 24
Finished Aug 24 08:43:34 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175695699 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_
token_digest.3175695699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.2158448925
Short name T551
Test name
Test status
Simulation time 2006120570 ps
CPU time 15.89 seconds
Started Aug 24 08:43:09 PM UTC 24
Finished Aug 24 08:43:27 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158448925 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_tok
en_mux.2158448925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3356868303
Short name T536
Test name
Test status
Simulation time 365820933 ps
CPU time 12.71 seconds
Started Aug 24 08:43:07 PM UTC 24
Finished Aug 24 08:43:21 PM UTC 24
Peak memory 238092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356868303 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3356868303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.553656143
Short name T504
Test name
Test status
Simulation time 74488812 ps
CPU time 2.45 seconds
Started Aug 24 08:43:05 PM UTC 24
Finished Aug 24 08:43:08 PM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553656143 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.553656143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2646756749
Short name T640
Test name
Test status
Simulation time 1768957272 ps
CPU time 47.56 seconds
Started Aug 24 08:43:05 PM UTC 24
Finished Aug 24 08:43:54 PM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646756749 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2646756749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.1236335740
Short name T520
Test name
Test status
Simulation time 107374837 ps
CPU time 9.21 seconds
Started Aug 24 08:43:06 PM UTC 24
Finished Aug 24 08:43:17 PM UTC 24
Peak memory 260940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236335740 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1236335740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.1510150770
Short name T863
Test name
Test status
Simulation time 91529232636 ps
CPU time 183.84 seconds
Started Aug 24 08:43:09 PM UTC 24
Finished Aug 24 08:46:16 PM UTC 24
Peak memory 289728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1510150770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 23.lc_ctrl_stress_all.1510150770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1792581320
Short name T499
Test name
Test status
Simulation time 96251096 ps
CPU time 1.32 seconds
Started Aug 24 08:43:05 PM UTC 24
Finished Aug 24 08:43:07 PM UTC 24
Peak memory 222724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792581320 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_volatile_unlock_smoke.1792581320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.1143286303
Short name T518
Test name
Test status
Simulation time 16753023 ps
CPU time 1.35 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:16 PM UTC 24
Peak memory 216928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143286303 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1143286303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.1913682340
Short name T545
Test name
Test status
Simulation time 213979244 ps
CPU time 11.67 seconds
Started Aug 24 08:43:11 PM UTC 24
Finished Aug 24 08:43:24 PM UTC 24
Peak memory 230120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913682340 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1913682340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.2881531576
Short name T608
Test name
Test status
Simulation time 6111200109 ps
CPU time 29.77 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:45 PM UTC 24
Peak memory 230240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881531576 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_acce
ss.2881531576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.3400337639
Short name T211
Test name
Test status
Simulation time 189328544 ps
CPU time 2.87 seconds
Started Aug 24 08:43:10 PM UTC 24
Finished Aug 24 08:43:14 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400337639 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3400337639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.751867743
Short name T547
Test name
Test status
Simulation time 208759151 ps
CPU time 10.67 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:25 PM UTC 24
Peak memory 237968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751867743 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.751867743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.4125470353
Short name T566
Test name
Test status
Simulation time 3659133798 ps
CPU time 15.58 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:31 PM UTC 24
Peak memory 232100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125470353 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_
token_digest.4125470353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2332007971
Short name T573
Test name
Test status
Simulation time 1278525254 ps
CPU time 16.5 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:32 PM UTC 24
Peak memory 237832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332007971 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_tok
en_mux.2332007971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.1298795620
Short name T568
Test name
Test status
Simulation time 374079609 ps
CPU time 18.12 seconds
Started Aug 24 08:43:11 PM UTC 24
Finished Aug 24 08:43:31 PM UTC 24
Peak memory 238160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298795620 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1298795620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.1057387861
Short name T98
Test name
Test status
Simulation time 86845879 ps
CPU time 2.87 seconds
Started Aug 24 08:43:09 PM UTC 24
Finished Aug 24 08:43:13 PM UTC 24
Peak memory 225992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057387861 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1057387861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.3923959802
Short name T603
Test name
Test status
Simulation time 437963533 ps
CPU time 32.33 seconds
Started Aug 24 08:43:10 PM UTC 24
Finished Aug 24 08:43:44 PM UTC 24
Peak memory 262556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923959802 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3923959802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.752635520
Short name T212
Test name
Test status
Simulation time 593940037 ps
CPU time 3.39 seconds
Started Aug 24 08:43:10 PM UTC 24
Finished Aug 24 08:43:15 PM UTC 24
Peak memory 234136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752635520 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.752635520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.2442783601
Short name T214
Test name
Test status
Simulation time 29413591760 ps
CPU time 132.84 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:45:29 PM UTC 24
Peak memory 262840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2442783601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 24.lc_ctrl_stress_all.2442783601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.920291448
Short name T205
Test name
Test status
Simulation time 34614943 ps
CPU time 1.28 seconds
Started Aug 24 08:43:09 PM UTC 24
Finished Aug 24 08:43:12 PM UTC 24
Peak memory 222652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920291448 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.lc_ctrl_volatile_unlock_smoke.920291448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1376633747
Short name T530
Test name
Test status
Simulation time 90771880 ps
CPU time 1.35 seconds
Started Aug 24 08:43:17 PM UTC 24
Finished Aug 24 08:43:19 PM UTC 24
Peak memory 218928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376633747 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1376633747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.4084465233
Short name T556
Test name
Test status
Simulation time 1227558573 ps
CPU time 12.98 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:28 PM UTC 24
Peak memory 230384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084465233 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.4084465233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.3441623287
Short name T540
Test name
Test status
Simulation time 932693267 ps
CPU time 6.68 seconds
Started Aug 24 08:43:15 PM UTC 24
Finished Aug 24 08:43:23 PM UTC 24
Peak memory 230068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441623287 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_acce
ss.3441623287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.995863371
Short name T526
Test name
Test status
Simulation time 228374428 ps
CPU time 3.66 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:19 PM UTC 24
Peak memory 234488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995863371 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.995863371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.714420952
Short name T584
Test name
Test status
Simulation time 808224257 ps
CPU time 21.25 seconds
Started Aug 24 08:43:15 PM UTC 24
Finished Aug 24 08:43:37 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714420952 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.714420952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.364636518
Short name T558
Test name
Test status
Simulation time 517464387 ps
CPU time 10.48 seconds
Started Aug 24 08:43:17 PM UTC 24
Finished Aug 24 08:43:29 PM UTC 24
Peak memory 232016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364636518 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_t
oken_digest.364636518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.45795935
Short name T557
Test name
Test status
Simulation time 686748240 ps
CPU time 11.1 seconds
Started Aug 24 08:43:16 PM UTC 24
Finished Aug 24 08:43:28 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45795935 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token
_mux.45795935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.881873816
Short name T554
Test name
Test status
Simulation time 710505217 ps
CPU time 11.36 seconds
Started Aug 24 08:43:15 PM UTC 24
Finished Aug 24 08:43:28 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881873816 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.881873816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.1920249355
Short name T99
Test name
Test status
Simulation time 63824888 ps
CPU time 1.83 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:17 PM UTC 24
Peak memory 222640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920249355 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1920249355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.2576969674
Short name T643
Test name
Test status
Simulation time 1260797968 ps
CPU time 39.45 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:55 PM UTC 24
Peak memory 262668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576969674 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2576969674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3283201632
Short name T544
Test name
Test status
Simulation time 181237274 ps
CPU time 9.13 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:24 PM UTC 24
Peak memory 262672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283201632 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3283201632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.701202184
Short name T837
Test name
Test status
Simulation time 2918999359 ps
CPU time 102.91 seconds
Started Aug 24 08:43:17 PM UTC 24
Finished Aug 24 08:45:02 PM UTC 24
Peak memory 291244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=701202184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 25.lc_ctrl_stress_all.701202184
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3230033966
Short name T517
Test name
Test status
Simulation time 16649785 ps
CPU time 1.49 seconds
Started Aug 24 08:43:13 PM UTC 24
Finished Aug 24 08:43:16 PM UTC 24
Peak memory 228860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230033966 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_volatile_unlock_smoke.3230033966
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2043433875
Short name T541
Test name
Test status
Simulation time 14909001 ps
CPU time 1.22 seconds
Started Aug 24 08:43:21 PM UTC 24
Finished Aug 24 08:43:24 PM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043433875 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2043433875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.2396215213
Short name T567
Test name
Test status
Simulation time 459931466 ps
CPU time 16.83 seconds
Started Aug 24 08:43:18 PM UTC 24
Finished Aug 24 08:43:36 PM UTC 24
Peak memory 232240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396215213 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2396215213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.2637461754
Short name T553
Test name
Test status
Simulation time 943443144 ps
CPU time 6.01 seconds
Started Aug 24 08:43:20 PM UTC 24
Finished Aug 24 08:43:27 PM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637461754 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_acce
ss.2637461754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.3637761853
Short name T537
Test name
Test status
Simulation time 64684093 ps
CPU time 2.07 seconds
Started Aug 24 08:43:18 PM UTC 24
Finished Aug 24 08:43:21 PM UTC 24
Peak memory 230208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637761853 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3637761853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2705275312
Short name T583
Test name
Test status
Simulation time 264296732 ps
CPU time 15.99 seconds
Started Aug 24 08:43:20 PM UTC 24
Finished Aug 24 08:43:37 PM UTC 24
Peak memory 238160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705275312 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2705275312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.3646315116
Short name T598
Test name
Test status
Simulation time 2324163424 ps
CPU time 21.69 seconds
Started Aug 24 08:43:20 PM UTC 24
Finished Aug 24 08:43:43 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646315116 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_
token_digest.3646315116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.3282820708
Short name T580
Test name
Test status
Simulation time 997539017 ps
CPU time 15.52 seconds
Started Aug 24 08:43:20 PM UTC 24
Finished Aug 24 08:43:36 PM UTC 24
Peak memory 232464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282820708 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_tok
en_mux.3282820708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.2095739712
Short name T564
Test name
Test status
Simulation time 273302161 ps
CPU time 8.8 seconds
Started Aug 24 08:43:20 PM UTC 24
Finished Aug 24 08:43:30 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095739712 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2095739712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.1723770365
Short name T535
Test name
Test status
Simulation time 237079062 ps
CPU time 3.05 seconds
Started Aug 24 08:43:17 PM UTC 24
Finished Aug 24 08:43:21 PM UTC 24
Peak memory 236272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723770365 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1723770365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.3984257743
Short name T623
Test name
Test status
Simulation time 4260560518 ps
CPU time 29.3 seconds
Started Aug 24 08:43:18 PM UTC 24
Finished Aug 24 08:43:49 PM UTC 24
Peak memory 262804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984257743 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3984257743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1123946220
Short name T552
Test name
Test status
Simulation time 148557220 ps
CPU time 16.6 seconds
Started Aug 24 08:43:18 PM UTC 24
Finished Aug 24 08:43:36 PM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123946220 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1123946220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.2011797314
Short name T93
Test name
Test status
Simulation time 46202287544 ps
CPU time 315.48 seconds
Started Aug 24 08:43:20 PM UTC 24
Finished Aug 24 08:48:39 PM UTC 24
Peak memory 295716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2011797314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 26.lc_ctrl_stress_all.2011797314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1358796977
Short name T533
Test name
Test status
Simulation time 14069536 ps
CPU time 1.29 seconds
Started Aug 24 08:43:18 PM UTC 24
Finished Aug 24 08:43:21 PM UTC 24
Peak memory 228852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358796977 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_volatile_unlock_smoke.1358796977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.692451221
Short name T555
Test name
Test status
Simulation time 97380980 ps
CPU time 1.74 seconds
Started Aug 24 08:43:25 PM UTC 24
Finished Aug 24 08:43:28 PM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692451221 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.692451221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1590609559
Short name T587
Test name
Test status
Simulation time 1124290154 ps
CPU time 13.88 seconds
Started Aug 24 08:43:23 PM UTC 24
Finished Aug 24 08:43:38 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590609559 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1590609559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.377679754
Short name T563
Test name
Test status
Simulation time 1632805031 ps
CPU time 4.68 seconds
Started Aug 24 08:43:24 PM UTC 24
Finished Aug 24 08:43:29 PM UTC 24
Peak memory 230108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377679754 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.377679754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3285762084
Short name T550
Test name
Test status
Simulation time 36486984 ps
CPU time 2.54 seconds
Started Aug 24 08:43:23 PM UTC 24
Finished Aug 24 08:43:26 PM UTC 24
Peak memory 234304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285762084 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3285762084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.2471081434
Short name T602
Test name
Test status
Simulation time 7485496831 ps
CPU time 18.56 seconds
Started Aug 24 08:43:24 PM UTC 24
Finished Aug 24 08:43:44 PM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471081434 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2471081434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1178761261
Short name T611
Test name
Test status
Simulation time 1978545158 ps
CPU time 18.68 seconds
Started Aug 24 08:43:25 PM UTC 24
Finished Aug 24 08:43:45 PM UTC 24
Peak memory 237780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178761261 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_
token_digest.1178761261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.1259988171
Short name T615
Test name
Test status
Simulation time 2837395550 ps
CPU time 20.09 seconds
Started Aug 24 08:43:25 PM UTC 24
Finished Aug 24 08:43:46 PM UTC 24
Peak memory 232232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259988171 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_tok
en_mux.1259988171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.127967908
Short name T600
Test name
Test status
Simulation time 389590431 ps
CPU time 18.15 seconds
Started Aug 24 08:43:24 PM UTC 24
Finished Aug 24 08:43:43 PM UTC 24
Peak memory 232188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127967908 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.127967908
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3974246302
Short name T549
Test name
Test status
Simulation time 169507576 ps
CPU time 3.6 seconds
Started Aug 24 08:43:21 PM UTC 24
Finished Aug 24 08:43:26 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974246302 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3974246302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.3559864872
Short name T681
Test name
Test status
Simulation time 1224806569 ps
CPU time 39.59 seconds
Started Aug 24 08:43:23 PM UTC 24
Finished Aug 24 08:44:04 PM UTC 24
Peak memory 259996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559864872 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3559864872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.1501391312
Short name T585
Test name
Test status
Simulation time 210256322 ps
CPU time 13.78 seconds
Started Aug 24 08:43:23 PM UTC 24
Finished Aug 24 08:43:37 PM UTC 24
Peak memory 262172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501391312 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1501391312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.1853391789
Short name T866
Test name
Test status
Simulation time 7271213071 ps
CPU time 182.54 seconds
Started Aug 24 08:43:25 PM UTC 24
Finished Aug 24 08:46:30 PM UTC 24
Peak memory 295744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1853391789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 27.lc_ctrl_stress_all.1853391789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.609659717
Short name T542
Test name
Test status
Simulation time 37079888 ps
CPU time 1.43 seconds
Started Aug 24 08:43:21 PM UTC 24
Finished Aug 24 08:43:24 PM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609659717 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.lc_ctrl_volatile_unlock_smoke.609659717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.4287798151
Short name T577
Test name
Test status
Simulation time 24556606 ps
CPU time 1.5 seconds
Started Aug 24 08:43:30 PM UTC 24
Finished Aug 24 08:43:33 PM UTC 24
Peak memory 218928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287798151 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4287798151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.1195849578
Short name T612
Test name
Test status
Simulation time 691107910 ps
CPU time 16.36 seconds
Started Aug 24 08:43:27 PM UTC 24
Finished Aug 24 08:43:45 PM UTC 24
Peak memory 232240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195849578 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1195849578
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3299800865
Short name T582
Test name
Test status
Simulation time 262014813 ps
CPU time 6.64 seconds
Started Aug 24 08:43:29 PM UTC 24
Finished Aug 24 08:43:37 PM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299800865 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_acce
ss.3299800865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3725404976
Short name T574
Test name
Test status
Simulation time 58669079 ps
CPU time 2.9 seconds
Started Aug 24 08:43:27 PM UTC 24
Finished Aug 24 08:43:32 PM UTC 24
Peak memory 232192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725404976 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3725404976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.4024734919
Short name T620
Test name
Test status
Simulation time 1613865670 ps
CPU time 17.44 seconds
Started Aug 24 08:43:29 PM UTC 24
Finished Aug 24 08:43:48 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024734919 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.4024734919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.1921082075
Short name T592
Test name
Test status
Simulation time 910394092 ps
CPU time 10.96 seconds
Started Aug 24 08:43:29 PM UTC 24
Finished Aug 24 08:43:41 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921082075 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_
token_digest.1921082075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3744915068
Short name T596
Test name
Test status
Simulation time 407660018 ps
CPU time 11.86 seconds
Started Aug 24 08:43:29 PM UTC 24
Finished Aug 24 08:43:42 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744915068 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_tok
en_mux.3744915068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.618873826
Short name T617
Test name
Test status
Simulation time 750113132 ps
CPU time 17.94 seconds
Started Aug 24 08:43:27 PM UTC 24
Finished Aug 24 08:43:47 PM UTC 24
Peak memory 238168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618873826 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.618873826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.3068730070
Short name T572
Test name
Test status
Simulation time 272407168 ps
CPU time 3.95 seconds
Started Aug 24 08:43:26 PM UTC 24
Finished Aug 24 08:43:31 PM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068730070 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3068730070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.692662713
Short name T628
Test name
Test status
Simulation time 601176663 ps
CPU time 23.25 seconds
Started Aug 24 08:43:26 PM UTC 24
Finished Aug 24 08:43:51 PM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692662713 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.692662713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1209641477
Short name T593
Test name
Test status
Simulation time 269336368 ps
CPU time 13.56 seconds
Started Aug 24 08:43:26 PM UTC 24
Finished Aug 24 08:43:41 PM UTC 24
Peak memory 260780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209641477 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1209641477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2039821259
Short name T856
Test name
Test status
Simulation time 14913509492 ps
CPU time 116.29 seconds
Started Aug 24 08:43:30 PM UTC 24
Finished Aug 24 08:45:29 PM UTC 24
Peak memory 285356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2039821259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 28.lc_ctrl_stress_all.2039821259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3609038328
Short name T559
Test name
Test status
Simulation time 43647586 ps
CPU time 1.38 seconds
Started Aug 24 08:43:26 PM UTC 24
Finished Aug 24 08:43:29 PM UTC 24
Peak memory 223040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609038328 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_volatile_unlock_smoke.3609038328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.1483787431
Short name T579
Test name
Test status
Simulation time 54444698 ps
CPU time 1.29 seconds
Started Aug 24 08:43:33 PM UTC 24
Finished Aug 24 08:43:36 PM UTC 24
Peak memory 219048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483787431 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1483787431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.836701051
Short name T604
Test name
Test status
Simulation time 486069685 ps
CPU time 10.67 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:43:44 PM UTC 24
Peak memory 230120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836701051 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.836701051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.1623749083
Short name T591
Test name
Test status
Simulation time 255330945 ps
CPU time 7.47 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:43:41 PM UTC 24
Peak memory 229820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623749083 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_acce
ss.1623749083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.3695531107
Short name T523
Test name
Test status
Simulation time 31831747 ps
CPU time 2.8 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:43:36 PM UTC 24
Peak memory 234228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695531107 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3695531107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.1452212185
Short name T609
Test name
Test status
Simulation time 229176923 ps
CPU time 11.25 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:43:45 PM UTC 24
Peak memory 238160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452212185 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1452212185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.1616943736
Short name T627
Test name
Test status
Simulation time 869569386 ps
CPU time 16.59 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:43:50 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616943736 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_
token_digest.1616943736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3233571987
Short name T613
Test name
Test status
Simulation time 1448857775 ps
CPU time 12.14 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:43:46 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233571987 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_tok
en_mux.3233571987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.726101968
Short name T607
Test name
Test status
Simulation time 683684860 ps
CPU time 10.81 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:43:44 PM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726101968 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.726101968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.3379011013
Short name T578
Test name
Test status
Simulation time 109815411 ps
CPU time 3.42 seconds
Started Aug 24 08:43:30 PM UTC 24
Finished Aug 24 08:43:35 PM UTC 24
Peak memory 226032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379011013 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3379011013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1878269421
Short name T673
Test name
Test status
Simulation time 159696714 ps
CPU time 29.92 seconds
Started Aug 24 08:43:30 PM UTC 24
Finished Aug 24 08:44:02 PM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878269421 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1878269421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2942571392
Short name T570
Test name
Test status
Simulation time 276009840 ps
CPU time 4.23 seconds
Started Aug 24 08:43:31 PM UTC 24
Finished Aug 24 08:43:36 PM UTC 24
Peak memory 234504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942571392 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2942571392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.281932655
Short name T732
Test name
Test status
Simulation time 8376680919 ps
CPU time 49.65 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:44:24 PM UTC 24
Peak memory 263076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=281932655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.lc_ctrl_stress_all.281932655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1414467337
Short name T124
Test name
Test status
Simulation time 8277146032 ps
CPU time 96.1 seconds
Started Aug 24 08:43:32 PM UTC 24
Finished Aug 24 08:45:11 PM UTC 24
Peak memory 281372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414467337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1414467337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1658884321
Short name T575
Test name
Test status
Simulation time 44527819 ps
CPU time 1.23 seconds
Started Aug 24 08:43:30 PM UTC 24
Finished Aug 24 08:43:33 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658884321 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_volatile_unlock_smoke.1658884321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.3806839546
Short name T46
Test name
Test status
Simulation time 15572877 ps
CPU time 1.47 seconds
Started Aug 24 08:41:18 PM UTC 24
Finished Aug 24 08:41:21 PM UTC 24
Peak memory 217988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806839546 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3806839546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3605915099
Short name T42
Test name
Test status
Simulation time 1164618524 ps
CPU time 11.57 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:28 PM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605915099 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3605915099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.4923164
Short name T47
Test name
Test status
Simulation time 439515450 ps
CPU time 14.04 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:31 PM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4923164 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4923164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.381266211
Short name T358
Test name
Test status
Simulation time 25603973887 ps
CPU time 53.03 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:42:11 PM UTC 24
Peak memory 237748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381266211
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_errors.381266211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.219494074
Short name T11
Test name
Test status
Simulation time 2462874243 ps
CPU time 11.42 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:28 PM UTC 24
Peak memory 230064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219494074 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_prio
rity.219494074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3370437100
Short name T264
Test name
Test status
Simulation time 317780442 ps
CPU time 11.76 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:29 PM UTC 24
Peak memory 235996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370437100
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_jtag_prog_failure.3370437100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.894330101
Short name T295
Test name
Test status
Simulation time 2746445010 ps
CPU time 24.51 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:42 PM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894330101
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc
_ctrl_jtag_regwen_during_op.894330101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.1290023572
Short name T8
Test name
Test status
Simulation time 144797214 ps
CPU time 5.72 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:23 PM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290023572
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_smoke.1290023572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.157307637
Short name T224
Test name
Test status
Simulation time 31761808695 ps
CPU time 86.96 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:42:45 PM UTC 24
Peak memory 295636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157307637
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_jtag_state_failure.157307637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.616477812
Short name T37
Test name
Test status
Simulation time 3879839141 ps
CPU time 13.64 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:31 PM UTC 24
Peak memory 236548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616477812
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc
_ctrl_jtag_state_post_trans.616477812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.2465361986
Short name T30
Test name
Test status
Simulation time 220513446 ps
CPU time 4.53 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:21 PM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465361986 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2465361986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2666177160
Short name T81
Test name
Test status
Simulation time 434935213 ps
CPU time 12.75 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:30 PM UTC 24
Peak memory 225724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666177160 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2666177160
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.344189058
Short name T132
Test name
Test status
Simulation time 221380860 ps
CPU time 35.93 seconds
Started Aug 24 08:41:18 PM UTC 24
Finished Aug 24 08:41:56 PM UTC 24
Peak memory 289844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344189058 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.344189058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1687905520
Short name T66
Test name
Test status
Simulation time 1019451682 ps
CPU time 13.78 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:31 PM UTC 24
Peak memory 227404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687905520 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1687905520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.82631967
Short name T35
Test name
Test status
Simulation time 641768869 ps
CPU time 13.36 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:30 PM UTC 24
Peak memory 232240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82631967 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_tok
en_digest.82631967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1667727868
Short name T274
Test name
Test status
Simulation time 324617087 ps
CPU time 12.22 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:29 PM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667727868 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_toke
n_mux.1667727868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1968386812
Short name T74
Test name
Test status
Simulation time 429155857 ps
CPU time 19.84 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:37 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968386812 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1968386812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2779674548
Short name T26
Test name
Test status
Simulation time 481528004 ps
CPU time 7.56 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:24 PM UTC 24
Peak memory 228524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779674548 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2779674548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1116307241
Short name T329
Test name
Test status
Simulation time 638402010 ps
CPU time 42.83 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:42:00 PM UTC 24
Peak memory 258536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116307241 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1116307241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.1378163943
Short name T115
Test name
Test status
Simulation time 3650963548 ps
CPU time 95.28 seconds
Started Aug 24 08:41:18 PM UTC 24
Finished Aug 24 08:42:56 PM UTC 24
Peak memory 281248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1378163943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 3.lc_ctrl_stress_all.1378163943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.348326837
Short name T18
Test name
Test status
Simulation time 15234971 ps
CPU time 0.99 seconds
Started Aug 24 08:41:14 PM UTC 24
Finished Aug 24 08:41:18 PM UTC 24
Peak memory 222376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348326837 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
.lc_ctrl_volatile_unlock_smoke.348326837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2170810033
Short name T589
Test name
Test status
Simulation time 20485518 ps
CPU time 1.74 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:43:40 PM UTC 24
Peak memory 217000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170810033 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2170810033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.3881175274
Short name T652
Test name
Test status
Simulation time 1699275467 ps
CPU time 17.57 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:43:56 PM UTC 24
Peak memory 232156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881175274 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3881175274
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2341946888
Short name T642
Test name
Test status
Simulation time 897786914 ps
CPU time 15.97 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:43:54 PM UTC 24
Peak memory 230032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341946888 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_acce
ss.2341946888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.4152799322
Short name T588
Test name
Test status
Simulation time 95827366 ps
CPU time 2.48 seconds
Started Aug 24 08:43:36 PM UTC 24
Finished Aug 24 08:43:39 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152799322 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.4152799322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.2647872425
Short name T644
Test name
Test status
Simulation time 399073845 ps
CPU time 16.37 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:43:55 PM UTC 24
Peak memory 232372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647872425 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2647872425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3673115322
Short name T638
Test name
Test status
Simulation time 259921650 ps
CPU time 14.91 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:43:54 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673115322 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_
token_digest.3673115322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3081551858
Short name T647
Test name
Test status
Simulation time 1614458528 ps
CPU time 16.92 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:43:55 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081551858 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_tok
en_mux.3081551858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.3130629680
Short name T648
Test name
Test status
Simulation time 2155334261 ps
CPU time 16.97 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:43:55 PM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130629680 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3130629680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.480281702
Short name T590
Test name
Test status
Simulation time 150283988 ps
CPU time 5.57 seconds
Started Aug 24 08:43:33 PM UTC 24
Finished Aug 24 08:43:40 PM UTC 24
Peak memory 229944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480281702 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.480281702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.188306100
Short name T701
Test name
Test status
Simulation time 689746476 ps
CPU time 36.34 seconds
Started Aug 24 08:43:34 PM UTC 24
Finished Aug 24 08:44:11 PM UTC 24
Peak memory 260616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188306100 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.188306100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.1743574327
Short name T626
Test name
Test status
Simulation time 280786765 ps
CPU time 12.58 seconds
Started Aug 24 08:43:36 PM UTC 24
Finished Aug 24 08:43:50 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743574327 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1743574327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3587112997
Short name T836
Test name
Test status
Simulation time 23467318145 ps
CPU time 82.58 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:45:02 PM UTC 24
Peak memory 279864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587112997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3587112997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2515358497
Short name T565
Test name
Test status
Simulation time 16791172 ps
CPU time 1.28 seconds
Started Aug 24 08:43:33 PM UTC 24
Finished Aug 24 08:43:36 PM UTC 24
Peak memory 220484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515358497 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_volatile_unlock_smoke.2515358497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.483384383
Short name T606
Test name
Test status
Simulation time 19507448 ps
CPU time 1.27 seconds
Started Aug 24 08:43:42 PM UTC 24
Finished Aug 24 08:43:44 PM UTC 24
Peak memory 217544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483384383 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.483384383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3928612563
Short name T660
Test name
Test status
Simulation time 433570357 ps
CPU time 18.89 seconds
Started Aug 24 08:43:39 PM UTC 24
Finished Aug 24 08:43:59 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928612563 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3928612563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.2338871099
Short name T618
Test name
Test status
Simulation time 197506103 ps
CPU time 5.16 seconds
Started Aug 24 08:43:41 PM UTC 24
Finished Aug 24 08:43:47 PM UTC 24
Peak memory 229848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338871099 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_acce
ss.2338871099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.3366156572
Short name T601
Test name
Test status
Simulation time 240388389 ps
CPU time 3.76 seconds
Started Aug 24 08:43:39 PM UTC 24
Finished Aug 24 08:43:44 PM UTC 24
Peak memory 232328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366156572 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3366156572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.925177593
Short name T669
Test name
Test status
Simulation time 1119959854 ps
CPU time 18.84 seconds
Started Aug 24 08:43:41 PM UTC 24
Finished Aug 24 08:44:01 PM UTC 24
Peak memory 232508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925177593 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.925177593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.227274660
Short name T645
Test name
Test status
Simulation time 277089913 ps
CPU time 11.93 seconds
Started Aug 24 08:43:42 PM UTC 24
Finished Aug 24 08:43:55 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227274660 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_t
oken_digest.227274660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.865547494
Short name T654
Test name
Test status
Simulation time 988538569 ps
CPU time 12.85 seconds
Started Aug 24 08:43:42 PM UTC 24
Finished Aug 24 08:43:56 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865547494 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_toke
n_mux.865547494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.4246944551
Short name T667
Test name
Test status
Simulation time 384488322 ps
CPU time 19.28 seconds
Started Aug 24 08:43:40 PM UTC 24
Finished Aug 24 08:44:00 PM UTC 24
Peak memory 237892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246944551 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.4246944551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3243627426
Short name T595
Test name
Test status
Simulation time 154304041 ps
CPU time 2.82 seconds
Started Aug 24 08:43:37 PM UTC 24
Finished Aug 24 08:43:41 PM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243627426 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3243627426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.987389885
Short name T751
Test name
Test status
Simulation time 1081084014 ps
CPU time 49.84 seconds
Started Aug 24 08:43:39 PM UTC 24
Finished Aug 24 08:44:30 PM UTC 24
Peak memory 261028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987389885 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.987389885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3483422819
Short name T633
Test name
Test status
Simulation time 134199817 ps
CPU time 12.07 seconds
Started Aug 24 08:43:39 PM UTC 24
Finished Aug 24 08:43:52 PM UTC 24
Peak memory 262996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483422819 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3483422819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1902097092
Short name T745
Test name
Test status
Simulation time 1471886059 ps
CPU time 45.05 seconds
Started Aug 24 08:43:42 PM UTC 24
Finished Aug 24 08:44:29 PM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1902097092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 31.lc_ctrl_stress_all.1902097092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3130078599
Short name T189
Test name
Test status
Simulation time 3853815032 ps
CPU time 79.13 seconds
Started Aug 24 08:43:42 PM UTC 24
Finished Aug 24 08:45:03 PM UTC 24
Peak memory 262928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130078599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.3130078599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.675664982
Short name T594
Test name
Test status
Simulation time 20011962 ps
CPU time 1.4 seconds
Started Aug 24 08:43:39 PM UTC 24
Finished Aug 24 08:43:41 PM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675664982 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.lc_ctrl_volatile_unlock_smoke.675664982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.1625817622
Short name T624
Test name
Test status
Simulation time 35570090 ps
CPU time 1.18 seconds
Started Aug 24 08:43:47 PM UTC 24
Finished Aug 24 08:43:49 PM UTC 24
Peak memory 218260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625817622 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1625817622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3433671620
Short name T659
Test name
Test status
Simulation time 655345554 ps
CPU time 12.6 seconds
Started Aug 24 08:43:45 PM UTC 24
Finished Aug 24 08:43:59 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433671620 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3433671620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.4031425503
Short name T663
Test name
Test status
Simulation time 1506226770 ps
CPU time 13.41 seconds
Started Aug 24 08:43:45 PM UTC 24
Finished Aug 24 08:44:00 PM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031425503 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_acce
ss.4031425503
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.737611101
Short name T629
Test name
Test status
Simulation time 371205592 ps
CPU time 5.24 seconds
Started Aug 24 08:43:45 PM UTC 24
Finished Aug 24 08:43:51 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737611101 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.737611101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.178406687
Short name T655
Test name
Test status
Simulation time 1324625202 ps
CPU time 9.9 seconds
Started Aug 24 08:43:45 PM UTC 24
Finished Aug 24 08:43:56 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178406687 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.178406687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2507948490
Short name T651
Test name
Test status
Simulation time 965976543 ps
CPU time 9.66 seconds
Started Aug 24 08:43:45 PM UTC 24
Finished Aug 24 08:43:56 PM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507948490 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_
token_digest.2507948490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.1954105944
Short name T656
Test name
Test status
Simulation time 354600313 ps
CPU time 10.83 seconds
Started Aug 24 08:43:45 PM UTC 24
Finished Aug 24 08:43:57 PM UTC 24
Peak memory 237984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954105944 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_tok
en_mux.1954105944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.2327109425
Short name T680
Test name
Test status
Simulation time 1748742046 ps
CPU time 17.26 seconds
Started Aug 24 08:43:45 PM UTC 24
Finished Aug 24 08:44:04 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327109425 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2327109425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3846632574
Short name T621
Test name
Test status
Simulation time 36996636 ps
CPU time 3.39 seconds
Started Aug 24 08:43:43 PM UTC 24
Finished Aug 24 08:43:48 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846632574 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3846632574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.451766678
Short name T715
Test name
Test status
Simulation time 1806288793 ps
CPU time 32.67 seconds
Started Aug 24 08:43:43 PM UTC 24
Finished Aug 24 08:44:17 PM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451766678 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.451766678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.822623987
Short name T632
Test name
Test status
Simulation time 74490410 ps
CPU time 5.53 seconds
Started Aug 24 08:43:45 PM UTC 24
Finished Aug 24 08:43:52 PM UTC 24
Peak memory 236800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822623987 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.822623987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.1696717682
Short name T865
Test name
Test status
Simulation time 8395077482 ps
CPU time 159.8 seconds
Started Aug 24 08:43:47 PM UTC 24
Finished Aug 24 08:46:29 PM UTC 24
Peak memory 289216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1696717682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 32.lc_ctrl_stress_all.1696717682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4050002144
Short name T614
Test name
Test status
Simulation time 13837159 ps
CPU time 1.41 seconds
Started Aug 24 08:43:43 PM UTC 24
Finished Aug 24 08:43:46 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050002144 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_volatile_unlock_smoke.4050002144
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2487500189
Short name T635
Test name
Test status
Simulation time 22131870 ps
CPU time 1.66 seconds
Started Aug 24 08:43:50 PM UTC 24
Finished Aug 24 08:43:52 PM UTC 24
Peak memory 218928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487500189 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2487500189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3673688604
Short name T678
Test name
Test status
Simulation time 262666243 ps
CPU time 14.86 seconds
Started Aug 24 08:43:47 PM UTC 24
Finished Aug 24 08:44:03 PM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673688604 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3673688604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2857865188
Short name T637
Test name
Test status
Simulation time 112929049 ps
CPU time 3.29 seconds
Started Aug 24 08:43:48 PM UTC 24
Finished Aug 24 08:43:53 PM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857865188 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_acce
ss.2857865188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.3754755724
Short name T639
Test name
Test status
Simulation time 100229485 ps
CPU time 6.04 seconds
Started Aug 24 08:43:47 PM UTC 24
Finished Aug 24 08:43:54 PM UTC 24
Peak memory 236608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754755724 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3754755724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.2818511039
Short name T672
Test name
Test status
Simulation time 748450150 ps
CPU time 12 seconds
Started Aug 24 08:43:48 PM UTC 24
Finished Aug 24 08:44:02 PM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818511039 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2818511039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2492247240
Short name T684
Test name
Test status
Simulation time 390319542 ps
CPU time 17.15 seconds
Started Aug 24 08:43:48 PM UTC 24
Finished Aug 24 08:44:07 PM UTC 24
Peak memory 232188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492247240 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_
token_digest.2492247240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.149706137
Short name T668
Test name
Test status
Simulation time 1635629905 ps
CPU time 10.9 seconds
Started Aug 24 08:43:48 PM UTC 24
Finished Aug 24 08:44:01 PM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149706137 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_toke
n_mux.149706137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.2497259363
Short name T658
Test name
Test status
Simulation time 3757785288 ps
CPU time 8.95 seconds
Started Aug 24 08:43:48 PM UTC 24
Finished Aug 24 08:43:58 PM UTC 24
Peak memory 232120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497259363 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2497259363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2687917426
Short name T90
Test name
Test status
Simulation time 131953237 ps
CPU time 2.94 seconds
Started Aug 24 08:43:47 PM UTC 24
Finished Aug 24 08:43:51 PM UTC 24
Peak memory 225408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687917426 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2687917426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3705773140
Short name T774
Test name
Test status
Simulation time 3052050169 ps
CPU time 49.61 seconds
Started Aug 24 08:43:47 PM UTC 24
Finished Aug 24 08:44:38 PM UTC 24
Peak memory 262836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705773140 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3705773140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.3817424823
Short name T646
Test name
Test status
Simulation time 813953706 ps
CPU time 7.08 seconds
Started Aug 24 08:43:47 PM UTC 24
Finished Aug 24 08:43:55 PM UTC 24
Peak memory 234576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817424823 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3817424823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.1237005093
Short name T855
Test name
Test status
Simulation time 4295666073 ps
CPU time 96.48 seconds
Started Aug 24 08:43:48 PM UTC 24
Finished Aug 24 08:45:27 PM UTC 24
Peak memory 258740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1237005093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 33.lc_ctrl_stress_all.1237005093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.4164356918
Short name T146
Test name
Test status
Simulation time 8115878453 ps
CPU time 68.9 seconds
Started Aug 24 08:43:48 PM UTC 24
Finished Aug 24 08:44:59 PM UTC 24
Peak memory 281356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164356918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.4164356918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.865919344
Short name T625
Test name
Test status
Simulation time 34436624 ps
CPU time 1.14 seconds
Started Aug 24 08:43:47 PM UTC 24
Finished Aug 24 08:43:49 PM UTC 24
Peak memory 220616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865919344 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.lc_ctrl_volatile_unlock_smoke.865919344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2153816494
Short name T653
Test name
Test status
Simulation time 34101752 ps
CPU time 1.55 seconds
Started Aug 24 08:43:53 PM UTC 24
Finished Aug 24 08:43:56 PM UTC 24
Peak memory 218768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153816494 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2153816494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.1160713536
Short name T689
Test name
Test status
Simulation time 267328761 ps
CPU time 15.02 seconds
Started Aug 24 08:43:52 PM UTC 24
Finished Aug 24 08:44:08 PM UTC 24
Peak memory 230120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160713536 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1160713536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.272394084
Short name T657
Test name
Test status
Simulation time 1353487552 ps
CPU time 4 seconds
Started Aug 24 08:43:52 PM UTC 24
Finished Aug 24 08:43:57 PM UTC 24
Peak memory 229852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272394084 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.272394084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.79469329
Short name T630
Test name
Test status
Simulation time 69695266 ps
CPU time 4.85 seconds
Started Aug 24 08:43:51 PM UTC 24
Finished Aug 24 08:43:57 PM UTC 24
Peak memory 236276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79469329 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.79469329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3450771098
Short name T706
Test name
Test status
Simulation time 349083593 ps
CPU time 20.53 seconds
Started Aug 24 08:43:52 PM UTC 24
Finished Aug 24 08:44:14 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450771098 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3450771098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.3266445366
Short name T687
Test name
Test status
Simulation time 1711054428 ps
CPU time 14.26 seconds
Started Aug 24 08:43:52 PM UTC 24
Finished Aug 24 08:44:08 PM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266445366 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_
token_digest.3266445366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.3409996775
Short name T686
Test name
Test status
Simulation time 2224102640 ps
CPU time 13.8 seconds
Started Aug 24 08:43:52 PM UTC 24
Finished Aug 24 08:44:07 PM UTC 24
Peak memory 232504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409996775 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_tok
en_mux.3409996775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3565411732
Short name T702
Test name
Test status
Simulation time 592094477 ps
CPU time 18.62 seconds
Started Aug 24 08:43:52 PM UTC 24
Finished Aug 24 08:44:12 PM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565411732 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3565411732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.3038979494
Short name T101
Test name
Test status
Simulation time 68853523 ps
CPU time 1.73 seconds
Started Aug 24 08:43:50 PM UTC 24
Finished Aug 24 08:43:52 PM UTC 24
Peak memory 229032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038979494 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3038979494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.815299821
Short name T754
Test name
Test status
Simulation time 284430887 ps
CPU time 40.12 seconds
Started Aug 24 08:43:50 PM UTC 24
Finished Aug 24 08:44:31 PM UTC 24
Peak memory 262840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815299821 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.815299821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.4264484363
Short name T679
Test name
Test status
Simulation time 99629209 ps
CPU time 11.56 seconds
Started Aug 24 08:43:51 PM UTC 24
Finished Aug 24 08:44:04 PM UTC 24
Peak memory 260776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264484363 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.4264484363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2916636392
Short name T735
Test name
Test status
Simulation time 1066905642 ps
CPU time 31.18 seconds
Started Aug 24 08:43:52 PM UTC 24
Finished Aug 24 08:44:25 PM UTC 24
Peak memory 230112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2916636392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 34.lc_ctrl_stress_all.2916636392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2017537398
Short name T634
Test name
Test status
Simulation time 14956901 ps
CPU time 1.55 seconds
Started Aug 24 08:43:50 PM UTC 24
Finished Aug 24 08:43:52 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017537398 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_volatile_unlock_smoke.2017537398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.193003902
Short name T665
Test name
Test status
Simulation time 27796327 ps
CPU time 1.92 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:00 PM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193003902 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.193003902
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.3204672716
Short name T717
Test name
Test status
Simulation time 4761775150 ps
CPU time 22.27 seconds
Started Aug 24 08:43:55 PM UTC 24
Finished Aug 24 08:44:18 PM UTC 24
Peak memory 232232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204672716 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3204672716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3245972541
Short name T693
Test name
Test status
Simulation time 1483050440 ps
CPU time 11.28 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:09 PM UTC 24
Peak memory 229688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245972541 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_acce
ss.3245972541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.1968761691
Short name T664
Test name
Test status
Simulation time 205899106 ps
CPU time 3.82 seconds
Started Aug 24 08:43:55 PM UTC 24
Finished Aug 24 08:44:00 PM UTC 24
Peak memory 236140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968761691 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1968761691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.2034319322
Short name T691
Test name
Test status
Simulation time 670893192 ps
CPU time 11.22 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:09 PM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034319322 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2034319322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.1356715818
Short name T708
Test name
Test status
Simulation time 552228234 ps
CPU time 16.6 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:14 PM UTC 24
Peak memory 232044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356715818 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_
token_digest.1356715818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.142618431
Short name T696
Test name
Test status
Simulation time 426127686 ps
CPU time 12.73 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:11 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142618431 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_toke
n_mux.142618431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.1533444570
Short name T685
Test name
Test status
Simulation time 470282582 ps
CPU time 11.25 seconds
Started Aug 24 08:43:55 PM UTC 24
Finished Aug 24 08:44:07 PM UTC 24
Peak memory 231996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533444570 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1533444570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2891004677
Short name T100
Test name
Test status
Simulation time 35066779 ps
CPU time 2.57 seconds
Started Aug 24 08:43:53 PM UTC 24
Finished Aug 24 08:43:57 PM UTC 24
Peak memory 225764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891004677 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2891004677
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.4036325391
Short name T743
Test name
Test status
Simulation time 1121143266 ps
CPU time 32.63 seconds
Started Aug 24 08:43:53 PM UTC 24
Finished Aug 24 08:44:27 PM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036325391 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4036325391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.3431362942
Short name T688
Test name
Test status
Simulation time 502852496 ps
CPU time 13.28 seconds
Started Aug 24 08:43:53 PM UTC 24
Finished Aug 24 08:44:08 PM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431362942 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3431362942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2597978386
Short name T852
Test name
Test status
Simulation time 1908813199 ps
CPU time 84.91 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 281276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2597978386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 35.lc_ctrl_stress_all.2597978386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.222271534
Short name T649
Test name
Test status
Simulation time 35508170 ps
CPU time 1.25 seconds
Started Aug 24 08:43:53 PM UTC 24
Finished Aug 24 08:43:56 PM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222271534 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.lc_ctrl_volatile_unlock_smoke.222271534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2119658540
Short name T675
Test name
Test status
Simulation time 38104910 ps
CPU time 1.45 seconds
Started Aug 24 08:44:00 PM UTC 24
Finished Aug 24 08:44:02 PM UTC 24
Peak memory 218928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119658540 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2119658540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.1409627427
Short name T724
Test name
Test status
Simulation time 903019992 ps
CPU time 21.63 seconds
Started Aug 24 08:43:58 PM UTC 24
Finished Aug 24 08:44:21 PM UTC 24
Peak memory 230384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409627427 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1409627427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.730687582
Short name T676
Test name
Test status
Simulation time 208697414 ps
CPU time 2.92 seconds
Started Aug 24 08:43:58 PM UTC 24
Finished Aug 24 08:44:02 PM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730687582 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.730687582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.2144442337
Short name T671
Test name
Test status
Simulation time 35134118 ps
CPU time 3.22 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:01 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144442337 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2144442337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.4235279747
Short name T734
Test name
Test status
Simulation time 715511058 ps
CPU time 25.05 seconds
Started Aug 24 08:43:58 PM UTC 24
Finished Aug 24 08:44:25 PM UTC 24
Peak memory 238036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235279747 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4235279747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3510111855
Short name T692
Test name
Test status
Simulation time 5485726762 ps
CPU time 24.57 seconds
Started Aug 24 08:43:58 PM UTC 24
Finished Aug 24 08:44:24 PM UTC 24
Peak memory 238232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510111855 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_
token_digest.3510111855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.1335056249
Short name T722
Test name
Test status
Simulation time 830661612 ps
CPU time 21.06 seconds
Started Aug 24 08:43:58 PM UTC 24
Finished Aug 24 08:44:21 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335056249 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_tok
en_mux.1335056249
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1333924436
Short name T690
Test name
Test status
Simulation time 327597550 ps
CPU time 9.4 seconds
Started Aug 24 08:43:58 PM UTC 24
Finished Aug 24 08:44:09 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333924436 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1333924436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.1098554124
Short name T666
Test name
Test status
Simulation time 49914979 ps
CPU time 2.09 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:00 PM UTC 24
Peak memory 236168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098554124 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1098554124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.450103325
Short name T800
Test name
Test status
Simulation time 339852263 ps
CPU time 48.89 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:47 PM UTC 24
Peak memory 258724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450103325 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.450103325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.3852928621
Short name T694
Test name
Test status
Simulation time 132305791 ps
CPU time 11.66 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:44:10 PM UTC 24
Peak memory 262760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852928621 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3852928621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.750541402
Short name T873
Test name
Test status
Simulation time 25544538999 ps
CPU time 207.39 seconds
Started Aug 24 08:43:58 PM UTC 24
Finished Aug 24 08:47:29 PM UTC 24
Peak memory 285336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=750541402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.lc_ctrl_stress_all.750541402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1814922579
Short name T661
Test name
Test status
Simulation time 14650813 ps
CPU time 1.24 seconds
Started Aug 24 08:43:57 PM UTC 24
Finished Aug 24 08:43:59 PM UTC 24
Peak memory 222724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814922579 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_volatile_unlock_smoke.1814922579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3977819725
Short name T91
Test name
Test status
Simulation time 17160499 ps
CPU time 1.61 seconds
Started Aug 24 08:44:02 PM UTC 24
Finished Aug 24 08:44:05 PM UTC 24
Peak memory 218752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977819725 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3977819725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3671642418
Short name T712
Test name
Test status
Simulation time 443749063 ps
CPU time 13.88 seconds
Started Aug 24 08:44:01 PM UTC 24
Finished Aug 24 08:44:16 PM UTC 24
Peak memory 232432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671642418 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3671642418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.296830149
Short name T726
Test name
Test status
Simulation time 2366796762 ps
CPU time 18.98 seconds
Started Aug 24 08:44:01 PM UTC 24
Finished Aug 24 08:44:21 PM UTC 24
Peak memory 229916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296830149 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.296830149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.2556317322
Short name T683
Test name
Test status
Simulation time 262750356 ps
CPU time 3.72 seconds
Started Aug 24 08:44:01 PM UTC 24
Finished Aug 24 08:44:06 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556317322 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2556317322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.3637960763
Short name T713
Test name
Test status
Simulation time 404155377 ps
CPU time 14.38 seconds
Started Aug 24 08:44:01 PM UTC 24
Finished Aug 24 08:44:17 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637960763 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3637960763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3648758916
Short name T650
Test name
Test status
Simulation time 573907823 ps
CPU time 20.96 seconds
Started Aug 24 08:44:02 PM UTC 24
Finished Aug 24 08:44:25 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648758916 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_
token_digest.3648758916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.85756422
Short name T716
Test name
Test status
Simulation time 335531579 ps
CPU time 13.75 seconds
Started Aug 24 08:44:02 PM UTC 24
Finished Aug 24 08:44:17 PM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85756422 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token
_mux.85756422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.3864046501
Short name T698
Test name
Test status
Simulation time 190459764 ps
CPU time 9.02 seconds
Started Aug 24 08:44:01 PM UTC 24
Finished Aug 24 08:44:11 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864046501 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3864046501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.3750173765
Short name T677
Test name
Test status
Simulation time 165760105 ps
CPU time 2.12 seconds
Started Aug 24 08:44:00 PM UTC 24
Finished Aug 24 08:44:03 PM UTC 24
Peak memory 225836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750173765 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3750173765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3937809419
Short name T771
Test name
Test status
Simulation time 4344854799 ps
CPU time 34.53 seconds
Started Aug 24 08:44:01 PM UTC 24
Finished Aug 24 08:44:37 PM UTC 24
Peak memory 262812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937809419 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3937809419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3856621843
Short name T697
Test name
Test status
Simulation time 515468808 ps
CPU time 8.89 seconds
Started Aug 24 08:44:01 PM UTC 24
Finished Aug 24 08:44:11 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856621843 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3856621843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1171606277
Short name T871
Test name
Test status
Simulation time 5209242601 ps
CPU time 198.58 seconds
Started Aug 24 08:44:02 PM UTC 24
Finished Aug 24 08:47:24 PM UTC 24
Peak memory 280504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1171606277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 37.lc_ctrl_stress_all.1171606277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2971116581
Short name T674
Test name
Test status
Simulation time 14276941 ps
CPU time 1.3 seconds
Started Aug 24 08:44:00 PM UTC 24
Finished Aug 24 08:44:02 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971116581 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_volatile_unlock_smoke.2971116581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.898910693
Short name T700
Test name
Test status
Simulation time 67906358 ps
CPU time 1.6 seconds
Started Aug 24 08:44:09 PM UTC 24
Finished Aug 24 08:44:11 PM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898910693 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.898910693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.3608100046
Short name T704
Test name
Test status
Simulation time 581826153 ps
CPU time 18.07 seconds
Started Aug 24 08:44:05 PM UTC 24
Finished Aug 24 08:44:24 PM UTC 24
Peak memory 232068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608100046 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3608100046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.292353914
Short name T744
Test name
Test status
Simulation time 10106011982 ps
CPU time 22.42 seconds
Started Aug 24 08:44:05 PM UTC 24
Finished Aug 24 08:44:29 PM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292353914 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.292353914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.4228319230
Short name T695
Test name
Test status
Simulation time 161411388 ps
CPU time 5.38 seconds
Started Aug 24 08:44:04 PM UTC 24
Finished Aug 24 08:44:10 PM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228319230 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.4228319230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2596197766
Short name T731
Test name
Test status
Simulation time 4534976289 ps
CPU time 16.37 seconds
Started Aug 24 08:44:06 PM UTC 24
Finished Aug 24 08:44:23 PM UTC 24
Peak memory 238220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596197766 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2596197766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.375453303
Short name T728
Test name
Test status
Simulation time 1504536034 ps
CPU time 13.33 seconds
Started Aug 24 08:44:07 PM UTC 24
Finished Aug 24 08:44:22 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375453303 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_t
oken_digest.375453303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.2468120281
Short name T720
Test name
Test status
Simulation time 2248085203 ps
CPU time 12.61 seconds
Started Aug 24 08:44:06 PM UTC 24
Finished Aug 24 08:44:20 PM UTC 24
Peak memory 238032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468120281 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_tok
en_mux.2468120281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2498711696
Short name T714
Test name
Test status
Simulation time 785893839 ps
CPU time 11.13 seconds
Started Aug 24 08:44:05 PM UTC 24
Finished Aug 24 08:44:17 PM UTC 24
Peak memory 232084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498711696 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2498711696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.204722468
Short name T705
Test name
Test status
Simulation time 155240185 ps
CPU time 10.31 seconds
Started Aug 24 08:44:02 PM UTC 24
Finished Aug 24 08:44:14 PM UTC 24
Peak memory 229948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204722468 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.204722468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.773030114
Short name T795
Test name
Test status
Simulation time 3766999297 ps
CPU time 40.93 seconds
Started Aug 24 08:44:04 PM UTC 24
Finished Aug 24 08:44:46 PM UTC 24
Peak memory 263080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773030114 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.773030114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3464348309
Short name T707
Test name
Test status
Simulation time 267091241 ps
CPU time 9.45 seconds
Started Aug 24 08:44:04 PM UTC 24
Finished Aug 24 08:44:14 PM UTC 24
Peak memory 256872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464348309 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3464348309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1154779541
Short name T682
Test name
Test status
Simulation time 13993584 ps
CPU time 1.39 seconds
Started Aug 24 08:44:03 PM UTC 24
Finished Aug 24 08:44:05 PM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154779541 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_volatile_unlock_smoke.1154779541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2050214184
Short name T709
Test name
Test status
Simulation time 101723398 ps
CPU time 1.21 seconds
Started Aug 24 08:44:13 PM UTC 24
Finished Aug 24 08:44:15 PM UTC 24
Peak memory 216928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050214184 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2050214184
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.4153535601
Short name T719
Test name
Test status
Simulation time 234964144 ps
CPU time 6 seconds
Started Aug 24 08:44:11 PM UTC 24
Finished Aug 24 08:44:18 PM UTC 24
Peak memory 229804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153535601 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_acce
ss.4153535601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.4025616913
Short name T711
Test name
Test status
Simulation time 196799469 ps
CPU time 4.27 seconds
Started Aug 24 08:44:10 PM UTC 24
Finished Aug 24 08:44:15 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025616913 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4025616913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1034071673
Short name T776
Test name
Test status
Simulation time 874937357 ps
CPU time 25.88 seconds
Started Aug 24 08:44:11 PM UTC 24
Finished Aug 24 08:44:39 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034071673 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1034071673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.1573302424
Short name T738
Test name
Test status
Simulation time 955591694 ps
CPU time 13.04 seconds
Started Aug 24 08:44:11 PM UTC 24
Finished Aug 24 08:44:25 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573302424 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_
token_digest.1573302424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.3386462297
Short name T750
Test name
Test status
Simulation time 358734591 ps
CPU time 17.41 seconds
Started Aug 24 08:44:11 PM UTC 24
Finished Aug 24 08:44:30 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386462297 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_tok
en_mux.3386462297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2474551992
Short name T733
Test name
Test status
Simulation time 1599194461 ps
CPU time 12.6 seconds
Started Aug 24 08:44:10 PM UTC 24
Finished Aug 24 08:44:24 PM UTC 24
Peak memory 232272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474551992 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2474551992
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3514001989
Short name T703
Test name
Test status
Simulation time 48254435 ps
CPU time 2.59 seconds
Started Aug 24 08:44:09 PM UTC 24
Finished Aug 24 08:44:12 PM UTC 24
Peak memory 226032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514001989 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3514001989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.2270815487
Short name T829
Test name
Test status
Simulation time 268892934 ps
CPU time 44.98 seconds
Started Aug 24 08:44:10 PM UTC 24
Finished Aug 24 08:44:57 PM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270815487 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2270815487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.4294356261
Short name T729
Test name
Test status
Simulation time 452763133 ps
CPU time 10.21 seconds
Started Aug 24 08:44:10 PM UTC 24
Finished Aug 24 08:44:22 PM UTC 24
Peak memory 262656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294356261 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4294356261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.1306872813
Short name T833
Test name
Test status
Simulation time 7145733549 ps
CPU time 97.54 seconds
Started Aug 24 08:44:13 PM UTC 24
Finished Aug 24 08:45:52 PM UTC 24
Peak memory 287372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1306872813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 39.lc_ctrl_stress_all.1306872813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1951175419
Short name T187
Test name
Test status
Simulation time 3250553499 ps
CPU time 103.18 seconds
Started Aug 24 08:44:13 PM UTC 24
Finished Aug 24 08:45:58 PM UTC 24
Peak memory 279316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951175419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1951175419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3032079907
Short name T699
Test name
Test status
Simulation time 15524889 ps
CPU time 1.41 seconds
Started Aug 24 08:44:09 PM UTC 24
Finished Aug 24 08:44:11 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032079907 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_volatile_unlock_smoke.3032079907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.845184054
Short name T55
Test name
Test status
Simulation time 22386853 ps
CPU time 1.46 seconds
Started Aug 24 08:41:24 PM UTC 24
Finished Aug 24 08:41:26 PM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845184054 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.845184054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2312300450
Short name T86
Test name
Test status
Simulation time 42571846 ps
CPU time 1.2 seconds
Started Aug 24 08:41:19 PM UTC 24
Finished Aug 24 08:41:22 PM UTC 24
Peak memory 218048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312300450 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2312300450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.1240590999
Short name T292
Test name
Test status
Simulation time 333591149 ps
CPU time 18.34 seconds
Started Aug 24 08:41:19 PM UTC 24
Finished Aug 24 08:41:39 PM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240590999 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1240590999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.3583505224
Short name T48
Test name
Test status
Simulation time 3358121294 ps
CPU time 10.67 seconds
Started Aug 24 08:41:21 PM UTC 24
Finished Aug 24 08:41:33 PM UTC 24
Peak memory 230148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583505224 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3583505224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2422183817
Short name T106
Test name
Test status
Simulation time 1159061581 ps
CPU time 28.85 seconds
Started Aug 24 08:41:21 PM UTC 24
Finished Aug 24 08:41:52 PM UTC 24
Peak memory 232104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422183817
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_errors.2422183817
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.309325049
Short name T287
Test name
Test status
Simulation time 432603019 ps
CPU time 13.27 seconds
Started Aug 24 08:41:21 PM UTC 24
Finished Aug 24 08:41:36 PM UTC 24
Peak memory 229956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309325049 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_prio
rity.309325049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.1192006707
Short name T318
Test name
Test status
Simulation time 1096225932 ps
CPU time 33.82 seconds
Started Aug 24 08:41:20 PM UTC 24
Finished Aug 24 08:41:56 PM UTC 24
Peak memory 237244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192006707
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_jtag_prog_failure.1192006707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1227359849
Short name T315
Test name
Test status
Simulation time 19483702149 ps
CPU time 30.82 seconds
Started Aug 24 08:41:21 PM UTC 24
Finished Aug 24 08:41:54 PM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227359849
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.l
c_ctrl_jtag_regwen_during_op.1227359849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.1965410949
Short name T277
Test name
Test status
Simulation time 706314390 ps
CPU time 12.55 seconds
Started Aug 24 08:41:20 PM UTC 24
Finished Aug 24 08:41:34 PM UTC 24
Peak memory 229764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965410949
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_smoke.1965410949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2994155369
Short name T597
Test name
Test status
Simulation time 6448446101 ps
CPU time 139.27 seconds
Started Aug 24 08:41:20 PM UTC 24
Finished Aug 24 08:43:42 PM UTC 24
Peak memory 295648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994155369
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_c
trl_jtag_state_failure.2994155369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.639546709
Short name T261
Test name
Test status
Simulation time 1515546299 ps
CPU time 20.3 seconds
Started Aug 24 08:41:20 PM UTC 24
Finished Aug 24 08:41:42 PM UTC 24
Peak memory 262948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639546709
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc
_ctrl_jtag_state_post_trans.639546709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2942878478
Short name T240
Test name
Test status
Simulation time 384218971 ps
CPU time 27.77 seconds
Started Aug 24 08:41:19 PM UTC 24
Finished Aug 24 08:41:48 PM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942878478 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2942878478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.872719173
Short name T133
Test name
Test status
Simulation time 410528931 ps
CPU time 56.13 seconds
Started Aug 24 08:41:24 PM UTC 24
Finished Aug 24 08:42:22 PM UTC 24
Peak memory 292100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872719173 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.872719173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2568997415
Short name T272
Test name
Test status
Simulation time 2761983332 ps
CPU time 23.7 seconds
Started Aug 24 08:41:21 PM UTC 24
Finished Aug 24 08:41:47 PM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568997415 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2568997415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2522217748
Short name T291
Test name
Test status
Simulation time 1925617006 ps
CPU time 14.69 seconds
Started Aug 24 08:41:23 PM UTC 24
Finished Aug 24 08:41:39 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522217748 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_t
oken_digest.2522217748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1925617447
Short name T285
Test name
Test status
Simulation time 299842676 ps
CPU time 12.61 seconds
Started Aug 24 08:41:22 PM UTC 24
Finished Aug 24 08:41:35 PM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925617447 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_toke
n_mux.1925617447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.1388507901
Short name T77
Test name
Test status
Simulation time 7753726506 ps
CPU time 14.19 seconds
Started Aug 24 08:41:19 PM UTC 24
Finished Aug 24 08:41:35 PM UTC 24
Peak memory 231620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388507901 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1388507901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.2600908090
Short name T31
Test name
Test status
Simulation time 136856532 ps
CPU time 4.43 seconds
Started Aug 24 08:41:18 PM UTC 24
Finished Aug 24 08:41:24 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600908090 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2600908090
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2895716137
Short name T263
Test name
Test status
Simulation time 274464231 ps
CPU time 33.41 seconds
Started Aug 24 08:41:18 PM UTC 24
Finished Aug 24 08:41:53 PM UTC 24
Peak memory 263064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895716137 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2895716137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1375738336
Short name T54
Test name
Test status
Simulation time 215974121 ps
CPU time 3.75 seconds
Started Aug 24 08:41:18 PM UTC 24
Finished Aug 24 08:41:23 PM UTC 24
Peak memory 232264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375738336 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1375738336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3486305751
Short name T483
Test name
Test status
Simulation time 9362538834 ps
CPU time 97.57 seconds
Started Aug 24 08:41:23 PM UTC 24
Finished Aug 24 08:43:02 PM UTC 24
Peak memory 237952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3486305751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 4.lc_ctrl_stress_all.3486305751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.242137108
Short name T109
Test name
Test status
Simulation time 2464978039 ps
CPU time 48.17 seconds
Started Aug 24 08:41:24 PM UTC 24
Finished Aug 24 08:42:14 PM UTC 24
Peak memory 262924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242137108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.242137108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3508912587
Short name T32
Test name
Test status
Simulation time 27560403 ps
CPU time 1.25 seconds
Started Aug 24 08:41:18 PM UTC 24
Finished Aug 24 08:41:21 PM UTC 24
Peak memory 222264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508912587 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_volatile_unlock_smoke.3508912587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1236385693
Short name T725
Test name
Test status
Simulation time 20813843 ps
CPU time 1.65 seconds
Started Aug 24 08:44:19 PM UTC 24
Finished Aug 24 08:44:21 PM UTC 24
Peak memory 218692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236385693 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1236385693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.3102621312
Short name T757
Test name
Test status
Simulation time 1597719995 ps
CPU time 16.81 seconds
Started Aug 24 08:44:15 PM UTC 24
Finished Aug 24 08:44:33 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102621312 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3102621312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.635774464
Short name T741
Test name
Test status
Simulation time 296394675 ps
CPU time 10.75 seconds
Started Aug 24 08:44:15 PM UTC 24
Finished Aug 24 08:44:27 PM UTC 24
Peak memory 229932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635774464 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.635774464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.3124715289
Short name T721
Test name
Test status
Simulation time 82313149 ps
CPU time 4.4 seconds
Started Aug 24 08:44:15 PM UTC 24
Finished Aug 24 08:44:20 PM UTC 24
Peak memory 230504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124715289 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3124715289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.206017752
Short name T797
Test name
Test status
Simulation time 764404538 ps
CPU time 29.36 seconds
Started Aug 24 08:44:16 PM UTC 24
Finished Aug 24 08:44:47 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206017752 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.206017752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3793944289
Short name T763
Test name
Test status
Simulation time 582938952 ps
CPU time 17.21 seconds
Started Aug 24 08:44:16 PM UTC 24
Finished Aug 24 08:44:35 PM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793944289 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_
token_digest.3793944289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.1281876730
Short name T764
Test name
Test status
Simulation time 431126776 ps
CPU time 17.51 seconds
Started Aug 24 08:44:16 PM UTC 24
Finished Aug 24 08:44:35 PM UTC 24
Peak memory 237968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281876730 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_tok
en_mux.1281876730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.2380687746
Short name T742
Test name
Test status
Simulation time 833859593 ps
CPU time 11.29 seconds
Started Aug 24 08:44:15 PM UTC 24
Finished Aug 24 08:44:27 PM UTC 24
Peak memory 236756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380687746 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2380687746
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.2285981482
Short name T718
Test name
Test status
Simulation time 62733103 ps
CPU time 4.52 seconds
Started Aug 24 08:44:13 PM UTC 24
Finished Aug 24 08:44:18 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285981482 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2285981482
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.272596488
Short name T810
Test name
Test status
Simulation time 1013664398 ps
CPU time 35.48 seconds
Started Aug 24 08:44:14 PM UTC 24
Finished Aug 24 08:44:51 PM UTC 24
Peak memory 260692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272596488 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.272596488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.4157755797
Short name T748
Test name
Test status
Simulation time 74875478 ps
CPU time 13.73 seconds
Started Aug 24 08:44:15 PM UTC 24
Finished Aug 24 08:44:30 PM UTC 24
Peak memory 261032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157755797 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.4157755797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.3497631586
Short name T232
Test name
Test status
Simulation time 3186498445 ps
CPU time 93.54 seconds
Started Aug 24 08:44:17 PM UTC 24
Finished Aug 24 08:45:53 PM UTC 24
Peak memory 289464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3497631586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 40.lc_ctrl_stress_all.3497631586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2638211675
Short name T710
Test name
Test status
Simulation time 21815327 ps
CPU time 1.56 seconds
Started Aug 24 08:44:13 PM UTC 24
Finished Aug 24 08:44:15 PM UTC 24
Peak memory 222908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638211675 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_volatile_unlock_smoke.2638211675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.3064472377
Short name T737
Test name
Test status
Simulation time 23097911 ps
CPU time 1.79 seconds
Started Aug 24 08:44:23 PM UTC 24
Finished Aug 24 08:44:25 PM UTC 24
Peak memory 218692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064472377 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3064472377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.668051180
Short name T782
Test name
Test status
Simulation time 1471128076 ps
CPU time 20.04 seconds
Started Aug 24 08:44:20 PM UTC 24
Finished Aug 24 08:44:41 PM UTC 24
Peak memory 237968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668051180 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.668051180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.259186475
Short name T759
Test name
Test status
Simulation time 1402389473 ps
CPU time 10.85 seconds
Started Aug 24 08:44:21 PM UTC 24
Finished Aug 24 08:44:33 PM UTC 24
Peak memory 229852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259186475 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.259186475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1075235847
Short name T730
Test name
Test status
Simulation time 50778130 ps
CPU time 2.08 seconds
Started Aug 24 08:44:20 PM UTC 24
Finished Aug 24 08:44:23 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075235847 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1075235847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.1588257686
Short name T765
Test name
Test status
Simulation time 250466010 ps
CPU time 12.37 seconds
Started Aug 24 08:44:21 PM UTC 24
Finished Aug 24 08:44:35 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588257686 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1588257686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.1915612565
Short name T769
Test name
Test status
Simulation time 1551411369 ps
CPU time 12.62 seconds
Started Aug 24 08:44:23 PM UTC 24
Finished Aug 24 08:44:36 PM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915612565 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_
token_digest.1915612565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.4209682106
Short name T807
Test name
Test status
Simulation time 1645947860 ps
CPU time 24.73 seconds
Started Aug 24 08:44:22 PM UTC 24
Finished Aug 24 08:44:49 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209682106 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_tok
en_mux.4209682106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.1676893266
Short name T767
Test name
Test status
Simulation time 1445661585 ps
CPU time 13.81 seconds
Started Aug 24 08:44:21 PM UTC 24
Finished Aug 24 08:44:36 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676893266 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1676893266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.227609571
Short name T727
Test name
Test status
Simulation time 14309737 ps
CPU time 1.71 seconds
Started Aug 24 08:44:19 PM UTC 24
Finished Aug 24 08:44:21 PM UTC 24
Peak memory 222736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227609571 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.227609571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.353794055
Short name T234
Test name
Test status
Simulation time 340963872 ps
CPU time 40.86 seconds
Started Aug 24 08:44:19 PM UTC 24
Finished Aug 24 08:45:01 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353794055 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.353794055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.3832224461
Short name T753
Test name
Test status
Simulation time 214071390 ps
CPU time 9.27 seconds
Started Aug 24 08:44:20 PM UTC 24
Finished Aug 24 08:44:30 PM UTC 24
Peak memory 260712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832224461 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3832224461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2384101333
Short name T862
Test name
Test status
Simulation time 2602578985 ps
CPU time 111.31 seconds
Started Aug 24 08:44:23 PM UTC 24
Finished Aug 24 08:46:16 PM UTC 24
Peak memory 263100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2384101333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 41.lc_ctrl_stress_all.2384101333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2649948425
Short name T217
Test name
Test status
Simulation time 1979986570 ps
CPU time 96.27 seconds
Started Aug 24 08:44:23 PM UTC 24
Finished Aug 24 08:46:01 PM UTC 24
Peak memory 281308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649948425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2649948425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3206746098
Short name T723
Test name
Test status
Simulation time 13927512 ps
CPU time 1.41 seconds
Started Aug 24 08:44:19 PM UTC 24
Finished Aug 24 08:44:21 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206746098 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_volatile_unlock_smoke.3206746098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.811495016
Short name T746
Test name
Test status
Simulation time 21605399 ps
CPU time 1.32 seconds
Started Aug 24 08:44:27 PM UTC 24
Finished Aug 24 08:44:29 PM UTC 24
Peak memory 218836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811495016 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.811495016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1366189022
Short name T786
Test name
Test status
Simulation time 1797386944 ps
CPU time 16.01 seconds
Started Aug 24 08:44:25 PM UTC 24
Finished Aug 24 08:44:42 PM UTC 24
Peak memory 230120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366189022 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1366189022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.3625159093
Short name T777
Test name
Test status
Simulation time 1640346014 ps
CPU time 12.62 seconds
Started Aug 24 08:44:25 PM UTC 24
Finished Aug 24 08:44:39 PM UTC 24
Peak memory 230080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625159093 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_acce
ss.3625159093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.312907776
Short name T749
Test name
Test status
Simulation time 98946904 ps
CPU time 3.81 seconds
Started Aug 24 08:44:25 PM UTC 24
Finished Aug 24 08:44:30 PM UTC 24
Peak memory 232008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312907776 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.312907776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.2889002690
Short name T796
Test name
Test status
Simulation time 312634115 ps
CPU time 18.59 seconds
Started Aug 24 08:44:26 PM UTC 24
Finished Aug 24 08:44:46 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889002690 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2889002690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.3875904794
Short name T809
Test name
Test status
Simulation time 1394526710 ps
CPU time 21.38 seconds
Started Aug 24 08:44:26 PM UTC 24
Finished Aug 24 08:44:49 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875904794 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_
token_digest.3875904794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1934849257
Short name T778
Test name
Test status
Simulation time 200494301 ps
CPU time 11.21 seconds
Started Aug 24 08:44:26 PM UTC 24
Finished Aug 24 08:44:39 PM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934849257 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_tok
en_mux.1934849257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.1822412011
Short name T785
Test name
Test status
Simulation time 1742198381 ps
CPU time 15.75 seconds
Started Aug 24 08:44:25 PM UTC 24
Finished Aug 24 08:44:42 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822412011 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1822412011
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.2817507525
Short name T739
Test name
Test status
Simulation time 21956395 ps
CPU time 1.98 seconds
Started Aug 24 08:44:23 PM UTC 24
Finished Aug 24 08:44:26 PM UTC 24
Peak memory 235016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817507525 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2817507525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.1252416453
Short name T838
Test name
Test status
Simulation time 252364508 ps
CPU time 39.19 seconds
Started Aug 24 08:44:24 PM UTC 24
Finished Aug 24 08:45:04 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252416453 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1252416453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.369163427
Short name T770
Test name
Test status
Simulation time 443013076 ps
CPU time 10.43 seconds
Started Aug 24 08:44:25 PM UTC 24
Finished Aug 24 08:44:37 PM UTC 24
Peak memory 262588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369163427 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.369163427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.4196665411
Short name T766
Test name
Test status
Simulation time 293414123 ps
CPU time 8.4 seconds
Started Aug 24 08:44:27 PM UTC 24
Finished Aug 24 08:44:36 PM UTC 24
Peak memory 230328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4196665411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 42.lc_ctrl_stress_all.4196665411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1554387596
Short name T736
Test name
Test status
Simulation time 35826732 ps
CPU time 1.24 seconds
Started Aug 24 08:44:23 PM UTC 24
Finished Aug 24 08:44:25 PM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554387596 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_volatile_unlock_smoke.1554387596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.4227576803
Short name T761
Test name
Test status
Simulation time 152454802 ps
CPU time 1.68 seconds
Started Aug 24 08:44:31 PM UTC 24
Finished Aug 24 08:44:34 PM UTC 24
Peak memory 217796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227576803 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4227576803
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2292760351
Short name T755
Test name
Test status
Simulation time 2798148971 ps
CPU time 19.78 seconds
Started Aug 24 08:44:29 PM UTC 24
Finished Aug 24 08:44:50 PM UTC 24
Peak memory 237952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292760351 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2292760351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.811137551
Short name T768
Test name
Test status
Simulation time 246080392 ps
CPU time 5.25 seconds
Started Aug 24 08:44:30 PM UTC 24
Finished Aug 24 08:44:36 PM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811137551 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.811137551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.3438861070
Short name T756
Test name
Test status
Simulation time 31197970 ps
CPU time 3.02 seconds
Started Aug 24 08:44:29 PM UTC 24
Finished Aug 24 08:44:33 PM UTC 24
Peak memory 234024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438861070 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3438861070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.618836335
Short name T794
Test name
Test status
Simulation time 1108899205 ps
CPU time 14.42 seconds
Started Aug 24 08:44:30 PM UTC 24
Finished Aug 24 08:44:46 PM UTC 24
Peak memory 232068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618836335 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.618836335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2924202836
Short name T791
Test name
Test status
Simulation time 309384395 ps
CPU time 11.13 seconds
Started Aug 24 08:44:31 PM UTC 24
Finished Aug 24 08:44:44 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924202836 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_
token_digest.2924202836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.2897689451
Short name T789
Test name
Test status
Simulation time 271809176 ps
CPU time 11.74 seconds
Started Aug 24 08:44:30 PM UTC 24
Finished Aug 24 08:44:43 PM UTC 24
Peak memory 237680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897689451 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_tok
en_mux.2897689451
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2082122153
Short name T781
Test name
Test status
Simulation time 2384077251 ps
CPU time 9.93 seconds
Started Aug 24 08:44:30 PM UTC 24
Finished Aug 24 08:44:41 PM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082122153 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2082122153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1501744364
Short name T752
Test name
Test status
Simulation time 147960198 ps
CPU time 2.58 seconds
Started Aug 24 08:44:27 PM UTC 24
Finished Aug 24 08:44:30 PM UTC 24
Peak memory 225904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501744364 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1501744364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3816175869
Short name T851
Test name
Test status
Simulation time 294010819 ps
CPU time 49.96 seconds
Started Aug 24 08:44:28 PM UTC 24
Finished Aug 24 08:45:19 PM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816175869 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3816175869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.803136368
Short name T762
Test name
Test status
Simulation time 228750952 ps
CPU time 4.53 seconds
Started Aug 24 08:44:29 PM UTC 24
Finished Aug 24 08:44:34 PM UTC 24
Peak memory 234320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803136368 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.803136368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.320903887
Short name T861
Test name
Test status
Simulation time 4426608045 ps
CPU time 102.2 seconds
Started Aug 24 08:44:31 PM UTC 24
Finished Aug 24 08:46:16 PM UTC 24
Peak memory 285336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=320903887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.lc_ctrl_stress_all.320903887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.710576886
Short name T199
Test name
Test status
Simulation time 1348663986 ps
CPU time 54.38 seconds
Started Aug 24 08:44:31 PM UTC 24
Finished Aug 24 08:45:28 PM UTC 24
Peak memory 238100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710576886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.710576886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.272509474
Short name T747
Test name
Test status
Simulation time 26652005 ps
CPU time 1.32 seconds
Started Aug 24 08:44:27 PM UTC 24
Finished Aug 24 08:44:29 PM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272509474 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.lc_ctrl_volatile_unlock_smoke.272509474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1523562128
Short name T775
Test name
Test status
Simulation time 25882025 ps
CPU time 1.26 seconds
Started Aug 24 08:44:36 PM UTC 24
Finished Aug 24 08:44:38 PM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523562128 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1523562128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2771596759
Short name T805
Test name
Test status
Simulation time 1183742980 ps
CPU time 12.12 seconds
Started Aug 24 08:44:34 PM UTC 24
Finished Aug 24 08:44:48 PM UTC 24
Peak memory 232364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771596759 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2771596759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.826822889
Short name T780
Test name
Test status
Simulation time 121459555 ps
CPU time 4.94 seconds
Started Aug 24 08:44:34 PM UTC 24
Finished Aug 24 08:44:40 PM UTC 24
Peak memory 229876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826822889 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.826822889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1323515389
Short name T773
Test name
Test status
Simulation time 95912516 ps
CPU time 2.35 seconds
Started Aug 24 08:44:34 PM UTC 24
Finished Aug 24 08:44:38 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323515389 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1323515389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.3704258976
Short name T811
Test name
Test status
Simulation time 579530397 ps
CPU time 15.52 seconds
Started Aug 24 08:44:34 PM UTC 24
Finished Aug 24 08:44:51 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704258976 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3704258976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.925092395
Short name T799
Test name
Test status
Simulation time 201888144 ps
CPU time 12.76 seconds
Started Aug 24 08:44:36 PM UTC 24
Finished Aug 24 08:44:50 PM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925092395 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_t
oken_digest.925092395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1021457057
Short name T803
Test name
Test status
Simulation time 235984225 ps
CPU time 10.54 seconds
Started Aug 24 08:44:35 PM UTC 24
Finished Aug 24 08:44:47 PM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021457057 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_tok
en_mux.1021457057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2656052779
Short name T801
Test name
Test status
Simulation time 296623719 ps
CPU time 11.72 seconds
Started Aug 24 08:44:34 PM UTC 24
Finished Aug 24 08:44:47 PM UTC 24
Peak memory 237028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656052779 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2656052779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.3925476993
Short name T772
Test name
Test status
Simulation time 752633182 ps
CPU time 4.81 seconds
Started Aug 24 08:44:31 PM UTC 24
Finished Aug 24 08:44:38 PM UTC 24
Peak memory 229076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925476993 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3925476993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.3799752709
Short name T849
Test name
Test status
Simulation time 188439052 ps
CPU time 39.77 seconds
Started Aug 24 08:44:32 PM UTC 24
Finished Aug 24 08:45:14 PM UTC 24
Peak memory 262944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799752709 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3799752709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.1373942229
Short name T808
Test name
Test status
Simulation time 102596328 ps
CPU time 13.83 seconds
Started Aug 24 08:44:34 PM UTC 24
Finished Aug 24 08:44:49 PM UTC 24
Peak memory 262760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373942229 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1373942229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.506906948
Short name T130
Test name
Test status
Simulation time 80564642653 ps
CPU time 244.67 seconds
Started Aug 24 08:44:36 PM UTC 24
Finished Aug 24 08:48:44 PM UTC 24
Peak memory 273120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=506906948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.lc_ctrl_stress_all.506906948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.579636953
Short name T188
Test name
Test status
Simulation time 43716288561 ps
CPU time 74.22 seconds
Started Aug 24 08:44:36 PM UTC 24
Finished Aug 24 08:45:52 PM UTC 24
Peak memory 262924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579636953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.579636953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1816878996
Short name T760
Test name
Test status
Simulation time 22203009 ps
CPU time 1.26 seconds
Started Aug 24 08:44:31 PM UTC 24
Finished Aug 24 08:44:34 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816878996 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_volatile_unlock_smoke.1816878996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2359124093
Short name T784
Test name
Test status
Simulation time 60079382 ps
CPU time 1.31 seconds
Started Aug 24 08:44:39 PM UTC 24
Finished Aug 24 08:44:42 PM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359124093 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2359124093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.1710393624
Short name T816
Test name
Test status
Simulation time 203927191 ps
CPU time 12.32 seconds
Started Aug 24 08:44:38 PM UTC 24
Finished Aug 24 08:44:52 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710393624 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1710393624
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.73997047
Short name T792
Test name
Test status
Simulation time 406274526 ps
CPU time 4.69 seconds
Started Aug 24 08:44:38 PM UTC 24
Finished Aug 24 08:44:44 PM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73997047 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.73997047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1399308037
Short name T783
Test name
Test status
Simulation time 68778946 ps
CPU time 3.2 seconds
Started Aug 24 08:44:37 PM UTC 24
Finished Aug 24 08:44:41 PM UTC 24
Peak memory 236544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399308037 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1399308037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.3704036472
Short name T235
Test name
Test status
Simulation time 3046494281 ps
CPU time 20.4 seconds
Started Aug 24 08:44:39 PM UTC 24
Finished Aug 24 08:45:01 PM UTC 24
Peak memory 231796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704036472 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3704036472
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.323219239
Short name T824
Test name
Test status
Simulation time 4393030534 ps
CPU time 13.96 seconds
Started Aug 24 08:44:39 PM UTC 24
Finished Aug 24 08:44:55 PM UTC 24
Peak memory 236532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323219239 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_t
oken_digest.323219239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.1453232143
Short name T812
Test name
Test status
Simulation time 331597309 ps
CPU time 10.49 seconds
Started Aug 24 08:44:39 PM UTC 24
Finished Aug 24 08:44:51 PM UTC 24
Peak memory 232096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453232143 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_tok
en_mux.1453232143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.1085408970
Short name T819
Test name
Test status
Simulation time 273634477 ps
CPU time 14.13 seconds
Started Aug 24 08:44:38 PM UTC 24
Finished Aug 24 08:44:54 PM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085408970 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1085408970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.386542259
Short name T788
Test name
Test status
Simulation time 469284692 ps
CPU time 5.43 seconds
Started Aug 24 08:44:36 PM UTC 24
Finished Aug 24 08:44:43 PM UTC 24
Peak memory 225768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386542259 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.386542259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.3287712424
Short name T840
Test name
Test status
Simulation time 727202253 ps
CPU time 26.5 seconds
Started Aug 24 08:44:37 PM UTC 24
Finished Aug 24 08:45:05 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287712424 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3287712424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.119511950
Short name T806
Test name
Test status
Simulation time 151148242 ps
CPU time 9.8 seconds
Started Aug 24 08:44:37 PM UTC 24
Finished Aug 24 08:44:48 PM UTC 24
Peak memory 260780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119511950 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.119511950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2584763729
Short name T864
Test name
Test status
Simulation time 6991862615 ps
CPU time 104.89 seconds
Started Aug 24 08:44:39 PM UTC 24
Finished Aug 24 08:46:26 PM UTC 24
Peak memory 294812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2584763729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 45.lc_ctrl_stress_all.2584763729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3602212265
Short name T859
Test name
Test status
Simulation time 10248563799 ps
CPU time 55.84 seconds
Started Aug 24 08:44:39 PM UTC 24
Finished Aug 24 08:45:37 PM UTC 24
Peak memory 287504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602212265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.3602212265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3036570024
Short name T779
Test name
Test status
Simulation time 12367714 ps
CPU time 1.22 seconds
Started Aug 24 08:44:37 PM UTC 24
Finished Aug 24 08:44:39 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036570024 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_volatile_unlock_smoke.3036570024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2633367061
Short name T798
Test name
Test status
Simulation time 117093777 ps
CPU time 1.19 seconds
Started Aug 24 08:44:45 PM UTC 24
Finished Aug 24 08:44:47 PM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633367061 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2633367061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2069790512
Short name T122
Test name
Test status
Simulation time 495375103 ps
CPU time 24.97 seconds
Started Aug 24 08:44:43 PM UTC 24
Finished Aug 24 08:45:10 PM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069790512 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2069790512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3390786058
Short name T230
Test name
Test status
Simulation time 6960749542 ps
CPU time 15.61 seconds
Started Aug 24 08:44:43 PM UTC 24
Finished Aug 24 08:45:00 PM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390786058 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_acce
ss.3390786058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.2728790359
Short name T817
Test name
Test status
Simulation time 148822725 ps
CPU time 7.75 seconds
Started Aug 24 08:44:43 PM UTC 24
Finished Aug 24 08:44:52 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728790359 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2728790359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.3248448324
Short name T831
Test name
Test status
Simulation time 835642647 ps
CPU time 12.52 seconds
Started Aug 24 08:44:43 PM UTC 24
Finished Aug 24 08:44:57 PM UTC 24
Peak memory 232424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248448324 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3248448324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.272729944
Short name T839
Test name
Test status
Simulation time 406753371 ps
CPU time 19.63 seconds
Started Aug 24 08:44:43 PM UTC 24
Finished Aug 24 08:45:04 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272729944 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_t
oken_digest.272729944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.2809856765
Short name T228
Test name
Test status
Simulation time 1385634505 ps
CPU time 14.9 seconds
Started Aug 24 08:44:43 PM UTC 24
Finished Aug 24 08:44:59 PM UTC 24
Peak memory 237968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809856765 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_tok
en_mux.2809856765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1288913237
Short name T827
Test name
Test status
Simulation time 270089560 ps
CPU time 11.35 seconds
Started Aug 24 08:44:43 PM UTC 24
Finished Aug 24 08:44:56 PM UTC 24
Peak memory 232412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288913237 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1288913237
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1447234162
Short name T92
Test name
Test status
Simulation time 217110429 ps
CPU time 8.28 seconds
Started Aug 24 08:44:40 PM UTC 24
Finished Aug 24 08:44:50 PM UTC 24
Peak memory 229936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447234162 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1447234162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.3528116070
Short name T850
Test name
Test status
Simulation time 442347703 ps
CPU time 34.72 seconds
Started Aug 24 08:44:42 PM UTC 24
Finished Aug 24 08:45:18 PM UTC 24
Peak memory 260704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528116070 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3528116070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2950378921
Short name T832
Test name
Test status
Simulation time 39575754 ps
CPU time 12.9 seconds
Started Aug 24 08:44:43 PM UTC 24
Finished Aug 24 08:44:57 PM UTC 24
Peak memory 262724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950378921 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2950378921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3139404187
Short name T860
Test name
Test status
Simulation time 15887053869 ps
CPU time 61.05 seconds
Started Aug 24 08:44:45 PM UTC 24
Finished Aug 24 08:45:48 PM UTC 24
Peak memory 289420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3139404187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 46.lc_ctrl_stress_all.3139404187
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3079435498
Short name T867
Test name
Test status
Simulation time 18218328274 ps
CPU time 131.05 seconds
Started Aug 24 08:44:45 PM UTC 24
Finished Aug 24 08:46:58 PM UTC 24
Peak memory 281528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079435498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3079435498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.413794108
Short name T793
Test name
Test status
Simulation time 18097265 ps
CPU time 1.41 seconds
Started Aug 24 08:44:42 PM UTC 24
Finished Aug 24 08:44:44 PM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413794108 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.lc_ctrl_volatile_unlock_smoke.413794108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.59028881
Short name T815
Test name
Test status
Simulation time 66495745 ps
CPU time 1.43 seconds
Started Aug 24 08:44:49 PM UTC 24
Finished Aug 24 08:44:51 PM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59028881 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.59028881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.667240266
Short name T125
Test name
Test status
Simulation time 397966282 ps
CPU time 22.76 seconds
Started Aug 24 08:44:47 PM UTC 24
Finished Aug 24 08:45:11 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667240266 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.667240266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.907940359
Short name T823
Test name
Test status
Simulation time 739270311 ps
CPU time 4.2 seconds
Started Aug 24 08:44:49 PM UTC 24
Finished Aug 24 08:44:54 PM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907940359 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.907940359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.927600025
Short name T820
Test name
Test status
Simulation time 117467318 ps
CPU time 5.24 seconds
Started Aug 24 08:44:47 PM UTC 24
Finished Aug 24 08:44:54 PM UTC 24
Peak memory 236016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927600025 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.927600025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.394580324
Short name T848
Test name
Test status
Simulation time 1642295889 ps
CPU time 23.39 seconds
Started Aug 24 08:44:49 PM UTC 24
Finished Aug 24 08:45:14 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394580324 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.394580324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.415909451
Short name T236
Test name
Test status
Simulation time 963069093 ps
CPU time 11.26 seconds
Started Aug 24 08:44:49 PM UTC 24
Finished Aug 24 08:45:01 PM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415909451 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_t
oken_digest.415909451
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1350165668
Short name T835
Test name
Test status
Simulation time 409680694 ps
CPU time 11.32 seconds
Started Aug 24 08:44:49 PM UTC 24
Finished Aug 24 08:45:01 PM UTC 24
Peak memory 230128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350165668 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_tok
en_mux.1350165668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3715866259
Short name T233
Test name
Test status
Simulation time 272859331 ps
CPU time 12.31 seconds
Started Aug 24 08:44:47 PM UTC 24
Finished Aug 24 08:45:01 PM UTC 24
Peak memory 232144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715866259 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3715866259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3044495673
Short name T804
Test name
Test status
Simulation time 18034176 ps
CPU time 1.7 seconds
Started Aug 24 08:44:45 PM UTC 24
Finished Aug 24 08:44:48 PM UTC 24
Peak memory 232968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044495673 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3044495673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1532613441
Short name T853
Test name
Test status
Simulation time 921147092 ps
CPU time 37.51 seconds
Started Aug 24 08:44:45 PM UTC 24
Finished Aug 24 08:45:24 PM UTC 24
Peak memory 261028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532613441 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1532613441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.2191417246
Short name T813
Test name
Test status
Simulation time 323299592 ps
CPU time 4.31 seconds
Started Aug 24 08:44:46 PM UTC 24
Finished Aug 24 08:44:51 PM UTC 24
Peak memory 236772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191417246 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2191417246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.1046189697
Short name T131
Test name
Test status
Simulation time 16203064867 ps
CPU time 249.5 seconds
Started Aug 24 08:44:49 PM UTC 24
Finished Aug 24 08:49:02 PM UTC 24
Peak memory 237924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1046189697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 47.lc_ctrl_stress_all.1046189697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.81957568
Short name T802
Test name
Test status
Simulation time 16898476 ps
CPU time 1.27 seconds
Started Aug 24 08:44:45 PM UTC 24
Finished Aug 24 08:44:47 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81957568 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47
.lc_ctrl_volatile_unlock_smoke.81957568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.2757120168
Short name T826
Test name
Test status
Simulation time 24760110 ps
CPU time 1.72 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:44:55 PM UTC 24
Peak memory 218632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757120168 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2757120168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.576726568
Short name T123
Test name
Test status
Simulation time 1565089820 ps
CPU time 17.2 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:45:11 PM UTC 24
Peak memory 232216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576726568 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.576726568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2135410571
Short name T842
Test name
Test status
Simulation time 626044248 ps
CPU time 11.73 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:45:05 PM UTC 24
Peak memory 229824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135410571 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_acce
ss.2135410571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.2359537141
Short name T825
Test name
Test status
Simulation time 48510147 ps
CPU time 3.88 seconds
Started Aug 24 08:44:50 PM UTC 24
Finished Aug 24 08:44:55 PM UTC 24
Peak memory 231636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359537141 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2359537141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2239974333
Short name T121
Test name
Test status
Simulation time 276202625 ps
CPU time 15.93 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:45:10 PM UTC 24
Peak memory 232220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239974333 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2239974333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.962772949
Short name T846
Test name
Test status
Simulation time 278382203 ps
CPU time 14.04 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962772949 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_t
oken_digest.962772949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1363916093
Short name T845
Test name
Test status
Simulation time 5559811021 ps
CPU time 13.2 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:45:07 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363916093 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_tok
en_mux.1363916093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3257799996
Short name T847
Test name
Test status
Simulation time 5069590106 ps
CPU time 14.18 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 232292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257799996 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3257799996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.210311250
Short name T818
Test name
Test status
Simulation time 193868666 ps
CPU time 2.42 seconds
Started Aug 24 08:44:49 PM UTC 24
Finished Aug 24 08:44:52 PM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210311250 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.210311250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3877570654
Short name T854
Test name
Test status
Simulation time 1278239392 ps
CPU time 35.01 seconds
Started Aug 24 08:44:50 PM UTC 24
Finished Aug 24 08:45:27 PM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877570654 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3877570654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.921221776
Short name T231
Test name
Test status
Simulation time 231404267 ps
CPU time 9 seconds
Started Aug 24 08:44:50 PM UTC 24
Finished Aug 24 08:45:00 PM UTC 24
Peak memory 262192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921221776 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.921221776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2588199412
Short name T814
Test name
Test status
Simulation time 27312435 ps
CPU time 1.29 seconds
Started Aug 24 08:44:49 PM UTC 24
Finished Aug 24 08:44:51 PM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588199412 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_volatile_unlock_smoke.2588199412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.334672126
Short name T229
Test name
Test status
Simulation time 57439886 ps
CPU time 1.25 seconds
Started Aug 24 08:44:57 PM UTC 24
Finished Aug 24 08:44:59 PM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334672126 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.334672126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1238493816
Short name T844
Test name
Test status
Simulation time 719090334 ps
CPU time 10.35 seconds
Started Aug 24 08:44:55 PM UTC 24
Finished Aug 24 08:45:06 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238493816 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1238493816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.1928565253
Short name T843
Test name
Test status
Simulation time 296085889 ps
CPU time 10 seconds
Started Aug 24 08:44:55 PM UTC 24
Finished Aug 24 08:45:06 PM UTC 24
Peak memory 230112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928565253 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_acce
ss.1928565253
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.4059189850
Short name T834
Test name
Test status
Simulation time 131443394 ps
CPU time 3.26 seconds
Started Aug 24 08:44:55 PM UTC 24
Finished Aug 24 08:44:59 PM UTC 24
Peak memory 234228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059189850 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.4059189850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2049800152
Short name T127
Test name
Test status
Simulation time 477261400 ps
CPU time 16.78 seconds
Started Aug 24 08:44:55 PM UTC 24
Finished Aug 24 08:45:13 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049800152 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2049800152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2407002161
Short name T120
Test name
Test status
Simulation time 1251322532 ps
CPU time 11.63 seconds
Started Aug 24 08:44:56 PM UTC 24
Finished Aug 24 08:45:09 PM UTC 24
Peak memory 232140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407002161 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_
token_digest.2407002161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2840376434
Short name T126
Test name
Test status
Simulation time 3983462807 ps
CPU time 14.76 seconds
Started Aug 24 08:44:56 PM UTC 24
Finished Aug 24 08:45:12 PM UTC 24
Peak memory 232056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840376434 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_tok
en_mux.2840376434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.3717042552
Short name T119
Test name
Test status
Simulation time 278800687 ps
CPU time 12.23 seconds
Started Aug 24 08:44:55 PM UTC 24
Finished Aug 24 08:45:08 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717042552 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3717042552
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.822313613
Short name T830
Test name
Test status
Simulation time 211402966 ps
CPU time 3.29 seconds
Started Aug 24 08:44:52 PM UTC 24
Finished Aug 24 08:44:57 PM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822313613 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.822313613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.1271660132
Short name T857
Test name
Test status
Simulation time 700318846 ps
CPU time 36.79 seconds
Started Aug 24 08:44:53 PM UTC 24
Finished Aug 24 08:45:32 PM UTC 24
Peak memory 258868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271660132 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1271660132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2892614213
Short name T841
Test name
Test status
Simulation time 64652897 ps
CPU time 10.31 seconds
Started Aug 24 08:44:53 PM UTC 24
Finished Aug 24 08:45:05 PM UTC 24
Peak memory 262720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892614213 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2892614213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2519093301
Short name T872
Test name
Test status
Simulation time 26871796494 ps
CPU time 147.84 seconds
Started Aug 24 08:44:56 PM UTC 24
Finished Aug 24 08:47:26 PM UTC 24
Peak memory 289536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2519093301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 49.lc_ctrl_stress_all.2519093301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3933046294
Short name T216
Test name
Test status
Simulation time 7816901951 ps
CPU time 31.96 seconds
Started Aug 24 08:44:57 PM UTC 24
Finished Aug 24 08:45:31 PM UTC 24
Peak memory 252688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933046294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3933046294
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2788470375
Short name T828
Test name
Test status
Simulation time 42679602 ps
CPU time 1 seconds
Started Aug 24 08:44:53 PM UTC 24
Finished Aug 24 08:44:56 PM UTC 24
Peak memory 218432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788470375 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_volatile_unlock_smoke.2788470375
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3374025559
Short name T281
Test name
Test status
Simulation time 146509203 ps
CPU time 1.38 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:33 PM UTC 24
Peak memory 218776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374025559 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3374025559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1436975498
Short name T297
Test name
Test status
Simulation time 1056592397 ps
CPU time 15.36 seconds
Started Aug 24 08:41:26 PM UTC 24
Finished Aug 24 08:41:43 PM UTC 24
Peak memory 237912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436975498 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1436975498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2736287860
Short name T49
Test name
Test status
Simulation time 2207657437 ps
CPU time 13.94 seconds
Started Aug 24 08:41:28 PM UTC 24
Finished Aug 24 08:41:44 PM UTC 24
Peak memory 229884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736287860 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2736287860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3396389993
Short name T387
Test name
Test status
Simulation time 4986678305 ps
CPU time 52.32 seconds
Started Aug 24 08:41:28 PM UTC 24
Finished Aug 24 08:42:23 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396389993
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_errors.3396389993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.354757305
Short name T290
Test name
Test status
Simulation time 409013183 ps
CPU time 7.72 seconds
Started Aug 24 08:41:28 PM UTC 24
Finished Aug 24 08:41:38 PM UTC 24
Peak memory 230192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354757305 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_prio
rity.354757305
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.3325996602
Short name T284
Test name
Test status
Simulation time 136291731 ps
CPU time 5.14 seconds
Started Aug 24 08:41:28 PM UTC 24
Finished Aug 24 08:41:35 PM UTC 24
Peak memory 232112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325996602
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_jtag_prog_failure.3325996602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2732680290
Short name T370
Test name
Test status
Simulation time 5956735596 ps
CPU time 46.03 seconds
Started Aug 24 08:41:28 PM UTC 24
Finished Aug 24 08:42:17 PM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732680290
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l
c_ctrl_jtag_regwen_during_op.2732680290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2663858646
Short name T44
Test name
Test status
Simulation time 55230907 ps
CPU time 2.21 seconds
Started Aug 24 08:41:27 PM UTC 24
Finished Aug 24 08:41:31 PM UTC 24
Peak memory 229768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663858646
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_smoke.2663858646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2265721721
Short name T447
Test name
Test status
Simulation time 3577205030 ps
CPU time 78.94 seconds
Started Aug 24 08:41:27 PM UTC 24
Finished Aug 24 08:42:48 PM UTC 24
Peak memory 281172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265721721
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_c
trl_jtag_state_failure.2265721721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1580737091
Short name T139
Test name
Test status
Simulation time 370155387 ps
CPU time 21.11 seconds
Started Aug 24 08:41:28 PM UTC 24
Finished Aug 24 08:41:51 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580737091
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l
c_ctrl_jtag_state_post_trans.1580737091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.650365340
Short name T278
Test name
Test status
Simulation time 993087638 ps
CPU time 6.66 seconds
Started Aug 24 08:41:25 PM UTC 24
Finished Aug 24 08:41:32 PM UTC 24
Peak memory 232456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650365340 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.650365340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3259764634
Short name T83
Test name
Test status
Simulation time 352651096 ps
CPU time 28.44 seconds
Started Aug 24 08:41:27 PM UTC 24
Finished Aug 24 08:41:57 PM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259764634 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3259764634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.4214231650
Short name T271
Test name
Test status
Simulation time 472040449 ps
CPU time 13.54 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:45 PM UTC 24
Peak memory 237844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214231650 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4214231650
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.2805370251
Short name T302
Test name
Test status
Simulation time 390202118 ps
CPU time 13.77 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:45 PM UTC 24
Peak memory 238032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805370251 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_t
oken_digest.2805370251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.3131684159
Short name T307
Test name
Test status
Simulation time 367846391 ps
CPU time 15.89 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:48 PM UTC 24
Peak memory 232364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131684159 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_toke
n_mux.3131684159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.4178580820
Short name T79
Test name
Test status
Simulation time 287106809 ps
CPU time 14.29 seconds
Started Aug 24 08:41:27 PM UTC 24
Finished Aug 24 08:41:43 PM UTC 24
Peak memory 232044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178580820 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4178580820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.2780377482
Short name T102
Test name
Test status
Simulation time 411972703 ps
CPU time 7.39 seconds
Started Aug 24 08:41:24 PM UTC 24
Finished Aug 24 08:41:32 PM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780377482 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2780377482
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2990177129
Short name T266
Test name
Test status
Simulation time 81756940 ps
CPU time 4.32 seconds
Started Aug 24 08:41:25 PM UTC 24
Finished Aug 24 08:41:30 PM UTC 24
Peak memory 234580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990177129 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2990177129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.1525974681
Short name T116
Test name
Test status
Simulation time 3353065929 ps
CPU time 84.95 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:42:58 PM UTC 24
Peak memory 262644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1525974681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 5.lc_ctrl_stress_all.1525974681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2700752943
Short name T258
Test name
Test status
Simulation time 2156412918 ps
CPU time 107.2 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:43:20 PM UTC 24
Peak memory 281392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700752943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.2700752943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2458238108
Short name T273
Test name
Test status
Simulation time 19665243 ps
CPU time 1.47 seconds
Started Aug 24 08:41:24 PM UTC 24
Finished Aug 24 08:41:26 PM UTC 24
Peak memory 228852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458238108 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_volatile_unlock_smoke.2458238108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.573675815
Short name T289
Test name
Test status
Simulation time 21609029 ps
CPU time 1.47 seconds
Started Aug 24 08:41:34 PM UTC 24
Finished Aug 24 08:41:37 PM UTC 24
Peak memory 218708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573675815 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.573675815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3216206297
Short name T283
Test name
Test status
Simulation time 14980737 ps
CPU time 1.27 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:34 PM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216206297 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3216206297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3155560094
Short name T69
Test name
Test status
Simulation time 350293863 ps
CPU time 16.65 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:49 PM UTC 24
Peak memory 237980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155560094 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3155560094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2616273974
Short name T51
Test name
Test status
Simulation time 866862272 ps
CPU time 23.44 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:57 PM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616273974 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2616273974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3382163406
Short name T71
Test name
Test status
Simulation time 2599144234 ps
CPU time 49.79 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:42:24 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382163406
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_errors.3382163406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.4249005790
Short name T310
Test name
Test status
Simulation time 1959395277 ps
CPU time 14.92 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:48 PM UTC 24
Peak memory 229312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249005790 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_pri
ority.4249005790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.1059877529
Short name T136
Test name
Test status
Simulation time 919619329 ps
CPU time 16.29 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:50 PM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059877529
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_jtag_prog_failure.1059877529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4097743254
Short name T381
Test name
Test status
Simulation time 5905611355 ps
CPU time 48.22 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:42:22 PM UTC 24
Peak memory 229272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097743254
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l
c_ctrl_jtag_regwen_during_op.4097743254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1256461669
Short name T286
Test name
Test status
Simulation time 7480398577 ps
CPU time 22.5 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:56 PM UTC 24
Peak memory 228232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256461669
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_smoke.1256461669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1016095356
Short name T223
Test name
Test status
Simulation time 2659889177 ps
CPU time 70.92 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:42:45 PM UTC 24
Peak memory 283216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016095356
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_c
trl_jtag_state_failure.1016095356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3132044847
Short name T265
Test name
Test status
Simulation time 341791523 ps
CPU time 12.03 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:45 PM UTC 24
Peak memory 256664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132044847
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l
c_ctrl_jtag_state_post_trans.3132044847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1112301467
Short name T282
Test name
Test status
Simulation time 45733650 ps
CPU time 2.93 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:35 PM UTC 24
Peak memory 232188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112301467 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1112301467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1500078052
Short name T140
Test name
Test status
Simulation time 685386010 ps
CPU time 18.94 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:51 PM UTC 24
Peak memory 229944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500078052 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1500078052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3426066283
Short name T67
Test name
Test status
Simulation time 271050574 ps
CPU time 13.21 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:47 PM UTC 24
Peak memory 237872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426066283 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3426066283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.1962198437
Short name T305
Test name
Test status
Simulation time 710325397 ps
CPU time 12.94 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:47 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962198437 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_t
oken_digest.1962198437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.497844383
Short name T309
Test name
Test status
Simulation time 619354267 ps
CPU time 14.71 seconds
Started Aug 24 08:41:32 PM UTC 24
Finished Aug 24 08:41:48 PM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497844383 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token
_mux.497844383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.4243716341
Short name T259
Test name
Test status
Simulation time 868834257 ps
CPU time 21.12 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:53 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243716341 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.4243716341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1383039952
Short name T94
Test name
Test status
Simulation time 44573887 ps
CPU time 1.39 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:33 PM UTC 24
Peak memory 222688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383039952 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1383039952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.3554485934
Short name T333
Test name
Test status
Simulation time 997381599 ps
CPU time 29.97 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:42:02 PM UTC 24
Peak memory 260700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554485934 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3554485934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.122418309
Short name T260
Test name
Test status
Simulation time 52880191 ps
CPU time 9.95 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:42 PM UTC 24
Peak memory 262732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122418309 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.122418309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.3324900533
Short name T72
Test name
Test status
Simulation time 6517733404 ps
CPU time 219.02 seconds
Started Aug 24 08:41:33 PM UTC 24
Finished Aug 24 08:45:16 PM UTC 24
Peak memory 295692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3324900533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 6.lc_ctrl_stress_all.3324900533
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3446126993
Short name T145
Test name
Test status
Simulation time 5493764831 ps
CPU time 116.47 seconds
Started Aug 24 08:41:33 PM UTC 24
Finished Aug 24 08:43:32 PM UTC 24
Peak memory 281640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446126993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3446126993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1098438055
Short name T280
Test name
Test status
Simulation time 15797193 ps
CPU time 1.32 seconds
Started Aug 24 08:41:30 PM UTC 24
Finished Aug 24 08:41:33 PM UTC 24
Peak memory 222720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098438055 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_volatile_unlock_smoke.1098438055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.1997610352
Short name T296
Test name
Test status
Simulation time 33620460 ps
CPU time 1.31 seconds
Started Aug 24 08:41:40 PM UTC 24
Finished Aug 24 08:41:43 PM UTC 24
Peak memory 218992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997610352 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1997610352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1310382041
Short name T61
Test name
Test status
Simulation time 369770067 ps
CPU time 22 seconds
Started Aug 24 08:41:34 PM UTC 24
Finished Aug 24 08:41:58 PM UTC 24
Peak memory 230116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310382041 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1310382041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.874641838
Short name T50
Test name
Test status
Simulation time 614623711 ps
CPU time 6.84 seconds
Started Aug 24 08:41:38 PM UTC 24
Finished Aug 24 08:41:46 PM UTC 24
Peak memory 230112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874641838 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.874641838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3086709696
Short name T222
Test name
Test status
Simulation time 14866339441 ps
CPU time 68.27 seconds
Started Aug 24 08:41:37 PM UTC 24
Finished Aug 24 08:42:47 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086709696
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_errors.3086709696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.535191435
Short name T238
Test name
Test status
Simulation time 179525863 ps
CPU time 6.87 seconds
Started Aug 24 08:41:38 PM UTC 24
Finished Aug 24 08:41:46 PM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535191435 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_prio
rity.535191435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3112937118
Short name T306
Test name
Test status
Simulation time 551272915 ps
CPU time 9.4 seconds
Started Aug 24 08:41:37 PM UTC 24
Finished Aug 24 08:41:47 PM UTC 24
Peak memory 232116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112937118
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_jtag_prog_failure.3112937118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1888091755
Short name T335
Test name
Test status
Simulation time 2136360198 ps
CPU time 23.94 seconds
Started Aug 24 08:41:38 PM UTC 24
Finished Aug 24 08:42:03 PM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888091755
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l
c_ctrl_jtag_regwen_during_op.1888091755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.722465716
Short name T301
Test name
Test status
Simulation time 514990348 ps
CPU time 8.71 seconds
Started Aug 24 08:41:36 PM UTC 24
Finished Aug 24 08:41:45 PM UTC 24
Peak memory 229764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722465716
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
smoke.722465716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.4120296790
Short name T383
Test name
Test status
Simulation time 948821156 ps
CPU time 45.21 seconds
Started Aug 24 08:41:36 PM UTC 24
Finished Aug 24 08:42:22 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120296790
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_c
trl_jtag_state_failure.4120296790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.4271685743
Short name T270
Test name
Test status
Simulation time 312625640 ps
CPU time 19.9 seconds
Started Aug 24 08:41:36 PM UTC 24
Finished Aug 24 08:41:57 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271685743
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l
c_ctrl_jtag_state_post_trans.4271685743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.829395124
Short name T294
Test name
Test status
Simulation time 308300220 ps
CPU time 5.74 seconds
Started Aug 24 08:41:34 PM UTC 24
Finished Aug 24 08:41:41 PM UTC 24
Peak memory 232264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829395124 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.829395124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3665174647
Short name T330
Test name
Test status
Simulation time 303455670 ps
CPU time 23.75 seconds
Started Aug 24 08:41:35 PM UTC 24
Finished Aug 24 08:42:01 PM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665174647 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3665174647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.223669644
Short name T348
Test name
Test status
Simulation time 13823256191 ps
CPU time 27.77 seconds
Started Aug 24 08:41:38 PM UTC 24
Finished Aug 24 08:42:07 PM UTC 24
Peak memory 232316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223669644 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.223669644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2872403498
Short name T320
Test name
Test status
Simulation time 1266317025 ps
CPU time 17.57 seconds
Started Aug 24 08:41:39 PM UTC 24
Finished Aug 24 08:41:58 PM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872403498 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_t
oken_digest.2872403498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2440055119
Short name T312
Test name
Test status
Simulation time 482374326 ps
CPU time 9.52 seconds
Started Aug 24 08:41:39 PM UTC 24
Finished Aug 24 08:41:50 PM UTC 24
Peak memory 230124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440055119 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_toke
n_mux.2440055119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.2995184895
Short name T75
Test name
Test status
Simulation time 558853198 ps
CPU time 12.93 seconds
Started Aug 24 08:41:35 PM UTC 24
Finished Aug 24 08:41:50 PM UTC 24
Peak memory 238224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995184895 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2995184895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.892729432
Short name T82
Test name
Test status
Simulation time 418747571 ps
CPU time 7.25 seconds
Started Aug 24 08:41:34 PM UTC 24
Finished Aug 24 08:41:43 PM UTC 24
Peak memory 229948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892729432 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.892729432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.378590959
Short name T191
Test name
Test status
Simulation time 345126624 ps
CPU time 43.5 seconds
Started Aug 24 08:41:34 PM UTC 24
Finished Aug 24 08:42:19 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378590959 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.378590959
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2987505223
Short name T293
Test name
Test status
Simulation time 188653472 ps
CPU time 3.64 seconds
Started Aug 24 08:41:34 PM UTC 24
Finished Aug 24 08:41:39 PM UTC 24
Peak memory 234508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987505223 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2987505223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3350228128
Short name T324
Test name
Test status
Simulation time 1023478475 ps
CPU time 19.06 seconds
Started Aug 24 08:41:39 PM UTC 24
Finished Aug 24 08:41:59 PM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3350228128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 7.lc_ctrl_stress_all.3350228128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1686048989
Short name T288
Test name
Test status
Simulation time 13495419 ps
CPU time 1.23 seconds
Started Aug 24 08:41:34 PM UTC 24
Finished Aug 24 08:41:37 PM UTC 24
Peak memory 220676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686048989 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_volatile_unlock_smoke.1686048989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1388076000
Short name T134
Test name
Test status
Simulation time 12705476 ps
CPU time 1.32 seconds
Started Aug 24 08:41:47 PM UTC 24
Finished Aug 24 08:41:50 PM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388076000 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1388076000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2764758417
Short name T303
Test name
Test status
Simulation time 15864588 ps
CPU time 1.24 seconds
Started Aug 24 08:41:44 PM UTC 24
Finished Aug 24 08:41:46 PM UTC 24
Peak memory 216920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764758417 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2764758417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.1128825
Short name T355
Test name
Test status
Simulation time 2540037546 ps
CPU time 24.52 seconds
Started Aug 24 08:41:44 PM UTC 24
Finished Aug 24 08:42:09 PM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128825 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1128825
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1596473287
Short name T137
Test name
Test status
Simulation time 221851396 ps
CPU time 2.95 seconds
Started Aug 24 08:41:46 PM UTC 24
Finished Aug 24 08:41:50 PM UTC 24
Peak memory 230108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596473287 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1596473287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2269512705
Short name T394
Test name
Test status
Simulation time 3700009121 ps
CPU time 37.45 seconds
Started Aug 24 08:41:46 PM UTC 24
Finished Aug 24 08:42:25 PM UTC 24
Peak memory 232456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269512705
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_errors.2269512705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.588586263
Short name T138
Test name
Test status
Simulation time 430581254 ps
CPU time 3.03 seconds
Started Aug 24 08:41:46 PM UTC 24
Finished Aug 24 08:41:50 PM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588586263 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_prio
rity.588586263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3300561082
Short name T323
Test name
Test status
Simulation time 325582727 ps
CPU time 11.65 seconds
Started Aug 24 08:41:46 PM UTC 24
Finished Aug 24 08:41:59 PM UTC 24
Peak memory 232108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300561082
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_jtag_prog_failure.3300561082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1649386354
Short name T347
Test name
Test status
Simulation time 978958759 ps
CPU time 19.44 seconds
Started Aug 24 08:41:46 PM UTC 24
Finished Aug 24 08:42:07 PM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649386354
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l
c_ctrl_jtag_regwen_during_op.1649386354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1259139838
Short name T311
Test name
Test status
Simulation time 175788747 ps
CPU time 4.1 seconds
Started Aug 24 08:41:44 PM UTC 24
Finished Aug 24 08:41:49 PM UTC 24
Peak memory 229584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259139838
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_smoke.1259139838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.633168342
Short name T485
Test name
Test status
Simulation time 2680090525 ps
CPU time 75.88 seconds
Started Aug 24 08:41:45 PM UTC 24
Finished Aug 24 08:43:02 PM UTC 24
Peak memory 283500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633168342
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_jtag_state_failure.633168342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1318704265
Short name T268
Test name
Test status
Simulation time 371257260 ps
CPU time 16.07 seconds
Started Aug 24 08:41:45 PM UTC 24
Finished Aug 24 08:42:02 PM UTC 24
Peak memory 236748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318704265
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l
c_ctrl_jtag_state_post_trans.1318704265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1840555728
Short name T304
Test name
Test status
Simulation time 30412000 ps
CPU time 3.12 seconds
Started Aug 24 08:41:42 PM UTC 24
Finished Aug 24 08:41:46 PM UTC 24
Peak memory 230208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840555728 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1840555728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2978931795
Short name T328
Test name
Test status
Simulation time 2093073967 ps
CPU time 15.15 seconds
Started Aug 24 08:41:44 PM UTC 24
Finished Aug 24 08:42:00 PM UTC 24
Peak memory 230000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978931795 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2978931795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.4033275677
Short name T351
Test name
Test status
Simulation time 1509748810 ps
CPU time 20.21 seconds
Started Aug 24 08:41:46 PM UTC 24
Finished Aug 24 08:42:08 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033275677 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4033275677
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.2999500821
Short name T349
Test name
Test status
Simulation time 576410460 ps
CPU time 18.38 seconds
Started Aug 24 08:41:47 PM UTC 24
Finished Aug 24 08:42:07 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999500821 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_t
oken_digest.2999500821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1692687969
Short name T340
Test name
Test status
Simulation time 845628870 ps
CPU time 17.12 seconds
Started Aug 24 08:41:46 PM UTC 24
Finished Aug 24 08:42:04 PM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692687969 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_toke
n_mux.1692687969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.193604681
Short name T76
Test name
Test status
Simulation time 1350390637 ps
CPU time 17.8 seconds
Started Aug 24 08:41:44 PM UTC 24
Finished Aug 24 08:42:03 PM UTC 24
Peak memory 232420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193604681 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.193604681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4221860736
Short name T298
Test name
Test status
Simulation time 25507141 ps
CPU time 1.98 seconds
Started Aug 24 08:41:40 PM UTC 24
Finished Aug 24 08:41:43 PM UTC 24
Peak memory 229036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221860736 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4221860736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.954743506
Short name T393
Test name
Test status
Simulation time 333306110 ps
CPU time 41.03 seconds
Started Aug 24 08:41:42 PM UTC 24
Finished Aug 24 08:42:25 PM UTC 24
Peak memory 263020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954743506 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.954743506
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.639433000
Short name T313
Test name
Test status
Simulation time 222122265 ps
CPU time 9.11 seconds
Started Aug 24 08:41:42 PM UTC 24
Finished Aug 24 08:41:52 PM UTC 24
Peak memory 256600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639433000 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.639433000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1018846392
Short name T129
Test name
Test status
Simulation time 46477723293 ps
CPU time 360.03 seconds
Started Aug 24 08:41:47 PM UTC 24
Finished Aug 24 08:47:53 PM UTC 24
Peak memory 234544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1018846392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 8.lc_ctrl_stress_all.1018846392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.397964055
Short name T299
Test name
Test status
Simulation time 16522394 ps
CPU time 1.32 seconds
Started Aug 24 08:41:42 PM UTC 24
Finished Aug 24 08:41:45 PM UTC 24
Peak memory 222912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397964055 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8
.lc_ctrl_volatile_unlock_smoke.397964055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2962040443
Short name T89
Test name
Test status
Simulation time 24891735 ps
CPU time 1.56 seconds
Started Aug 24 08:41:51 PM UTC 24
Finished Aug 24 08:41:54 PM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962040443 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2962040443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.2928832565
Short name T141
Test name
Test status
Simulation time 19776891 ps
CPU time 1.36 seconds
Started Aug 24 08:41:49 PM UTC 24
Finished Aug 24 08:41:51 PM UTC 24
Peak memory 219176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928832565 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2928832565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2833995500
Short name T352
Test name
Test status
Simulation time 2220574441 ps
CPU time 18.7 seconds
Started Aug 24 08:41:49 PM UTC 24
Finished Aug 24 08:42:09 PM UTC 24
Peak memory 232196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833995500 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2833995500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.270080340
Short name T52
Test name
Test status
Simulation time 391008021 ps
CPU time 7.12 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:41:59 PM UTC 24
Peak memory 230088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270080340 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.270080340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.4243543366
Short name T512
Test name
Test status
Simulation time 14747172176 ps
CPU time 78.79 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:43:11 PM UTC 24
Peak memory 232316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243543366
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_errors.4243543366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3616386981
Short name T332
Test name
Test status
Simulation time 1406112632 ps
CPU time 9.92 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:42:01 PM UTC 24
Peak memory 229996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616386981 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_pri
ority.3616386981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.3001709699
Short name T319
Test name
Test status
Simulation time 968231631 ps
CPU time 6.26 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:41:58 PM UTC 24
Peak memory 234236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001709699
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_jtag_prog_failure.3001709699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.774486346
Short name T372
Test name
Test status
Simulation time 2797632644 ps
CPU time 25.72 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:42:18 PM UTC 24
Peak memory 229924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774486346
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc
_ctrl_jtag_regwen_during_op.774486346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2990009609
Short name T331
Test name
Test status
Simulation time 577915034 ps
CPU time 10.91 seconds
Started Aug 24 08:41:49 PM UTC 24
Finished Aug 24 08:42:01 PM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990009609
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_smoke.2990009609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.2517488596
Short name T440
Test name
Test status
Simulation time 1086063553 ps
CPU time 50.19 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:42:42 PM UTC 24
Peak memory 262688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517488596
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_c
trl_jtag_state_failure.2517488596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2775537444
Short name T386
Test name
Test status
Simulation time 3546699446 ps
CPU time 31.12 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:42:23 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775537444
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.l
c_ctrl_jtag_state_post_trans.2775537444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.2459139721
Short name T317
Test name
Test status
Simulation time 78292010 ps
CPU time 4.26 seconds
Started Aug 24 08:41:49 PM UTC 24
Finished Aug 24 08:41:54 PM UTC 24
Peak memory 232264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459139721 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2459139721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1514813783
Short name T322
Test name
Test status
Simulation time 745759841 ps
CPU time 8.2 seconds
Started Aug 24 08:41:49 PM UTC 24
Finished Aug 24 08:41:58 PM UTC 24
Peak memory 236388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514813783 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1514813783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3254686643
Short name T342
Test name
Test status
Simulation time 1208786364 ps
CPU time 13.33 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:42:05 PM UTC 24
Peak memory 229972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254686643 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3254686643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1637274381
Short name T354
Test name
Test status
Simulation time 344201554 ps
CPU time 17.38 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:42:09 PM UTC 24
Peak memory 230812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637274381 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_t
oken_digest.1637274381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1255109640
Short name T353
Test name
Test status
Simulation time 2286497886 ps
CPU time 17.19 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:42:09 PM UTC 24
Peak memory 230764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255109640 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_toke
n_mux.1255109640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.3896906931
Short name T345
Test name
Test status
Simulation time 629144592 ps
CPU time 15.7 seconds
Started Aug 24 08:41:49 PM UTC 24
Finished Aug 24 08:42:06 PM UTC 24
Peak memory 232504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896906931 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3896906931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.2710926364
Short name T314
Test name
Test status
Simulation time 55462004 ps
CPU time 4.51 seconds
Started Aug 24 08:41:47 PM UTC 24
Finished Aug 24 08:41:53 PM UTC 24
Peak memory 230124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710926364 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2710926364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.374730716
Short name T420
Test name
Test status
Simulation time 270100309 ps
CPU time 47.66 seconds
Started Aug 24 08:41:47 PM UTC 24
Finished Aug 24 08:42:37 PM UTC 24
Peak memory 260968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374730716 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.374730716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2406047121
Short name T114
Test name
Test status
Simulation time 249755019 ps
CPU time 10.53 seconds
Started Aug 24 08:41:49 PM UTC 24
Finished Aug 24 08:42:00 PM UTC 24
Peak memory 263020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406047121 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2406047121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3959284384
Short name T868
Test name
Test status
Simulation time 21155298669 ps
CPU time 306.88 seconds
Started Aug 24 08:41:50 PM UTC 24
Finished Aug 24 08:47:02 PM UTC 24
Peak memory 295676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3959284384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 9.lc_ctrl_stress_all.3959284384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4087851457
Short name T135
Test name
Test status
Simulation time 64875062 ps
CPU time 1.23 seconds
Started Aug 24 08:41:47 PM UTC 24
Finished Aug 24 08:41:50 PM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087851457 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_volatile_unlock_smoke.4087851457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest
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