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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 97.92 95.93 93.40 100.00 98.52 99.00 96.11


Total test records in report: 1004
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T368 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3310780365 Aug 25 07:43:16 AM UTC 24 Aug 25 07:43:32 AM UTC 24 1261826766 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1887181465 Aug 25 07:43:27 AM UTC 24 Aug 25 07:43:35 AM UTC 24 756112441 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.2848680520 Aug 25 07:43:22 AM UTC 24 Aug 25 07:43:37 AM UTC 24 3069972717 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1185753069 Aug 25 07:43:07 AM UTC 24 Aug 25 07:43:37 AM UTC 24 1240449206 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3348786074 Aug 25 07:43:13 AM UTC 24 Aug 25 07:43:37 AM UTC 24 2463406104 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.404544227 Aug 25 07:43:22 AM UTC 24 Aug 25 07:43:39 AM UTC 24 212993399 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.4286684970 Aug 25 07:43:28 AM UTC 24 Aug 25 07:43:41 AM UTC 24 216175608 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.1549180770 Aug 25 07:43:09 AM UTC 24 Aug 25 07:43:42 AM UTC 24 670322989 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.1307286593 Aug 25 07:42:39 AM UTC 24 Aug 25 07:43:43 AM UTC 24 872691270 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.971821930 Aug 25 07:43:27 AM UTC 24 Aug 25 07:43:46 AM UTC 24 338684345 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.929491768 Aug 25 07:43:44 AM UTC 24 Aug 25 07:43:46 AM UTC 24 24756646 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.598159378 Aug 25 07:43:44 AM UTC 24 Aug 25 07:43:46 AM UTC 24 13529263 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.3875947523 Aug 25 07:43:44 AM UTC 24 Aug 25 07:43:48 AM UTC 24 204497169 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.2625383736 Aug 25 07:43:44 AM UTC 24 Aug 25 07:43:48 AM UTC 24 140533716 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2402443571 Aug 25 07:43:44 AM UTC 24 Aug 25 07:43:49 AM UTC 24 128816602 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.676475283 Aug 25 07:43:44 AM UTC 24 Aug 25 07:43:50 AM UTC 24 561628561 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.2487258168 Aug 25 07:43:44 AM UTC 24 Aug 25 07:43:50 AM UTC 24 239682257 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.2904355204 Aug 25 07:43:24 AM UTC 24 Aug 25 07:43:51 AM UTC 24 12333203805 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2847106116 Aug 25 07:43:50 AM UTC 24 Aug 25 07:43:52 AM UTC 24 54093499 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1088187895 Aug 25 07:43:01 AM UTC 24 Aug 25 07:43:53 AM UTC 24 518327598 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3399690703 Aug 25 07:43:51 AM UTC 24 Aug 25 07:43:54 AM UTC 24 12173102 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.1293040440 Aug 25 07:43:51 AM UTC 24 Aug 25 07:43:54 AM UTC 24 32443865 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.3833636210 Aug 25 07:42:39 AM UTC 24 Aug 25 07:43:54 AM UTC 24 5083903181 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.902276457 Aug 25 07:43:46 AM UTC 24 Aug 25 07:43:55 AM UTC 24 1857055526 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.4169767926 Aug 25 07:43:42 AM UTC 24 Aug 25 07:43:57 AM UTC 24 213368367 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.4265933914 Aug 25 07:43:54 AM UTC 24 Aug 25 07:43:58 AM UTC 24 193835328 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.441561847 Aug 25 07:42:41 AM UTC 24 Aug 25 07:44:02 AM UTC 24 6085709090 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.2578190010 Aug 25 07:43:44 AM UTC 24 Aug 25 07:44:04 AM UTC 24 314047063 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.4077434659 Aug 25 07:42:52 AM UTC 24 Aug 25 07:44:04 AM UTC 24 21449499640 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2072566370 Aug 25 07:43:44 AM UTC 24 Aug 25 07:44:05 AM UTC 24 492489010 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.2097360876 Aug 25 07:43:56 AM UTC 24 Aug 25 07:44:06 AM UTC 24 506121765 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.3419238562 Aug 25 07:43:53 AM UTC 24 Aug 25 07:44:07 AM UTC 24 308384136 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3370424184 Aug 25 07:43:47 AM UTC 24 Aug 25 07:44:07 AM UTC 24 586433441 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1735342263 Aug 25 07:43:44 AM UTC 24 Aug 25 07:44:09 AM UTC 24 1321232583 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3529019311 Aug 25 07:43:47 AM UTC 24 Aug 25 07:44:09 AM UTC 24 511462700 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.3080017335 Aug 25 07:43:47 AM UTC 24 Aug 25 07:44:09 AM UTC 24 290756227 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.4051461815 Aug 25 07:44:08 AM UTC 24 Aug 25 07:44:10 AM UTC 24 16066215 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1939699347 Aug 25 07:44:10 AM UTC 24 Aug 25 07:44:13 AM UTC 24 14746509 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1336415646 Aug 25 07:41:21 AM UTC 24 Aug 25 07:44:14 AM UTC 24 7846111651 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.3053564689 Aug 25 07:43:55 AM UTC 24 Aug 25 07:44:14 AM UTC 24 739101817 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3777358590 Aug 25 07:43:56 AM UTC 24 Aug 25 07:44:15 AM UTC 24 611261846 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.4201610246 Aug 25 07:44:10 AM UTC 24 Aug 25 07:44:16 AM UTC 24 36632547 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.435471914 Aug 25 07:43:11 AM UTC 24 Aug 25 07:44:17 AM UTC 24 1431080952 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.3367103782 Aug 25 07:44:13 AM UTC 24 Aug 25 07:44:19 AM UTC 24 215963629 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.3815839120 Aug 25 07:43:27 AM UTC 24 Aug 25 07:44:20 AM UTC 24 26842351880 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.4022716168 Aug 25 07:39:59 AM UTC 24 Aug 25 07:44:36 AM UTC 24 5187774767 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.1501827141 Aug 25 07:44:06 AM UTC 24 Aug 25 07:44:22 AM UTC 24 1532184612 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.791151581 Aug 25 07:43:07 AM UTC 24 Aug 25 07:44:22 AM UTC 24 1074020269 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3715577623 Aug 25 07:44:16 AM UTC 24 Aug 25 07:44:22 AM UTC 24 851634889 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.101738737 Aug 25 07:44:11 AM UTC 24 Aug 25 07:44:23 AM UTC 24 80921460 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.621678271 Aug 25 07:43:21 AM UTC 24 Aug 25 07:44:24 AM UTC 24 955789361 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.2389356294 Aug 25 07:43:44 AM UTC 24 Aug 25 07:44:24 AM UTC 24 192388954 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.4213916707 Aug 25 07:44:15 AM UTC 24 Aug 25 07:44:26 AM UTC 24 349053365 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.2265374058 Aug 25 07:44:06 AM UTC 24 Aug 25 07:44:26 AM UTC 24 1586283256 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.489459369 Aug 25 07:44:23 AM UTC 24 Aug 25 07:44:28 AM UTC 24 681615555 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2631593679 Aug 25 07:44:25 AM UTC 24 Aug 25 07:44:28 AM UTC 24 44014405 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1131049655 Aug 25 07:44:06 AM UTC 24 Aug 25 07:44:28 AM UTC 24 441619300 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.2196605483 Aug 25 07:44:06 AM UTC 24 Aug 25 07:44:28 AM UTC 24 632806486 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1440337270 Aug 25 07:44:19 AM UTC 24 Aug 25 07:44:29 AM UTC 24 2448507946 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2265920805 Aug 25 07:44:28 AM UTC 24 Aug 25 07:44:30 AM UTC 24 22041742 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3039961217 Aug 25 07:42:19 AM UTC 24 Aug 25 07:44:32 AM UTC 24 4253733425 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.222369607 Aug 25 07:44:26 AM UTC 24 Aug 25 07:44:34 AM UTC 24 666555871 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.3742349696 Aug 25 07:44:29 AM UTC 24 Aug 25 07:44:34 AM UTC 24 48840813 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.2804605164 Aug 25 07:42:50 AM UTC 24 Aug 25 07:44:34 AM UTC 24 1311540476 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.3659127203 Aug 25 07:44:18 AM UTC 24 Aug 25 07:44:35 AM UTC 24 1481803915 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.714591181 Aug 25 07:44:06 AM UTC 24 Aug 25 07:44:36 AM UTC 24 1579066900 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.2818476584 Aug 25 07:44:29 AM UTC 24 Aug 25 07:44:38 AM UTC 24 68046357 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3654110568 Aug 25 07:44:04 AM UTC 24 Aug 25 07:44:40 AM UTC 24 483364452 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.874073877 Aug 25 07:44:23 AM UTC 24 Aug 25 07:44:40 AM UTC 24 326600314 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3769070362 Aug 25 07:44:31 AM UTC 24 Aug 25 07:44:40 AM UTC 24 816998891 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.335295852 Aug 25 07:44:34 AM UTC 24 Aug 25 07:44:41 AM UTC 24 693455857 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.1012996124 Aug 25 07:43:52 AM UTC 24 Aug 25 07:44:42 AM UTC 24 1682520815 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.2679173101 Aug 25 07:44:41 AM UTC 24 Aug 25 07:44:43 AM UTC 24 83763662 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.2973792471 Aug 25 07:44:23 AM UTC 24 Aug 25 07:44:44 AM UTC 24 3381125090 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2469734186 Aug 25 07:42:43 AM UTC 24 Aug 25 07:44:44 AM UTC 24 6096706794 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4010243570 Aug 25 07:44:42 AM UTC 24 Aug 25 07:44:44 AM UTC 24 12658611 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.2196697424 Aug 25 07:44:30 AM UTC 24 Aug 25 07:44:44 AM UTC 24 319437982 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1064963350 Aug 25 07:43:16 AM UTC 24 Aug 25 07:44:45 AM UTC 24 5327022843 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.1580130224 Aug 25 07:44:41 AM UTC 24 Aug 25 07:44:45 AM UTC 24 64202513 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3047471945 Aug 25 07:45:33 AM UTC 24 Aug 25 07:45:49 AM UTC 24 2206314815 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.1734928450 Aug 25 07:44:44 AM UTC 24 Aug 25 07:44:48 AM UTC 24 79276217 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.1919287891 Aug 25 07:42:03 AM UTC 24 Aug 25 07:44:48 AM UTC 24 2362235090 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.405868236 Aug 25 07:44:06 AM UTC 24 Aug 25 07:44:48 AM UTC 24 1475507821 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3749717777 Aug 25 07:44:37 AM UTC 24 Aug 25 07:44:49 AM UTC 24 1096670980 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.1235141065 Aug 25 07:44:35 AM UTC 24 Aug 25 07:44:50 AM UTC 24 519433992 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3176569669 Aug 25 07:44:24 AM UTC 24 Aug 25 07:44:51 AM UTC 24 2390114421 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2339251989 Aug 25 07:44:44 AM UTC 24 Aug 25 07:44:51 AM UTC 24 75587197 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1360032884 Aug 25 07:44:30 AM UTC 24 Aug 25 07:44:51 AM UTC 24 799219710 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.1016711028 Aug 25 07:43:44 AM UTC 24 Aug 25 07:44:52 AM UTC 24 32483874024 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.1603021080 Aug 25 07:44:37 AM UTC 24 Aug 25 07:44:53 AM UTC 24 227536957 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.3886745994 Aug 25 07:44:46 AM UTC 24 Aug 25 07:44:54 AM UTC 24 318047114 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.3972089172 Aug 25 07:44:37 AM UTC 24 Aug 25 07:44:55 AM UTC 24 656821940 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.2401191626 Aug 25 07:41:48 AM UTC 24 Aug 25 07:44:55 AM UTC 24 8274721241 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.4066540202 Aug 25 07:44:49 AM UTC 24 Aug 25 07:44:59 AM UTC 24 816344758 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.1352845771 Aug 25 07:44:46 AM UTC 24 Aug 25 07:45:01 AM UTC 24 1891651876 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.1165063797 Aug 25 07:44:34 AM UTC 24 Aug 25 07:45:01 AM UTC 24 11028311239 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.591431275 Aug 25 07:44:46 AM UTC 24 Aug 25 07:45:02 AM UTC 24 465680471 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.4228189396 Aug 25 07:44:57 AM UTC 24 Aug 25 07:45:03 AM UTC 24 375666570 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.2857821858 Aug 25 07:43:24 AM UTC 24 Aug 25 07:45:03 AM UTC 24 1352761347 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3797748079 Aug 25 07:44:29 AM UTC 24 Aug 25 07:45:04 AM UTC 24 148081888 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.576431010 Aug 25 07:44:46 AM UTC 24 Aug 25 07:45:05 AM UTC 24 738867764 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.4017615082 Aug 25 07:44:35 AM UTC 24 Aug 25 07:45:48 AM UTC 24 1815972086 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.3956224932 Aug 25 07:42:36 AM UTC 24 Aug 25 07:45:05 AM UTC 24 9236971043 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.1891726033 Aug 25 07:44:57 AM UTC 24 Aug 25 07:45:08 AM UTC 24 364472801 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.3486698218 Aug 25 07:43:16 AM UTC 24 Aug 25 07:45:12 AM UTC 24 3145666776 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.1700280138 Aug 25 07:45:11 AM UTC 24 Aug 25 07:45:14 AM UTC 24 20924353 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3705417097 Aug 25 07:45:11 AM UTC 24 Aug 25 07:45:14 AM UTC 24 21461552 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.1030689803 Aug 25 07:43:44 AM UTC 24 Aug 25 07:45:14 AM UTC 24 23690759771 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.236948580 Aug 25 07:45:11 AM UTC 24 Aug 25 07:45:15 AM UTC 24 342758791 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1430243832 Aug 25 07:45:11 AM UTC 24 Aug 25 07:45:16 AM UTC 24 182174398 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1110421614 Aug 25 07:45:15 AM UTC 24 Aug 25 07:45:18 AM UTC 24 46555253 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.1413524067 Aug 25 07:45:15 AM UTC 24 Aug 25 07:45:18 AM UTC 24 65574631 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.2149127593 Aug 25 07:44:57 AM UTC 24 Aug 25 07:45:18 AM UTC 24 702314974 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.2733715408 Aug 25 07:45:27 AM UTC 24 Aug 25 07:45:49 AM UTC 24 353346058 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2052464519 Aug 25 07:44:10 AM UTC 24 Aug 25 07:45:18 AM UTC 24 656989892 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3601465461 Aug 25 07:45:18 AM UTC 24 Aug 25 07:45:24 AM UTC 24 78784370 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.1951449643 Aug 25 07:45:15 AM UTC 24 Aug 25 07:45:24 AM UTC 24 499462936 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.2166861133 Aug 25 07:45:14 AM UTC 24 Aug 25 07:45:24 AM UTC 24 1080996495 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.771541552 Aug 25 07:45:13 AM UTC 24 Aug 25 07:45:24 AM UTC 24 1391643134 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.3763064771 Aug 25 07:45:11 AM UTC 24 Aug 25 07:45:25 AM UTC 24 78662362 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.1019124769 Aug 25 07:45:11 AM UTC 24 Aug 25 07:45:26 AM UTC 24 945643452 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.2679307561 Aug 25 07:45:20 AM UTC 24 Aug 25 07:45:27 AM UTC 24 462584848 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.1763456927 Aug 25 07:44:43 AM UTC 24 Aug 25 07:45:27 AM UTC 24 1471229806 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.4143020780 Aug 25 07:45:16 AM UTC 24 Aug 25 07:45:28 AM UTC 24 66583811 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.3005251084 Aug 25 07:45:13 AM UTC 24 Aug 25 07:45:28 AM UTC 24 917283697 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.854431507 Aug 25 07:45:13 AM UTC 24 Aug 25 07:45:28 AM UTC 24 1098327184 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3910567801 Aug 25 07:45:13 AM UTC 24 Aug 25 07:45:29 AM UTC 24 1099944511 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.3203304394 Aug 25 07:45:25 AM UTC 24 Aug 25 07:45:30 AM UTC 24 213437600 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.673203361 Aug 25 07:45:14 AM UTC 24 Aug 25 07:45:31 AM UTC 24 894578552 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3430571280 Aug 25 07:45:29 AM UTC 24 Aug 25 07:45:32 AM UTC 24 31175534 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.2717031165 Aug 25 07:45:18 AM UTC 24 Aug 25 07:45:32 AM UTC 24 694892708 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1257601153 Aug 25 07:45:30 AM UTC 24 Aug 25 07:45:33 AM UTC 24 26267216 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.694875888 Aug 25 07:45:13 AM UTC 24 Aug 25 07:45:33 AM UTC 24 4767903913 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.727114407 Aug 25 07:45:11 AM UTC 24 Aug 25 07:45:33 AM UTC 24 443735231 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3079699525 Aug 25 07:45:29 AM UTC 24 Aug 25 07:45:34 AM UTC 24 194907279 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.1034180784 Aug 25 07:45:20 AM UTC 24 Aug 25 07:45:35 AM UTC 24 449772010 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.480678536 Aug 25 07:45:25 AM UTC 24 Aug 25 07:45:37 AM UTC 24 523452978 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.2433628631 Aug 25 07:45:32 AM UTC 24 Aug 25 07:45:37 AM UTC 24 37163694 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.2606448293 Aug 25 07:45:34 AM UTC 24 Aug 25 07:45:37 AM UTC 24 34214309 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.52803341 Aug 25 07:45:38 AM UTC 24 Aug 25 07:45:41 AM UTC 24 92153103 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.3640794467 Aug 25 07:44:21 AM UTC 24 Aug 25 07:45:42 AM UTC 24 6679827923 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.2380012183 Aug 25 07:45:27 AM UTC 24 Aug 25 07:45:43 AM UTC 24 335132184 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1784994940 Aug 25 07:45:43 AM UTC 24 Aug 25 07:45:45 AM UTC 24 40424052 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.4231800631 Aug 25 07:44:08 AM UTC 24 Aug 25 07:45:46 AM UTC 24 2449301986 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.2282801885 Aug 25 07:45:25 AM UTC 24 Aug 25 07:45:47 AM UTC 24 2398094491 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3462319569 Aug 25 07:45:35 AM UTC 24 Aug 25 07:45:48 AM UTC 24 755651217 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3147004074 Aug 25 07:45:32 AM UTC 24 Aug 25 07:45:49 AM UTC 24 118237646 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.1226484152 Aug 25 07:45:13 AM UTC 24 Aug 25 07:45:50 AM UTC 24 9835206139 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.721557606 Aug 25 07:45:43 AM UTC 24 Aug 25 07:45:50 AM UTC 24 66363308 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.48178752 Aug 25 07:44:17 AM UTC 24 Aug 25 07:45:51 AM UTC 24 2730659129 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.4162565761 Aug 25 07:45:46 AM UTC 24 Aug 25 07:45:51 AM UTC 24 151991630 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.3446811609 Aug 25 07:45:26 AM UTC 24 Aug 25 07:45:52 AM UTC 24 397491714 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2958257613 Aug 25 07:45:47 AM UTC 24 Aug 25 07:45:53 AM UTC 24 50174927 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3251255526 Aug 25 07:45:52 AM UTC 24 Aug 25 07:45:55 AM UTC 24 20237855 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.576740220 Aug 25 07:45:52 AM UTC 24 Aug 25 07:45:55 AM UTC 24 16351295 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.3847444057 Aug 25 07:45:54 AM UTC 24 Aug 25 07:46:44 AM UTC 24 308688054 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.2123455489 Aug 25 07:44:49 AM UTC 24 Aug 25 07:45:55 AM UTC 24 2112038708 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1125442768 Aug 25 07:45:34 AM UTC 24 Aug 25 07:45:58 AM UTC 24 973707832 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.1133295020 Aug 25 07:45:52 AM UTC 24 Aug 25 07:45:58 AM UTC 24 53536005 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1163450771 Aug 25 07:44:33 AM UTC 24 Aug 25 07:45:59 AM UTC 24 1292571712 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.743800102 Aug 25 07:45:13 AM UTC 24 Aug 25 07:45:59 AM UTC 24 2067886301 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1951831532 Aug 25 07:45:50 AM UTC 24 Aug 25 07:45:59 AM UTC 24 203826494 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1203857210 Aug 25 07:45:34 AM UTC 24 Aug 25 07:46:00 AM UTC 24 813921445 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2173862398 Aug 25 07:45:56 AM UTC 24 Aug 25 07:46:00 AM UTC 24 52246979 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1072544409 Aug 25 07:45:36 AM UTC 24 Aug 25 07:46:01 AM UTC 24 839554217 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1870892614 Aug 25 07:45:48 AM UTC 24 Aug 25 07:46:02 AM UTC 24 195332380 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.4054236635 Aug 25 07:45:50 AM UTC 24 Aug 25 07:46:03 AM UTC 24 189974564 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.2010226467 Aug 25 07:46:02 AM UTC 24 Aug 25 07:46:05 AM UTC 24 104117466 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.2116529891 Aug 25 07:45:11 AM UTC 24 Aug 25 07:46:05 AM UTC 24 710636977 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1640755602 Aug 25 07:46:04 AM UTC 24 Aug 25 07:46:07 AM UTC 24 38262777 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3429515316 Aug 25 07:45:50 AM UTC 24 Aug 25 07:46:07 AM UTC 24 3530927660 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.994231882 Aug 25 07:45:56 AM UTC 24 Aug 25 07:46:09 AM UTC 24 69453249 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.2574364096 Aug 25 07:46:03 AM UTC 24 Aug 25 07:46:09 AM UTC 24 653779657 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.1631822714 Aug 25 07:45:11 AM UTC 24 Aug 25 07:46:09 AM UTC 24 844135041 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.2167436553 Aug 25 07:45:20 AM UTC 24 Aug 25 07:46:10 AM UTC 24 1619427045 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.3533616713 Aug 25 07:45:51 AM UTC 24 Aug 25 07:46:10 AM UTC 24 1127490731 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.148168326 Aug 25 07:45:59 AM UTC 24 Aug 25 07:46:10 AM UTC 24 733711392 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3064819700 Aug 25 07:45:50 AM UTC 24 Aug 25 07:46:12 AM UTC 24 2869006090 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.608835759 Aug 25 07:45:25 AM UTC 24 Aug 25 07:46:14 AM UTC 24 1544013276 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2893489794 Aug 25 07:45:59 AM UTC 24 Aug 25 07:46:14 AM UTC 24 1112020840 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.3272728795 Aug 25 07:45:59 AM UTC 24 Aug 25 07:46:14 AM UTC 24 562003635 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1446367609 Aug 25 07:46:41 AM UTC 24 Aug 25 07:46:44 AM UTC 24 25788889 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.321445517 Aug 25 07:46:07 AM UTC 24 Aug 25 07:46:14 AM UTC 24 146853521 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.2488357255 Aug 25 07:45:16 AM UTC 24 Aug 25 07:46:15 AM UTC 24 884217278 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.857434626 Aug 25 07:45:58 AM UTC 24 Aug 25 07:46:17 AM UTC 24 441782329 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.646530578 Aug 25 07:46:10 AM UTC 24 Aug 25 07:46:17 AM UTC 24 860152701 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.3180219586 Aug 25 07:46:06 AM UTC 24 Aug 25 07:46:18 AM UTC 24 135177357 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1223553011 Aug 25 07:43:49 AM UTC 24 Aug 25 07:46:19 AM UTC 24 9336502837 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1118653982 Aug 25 07:46:01 AM UTC 24 Aug 25 07:46:21 AM UTC 24 1452496264 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.1594004729 Aug 25 07:43:56 AM UTC 24 Aug 25 07:46:21 AM UTC 24 4111330728 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3807327676 Aug 25 07:46:10 AM UTC 24 Aug 25 07:46:22 AM UTC 24 676972304 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.460378800 Aug 25 07:46:20 AM UTC 24 Aug 25 07:46:23 AM UTC 24 15648727 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1988577641 Aug 25 07:46:20 AM UTC 24 Aug 25 07:46:23 AM UTC 24 16689005 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.799324852 Aug 25 07:46:21 AM UTC 24 Aug 25 07:46:25 AM UTC 24 129773450 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3476644032 Aug 25 07:46:20 AM UTC 24 Aug 25 07:46:26 AM UTC 24 139515318 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.3684212874 Aug 25 07:46:23 AM UTC 24 Aug 25 07:46:26 AM UTC 24 17356036 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2603237487 Aug 25 07:46:21 AM UTC 24 Aug 25 07:46:26 AM UTC 24 257470023 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.1483879575 Aug 25 07:46:10 AM UTC 24 Aug 25 07:46:28 AM UTC 24 350494153 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3678975201 Aug 25 07:46:09 AM UTC 24 Aug 25 07:46:28 AM UTC 24 378391083 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.774628241 Aug 25 07:46:25 AM UTC 24 Aug 25 07:46:28 AM UTC 24 31011870 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1732986404 Aug 25 07:41:37 AM UTC 24 Aug 25 07:46:28 AM UTC 24 12452206243 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2629496600 Aug 25 07:40:17 AM UTC 24 Aug 25 07:46:28 AM UTC 24 104737477243 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2202323744 Aug 25 07:46:23 AM UTC 24 Aug 25 07:46:28 AM UTC 24 174879432 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2939317028 Aug 25 07:45:44 AM UTC 24 Aug 25 07:46:30 AM UTC 24 957449473 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.1822612317 Aug 25 07:45:57 AM UTC 24 Aug 25 07:46:30 AM UTC 24 1660091216 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.3601470407 Aug 25 07:46:21 AM UTC 24 Aug 25 07:46:31 AM UTC 24 240097589 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.3639669047 Aug 25 07:46:21 AM UTC 24 Aug 25 07:46:32 AM UTC 24 164270684 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.773635754 Aug 25 07:45:13 AM UTC 24 Aug 25 07:46:32 AM UTC 24 5826017953 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.253720477 Aug 25 07:46:28 AM UTC 24 Aug 25 07:46:32 AM UTC 24 63302433 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3110183137 Aug 25 07:46:21 AM UTC 24 Aug 25 07:46:32 AM UTC 24 1797589724 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.3172998068 Aug 25 07:46:30 AM UTC 24 Aug 25 07:46:33 AM UTC 24 64080702 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.3195076279 Aug 25 07:46:18 AM UTC 24 Aug 25 07:46:33 AM UTC 24 1220037876 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3900126318 Aug 25 07:46:31 AM UTC 24 Aug 25 07:46:34 AM UTC 24 75117534 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1661693903 Aug 25 07:46:33 AM UTC 24 Aug 25 07:46:36 AM UTC 24 13042818 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.770866696 Aug 25 07:46:28 AM UTC 24 Aug 25 07:46:36 AM UTC 24 582554319 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.2224541899 Aug 25 07:46:18 AM UTC 24 Aug 25 07:46:37 AM UTC 24 1896800621 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.3681269429 Aug 25 07:45:31 AM UTC 24 Aug 25 07:46:38 AM UTC 24 1065865976 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1012087630 Aug 25 07:46:22 AM UTC 24 Aug 25 07:46:38 AM UTC 24 272828500 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.166680134 Aug 25 07:46:33 AM UTC 24 Aug 25 07:46:38 AM UTC 24 286349554 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.3182364322 Aug 25 07:46:34 AM UTC 24 Aug 25 07:46:39 AM UTC 24 981374788 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1988874841 Aug 25 07:46:34 AM UTC 24 Aug 25 07:46:40 AM UTC 24 81939452 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.41583098 Aug 25 07:44:46 AM UTC 24 Aug 25 07:46:41 AM UTC 24 5100805674 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.2744855261 Aug 25 07:46:30 AM UTC 24 Aug 25 07:46:42 AM UTC 24 275614724 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2752331929 Aug 25 07:46:40 AM UTC 24 Aug 25 07:46:43 AM UTC 24 64696017 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.4248609976 Aug 25 07:46:21 AM UTC 24 Aug 25 07:46:43 AM UTC 24 786074246 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3268894719 Aug 25 07:46:41 AM UTC 24 Aug 25 07:46:46 AM UTC 24 220711971 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1114015011 Aug 25 07:46:30 AM UTC 24 Aug 25 07:46:46 AM UTC 24 252661153 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.3756541891 Aug 25 07:46:30 AM UTC 24 Aug 25 07:46:46 AM UTC 24 1252992944 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.925245031 Aug 25 07:46:30 AM UTC 24 Aug 25 07:46:47 AM UTC 24 1259051059 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3292525438 Aug 25 07:46:45 AM UTC 24 Aug 25 07:46:50 AM UTC 24 189748885 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.426873886 Aug 25 07:46:21 AM UTC 24 Aug 25 07:46:52 AM UTC 24 919112494 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.3134903212 Aug 25 07:46:34 AM UTC 24 Aug 25 07:46:52 AM UTC 24 286997701 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3331100807 Aug 25 07:46:36 AM UTC 24 Aug 25 07:46:53 AM UTC 24 1901521362 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.935756781 Aug 25 07:46:38 AM UTC 24 Aug 25 07:46:54 AM UTC 24 829260767 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3830763227 Aug 25 07:46:54 AM UTC 24 Aug 25 07:46:56 AM UTC 24 21736633 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.453956296 Aug 25 07:46:54 AM UTC 24 Aug 25 07:46:56 AM UTC 24 37564745 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.4221358768 Aug 25 07:46:54 AM UTC 24 Aug 25 07:46:57 AM UTC 24 16318997 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2800717006 Aug 25 07:46:36 AM UTC 24 Aug 25 07:46:57 AM UTC 24 2011710125 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.2330983823 Aug 25 07:46:44 AM UTC 24 Aug 25 07:46:58 AM UTC 24 51089663 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.2169029445 Aug 25 07:45:38 AM UTC 24 Aug 25 07:46:59 AM UTC 24 8406706556 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.3586055136 Aug 25 07:46:47 AM UTC 24 Aug 25 07:47:01 AM UTC 24 207468198 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1603358476 Aug 25 07:46:30 AM UTC 24 Aug 25 07:47:01 AM UTC 24 2266462211 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.3881827584 Aug 25 07:46:40 AM UTC 24 Aug 25 07:47:02 AM UTC 24 611767755 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.1284923970 Aug 25 07:46:57 AM UTC 24 Aug 25 07:47:03 AM UTC 24 57326276 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1990025055 Aug 25 07:46:35 AM UTC 24 Aug 25 07:47:04 AM UTC 24 595546716 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.35084174 Aug 25 07:46:06 AM UTC 24 Aug 25 07:47:04 AM UTC 24 267655880 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.198865297 Aug 25 07:46:45 AM UTC 24 Aug 25 07:47:05 AM UTC 24 260764795 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2176166626 Aug 25 07:46:45 AM UTC 24 Aug 25 07:47:05 AM UTC 24 6296720736 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.371279562 Aug 25 07:46:47 AM UTC 24 Aug 25 07:47:05 AM UTC 24 8600316733 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.743227229 Aug 25 07:46:47 AM UTC 24 Aug 25 07:47:07 AM UTC 24 1502606308 ps
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