| T811 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.722723002 |
|
|
Aug 25 07:49:56 AM UTC 24 |
Aug 25 07:50:30 AM UTC 24 |
2863833104 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.594145505 |
|
|
Aug 25 07:50:15 AM UTC 24 |
Aug 25 07:50:32 AM UTC 24 |
198966763 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3437054199 |
|
|
Aug 25 07:49:08 AM UTC 24 |
Aug 25 07:50:32 AM UTC 24 |
6183958332 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.3624962275 |
|
|
Aug 25 07:50:16 AM UTC 24 |
Aug 25 07:50:32 AM UTC 24 |
1597549701 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.589330032 |
|
|
Aug 25 07:50:16 AM UTC 24 |
Aug 25 07:50:32 AM UTC 24 |
636526463 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.527083203 |
|
|
Aug 25 07:50:23 AM UTC 24 |
Aug 25 07:50:32 AM UTC 24 |
1890959614 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.1788435152 |
|
|
Aug 25 07:48:59 AM UTC 24 |
Aug 25 07:51:05 AM UTC 24 |
8078531481 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.2548689708 |
|
|
Aug 25 07:50:28 AM UTC 24 |
Aug 25 07:50:33 AM UTC 24 |
63111859 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3510213949 |
|
|
Aug 25 07:50:20 AM UTC 24 |
Aug 25 07:50:33 AM UTC 24 |
599803376 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1315849566 |
|
|
Aug 25 07:50:33 AM UTC 24 |
Aug 25 07:50:36 AM UTC 24 |
61162232 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.844265666 |
|
|
Aug 25 07:50:08 AM UTC 24 |
Aug 25 07:50:36 AM UTC 24 |
3043832662 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2583133082 |
|
|
Aug 25 07:50:30 AM UTC 24 |
Aug 25 07:50:36 AM UTC 24 |
174267582 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.2298459047 |
|
|
Aug 25 07:47:50 AM UTC 24 |
Aug 25 07:50:37 AM UTC 24 |
5329579334 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.494372925 |
|
|
Aug 25 07:50:34 AM UTC 24 |
Aug 25 07:50:37 AM UTC 24 |
74516446 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2874291341 |
|
|
Aug 25 07:50:21 AM UTC 24 |
Aug 25 07:50:40 AM UTC 24 |
358351650 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.1113339294 |
|
|
Aug 25 07:50:34 AM UTC 24 |
Aug 25 07:50:40 AM UTC 24 |
181945149 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1061801603 |
|
|
Aug 25 07:50:23 AM UTC 24 |
Aug 25 07:50:41 AM UTC 24 |
893473619 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3475321154 |
|
|
Aug 25 07:50:30 AM UTC 24 |
Aug 25 07:50:42 AM UTC 24 |
208738445 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.3695539016 |
|
|
Aug 25 07:50:15 AM UTC 24 |
Aug 25 07:50:42 AM UTC 24 |
1649454105 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1397287637 |
|
|
Aug 25 07:50:21 AM UTC 24 |
Aug 25 07:50:42 AM UTC 24 |
1404810024 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.141246927 |
|
|
Aug 25 07:50:28 AM UTC 24 |
Aug 25 07:50:42 AM UTC 24 |
85780454 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3502678074 |
|
|
Aug 25 07:50:23 AM UTC 24 |
Aug 25 07:50:43 AM UTC 24 |
542146252 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1391055791 |
|
|
Aug 25 07:50:03 AM UTC 24 |
Aug 25 07:50:43 AM UTC 24 |
160371195 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.4063536589 |
|
|
Aug 25 07:50:35 AM UTC 24 |
Aug 25 07:51:06 AM UTC 24 |
282452905 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.193279245 |
|
|
Aug 25 07:50:38 AM UTC 24 |
Aug 25 07:50:44 AM UTC 24 |
325377122 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.3977631885 |
|
|
Aug 25 07:50:37 AM UTC 24 |
Aug 25 07:50:45 AM UTC 24 |
477404472 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.4095257739 |
|
|
Aug 25 07:50:43 AM UTC 24 |
Aug 25 07:50:46 AM UTC 24 |
22177054 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.4103132423 |
|
|
Aug 25 07:50:38 AM UTC 24 |
Aug 25 07:50:46 AM UTC 24 |
268092889 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.4284267923 |
|
|
Aug 25 07:49:57 AM UTC 24 |
Aug 25 07:50:47 AM UTC 24 |
229552567 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.615529396 |
|
|
Aug 25 07:50:33 AM UTC 24 |
Aug 25 07:50:50 AM UTC 24 |
2547995775 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1613142400 |
|
|
Aug 25 07:48:44 AM UTC 24 |
Aug 25 07:50:51 AM UTC 24 |
8853604126 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.214724304 |
|
|
Aug 25 07:50:38 AM UTC 24 |
Aug 25 07:50:53 AM UTC 24 |
2310392241 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.3539743875 |
|
|
Aug 25 07:50:31 AM UTC 24 |
Aug 25 07:50:54 AM UTC 24 |
307819900 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.4205213633 |
|
|
Aug 25 07:50:29 AM UTC 24 |
Aug 25 07:50:55 AM UTC 24 |
1521237992 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.4042612634 |
|
|
Aug 25 07:50:23 AM UTC 24 |
Aug 25 07:50:55 AM UTC 24 |
1321915987 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1082274962 |
|
|
Aug 25 07:50:33 AM UTC 24 |
Aug 25 07:50:56 AM UTC 24 |
2525831239 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.1529659980 |
|
|
Aug 25 07:49:53 AM UTC 24 |
Aug 25 07:50:56 AM UTC 24 |
263648799 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3261412308 |
|
|
Aug 25 07:50:15 AM UTC 24 |
Aug 25 07:50:57 AM UTC 24 |
4691955844 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3325430337 |
|
|
Aug 25 07:50:41 AM UTC 24 |
Aug 25 07:50:58 AM UTC 24 |
324100743 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.274154667 |
|
|
Aug 25 07:48:59 AM UTC 24 |
Aug 25 07:50:59 AM UTC 24 |
18355581288 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.365842946 |
|
|
Aug 25 07:47:43 AM UTC 24 |
Aug 25 07:51:13 AM UTC 24 |
9446267282 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1281609208 |
|
|
Aug 25 07:50:38 AM UTC 24 |
Aug 25 07:50:59 AM UTC 24 |
1490284010 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2901601280 |
|
|
Aug 25 07:50:41 AM UTC 24 |
Aug 25 07:51:00 AM UTC 24 |
7062370008 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1955409923 |
|
|
Aug 25 07:50:20 AM UTC 24 |
Aug 25 07:51:02 AM UTC 24 |
1025321873 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.4088343698 |
|
|
Aug 25 07:50:13 AM UTC 24 |
Aug 25 07:51:02 AM UTC 24 |
232317307 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2959939924 |
|
|
Aug 25 07:50:28 AM UTC 24 |
Aug 25 07:51:04 AM UTC 24 |
234623729 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.253225958 |
|
|
Aug 25 07:50:42 AM UTC 24 |
Aug 25 07:51:16 AM UTC 24 |
5626806561 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1118211552 |
|
|
Aug 25 07:47:52 AM UTC 24 |
Aug 25 07:51:16 AM UTC 24 |
15433906279 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2852597040 |
|
|
Aug 25 07:49:23 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
2686062156 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2465536640 |
|
|
Aug 25 07:45:29 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
65692032356 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1892705141 |
|
|
Aug 25 07:50:11 AM UTC 24 |
Aug 25 07:51:39 AM UTC 24 |
19909698755 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1578103846 |
|
|
Aug 25 07:49:41 AM UTC 24 |
Aug 25 07:51:50 AM UTC 24 |
12608906015 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1970722196 |
|
|
Aug 25 07:50:25 AM UTC 24 |
Aug 25 07:52:14 AM UTC 24 |
2131430785 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1607207865 |
|
|
Aug 25 07:48:53 AM UTC 24 |
Aug 25 07:52:28 AM UTC 24 |
4558653016 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.981905424 |
|
|
Aug 25 07:49:17 AM UTC 24 |
Aug 25 07:52:32 AM UTC 24 |
5381760307 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.753118854 |
|
|
Aug 25 07:50:43 AM UTC 24 |
Aug 25 07:52:34 AM UTC 24 |
3373048232 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3418543020 |
|
|
Aug 25 07:50:00 AM UTC 24 |
Aug 25 07:52:39 AM UTC 24 |
4766820726 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3988852567 |
|
|
Aug 25 07:50:16 AM UTC 24 |
Aug 25 07:52:48 AM UTC 24 |
9852158010 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1116529772 |
|
|
Aug 25 07:50:33 AM UTC 24 |
Aug 25 07:52:51 AM UTC 24 |
3744934580 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.3747963590 |
|
|
Aug 25 07:50:23 AM UTC 24 |
Aug 25 07:52:54 AM UTC 24 |
24473947479 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.346460259 |
|
|
Aug 25 07:50:33 AM UTC 24 |
Aug 25 07:53:51 AM UTC 24 |
24435412810 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.623447957 |
|
|
Aug 25 07:46:52 AM UTC 24 |
Aug 25 07:54:46 AM UTC 24 |
19371168776 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3500701609 |
|
|
Aug 25 07:50:16 AM UTC 24 |
Aug 25 07:54:47 AM UTC 24 |
4816793830 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.838783356 |
|
|
Aug 25 07:49:08 AM UTC 24 |
Aug 25 07:55:06 AM UTC 24 |
36519539777 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.698456060 |
|
|
Aug 25 07:47:34 AM UTC 24 |
Aug 25 07:55:47 AM UTC 24 |
152748122375 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2495511984 |
|
|
Aug 25 07:50:43 AM UTC 24 |
Aug 25 07:56:28 AM UTC 24 |
42174227381 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.1109561088 |
|
|
Aug 25 07:48:30 AM UTC 24 |
Aug 25 07:56:32 AM UTC 24 |
16918113488 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3548696693 |
|
|
Aug 25 07:45:51 AM UTC 24 |
Aug 25 07:56:39 AM UTC 24 |
15170717179 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.3530265581 |
|
|
Aug 25 07:45:14 AM UTC 24 |
Aug 25 07:58:09 AM UTC 24 |
74232222121 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4026115708 |
|
|
Aug 25 07:50:44 AM UTC 24 |
Aug 25 07:50:47 AM UTC 24 |
96487375 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3357175497 |
|
|
Aug 25 07:50:45 AM UTC 24 |
Aug 25 07:50:48 AM UTC 24 |
26029592 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3171293768 |
|
|
Aug 25 07:50:44 AM UTC 24 |
Aug 25 07:50:49 AM UTC 24 |
385340961 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3245162025 |
|
|
Aug 25 07:50:47 AM UTC 24 |
Aug 25 07:50:50 AM UTC 24 |
20332686 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2864278790 |
|
|
Aug 25 07:50:46 AM UTC 24 |
Aug 25 07:50:51 AM UTC 24 |
134595110 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.707180082 |
|
|
Aug 25 07:50:48 AM UTC 24 |
Aug 25 07:50:51 AM UTC 24 |
18084493 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2873774755 |
|
|
Aug 25 07:50:48 AM UTC 24 |
Aug 25 07:50:52 AM UTC 24 |
131241570 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3864978846 |
|
|
Aug 25 07:50:47 AM UTC 24 |
Aug 25 07:50:53 AM UTC 24 |
344658095 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2000580026 |
|
|
Aug 25 07:50:45 AM UTC 24 |
Aug 25 07:50:54 AM UTC 24 |
1622737220 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2264977553 |
|
|
Aug 25 07:50:55 AM UTC 24 |
Aug 25 07:50:58 AM UTC 24 |
15317846 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2293000010 |
|
|
Aug 25 07:50:55 AM UTC 24 |
Aug 25 07:50:58 AM UTC 24 |
15134364 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2486173731 |
|
|
Aug 25 07:50:55 AM UTC 24 |
Aug 25 07:50:59 AM UTC 24 |
91549690 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2335253747 |
|
|
Aug 25 07:50:57 AM UTC 24 |
Aug 25 07:51:00 AM UTC 24 |
94999157 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1871611168 |
|
|
Aug 25 07:50:58 AM UTC 24 |
Aug 25 07:51:00 AM UTC 24 |
12723335 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4178726160 |
|
|
Aug 25 07:50:57 AM UTC 24 |
Aug 25 07:51:00 AM UTC 24 |
38954073 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1171792768 |
|
|
Aug 25 07:50:57 AM UTC 24 |
Aug 25 07:51:01 AM UTC 24 |
149462365 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2866101903 |
|
|
Aug 25 07:50:58 AM UTC 24 |
Aug 25 07:51:01 AM UTC 24 |
340021722 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2285436566 |
|
|
Aug 25 07:50:58 AM UTC 24 |
Aug 25 07:51:01 AM UTC 24 |
79805672 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2336403830 |
|
|
Aug 25 07:50:58 AM UTC 24 |
Aug 25 07:51:01 AM UTC 24 |
90388042 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3164718731 |
|
|
Aug 25 07:50:59 AM UTC 24 |
Aug 25 07:51:02 AM UTC 24 |
152425568 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3224294299 |
|
|
Aug 25 07:50:58 AM UTC 24 |
Aug 25 07:51:02 AM UTC 24 |
99008340 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3861531460 |
|
|
Aug 25 07:50:59 AM UTC 24 |
Aug 25 07:51:02 AM UTC 24 |
86518408 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2328829191 |
|
|
Aug 25 07:50:59 AM UTC 24 |
Aug 25 07:51:02 AM UTC 24 |
84108263 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3666971983 |
|
|
Aug 25 07:50:58 AM UTC 24 |
Aug 25 07:51:03 AM UTC 24 |
64831822 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1293949990 |
|
|
Aug 25 07:51:09 AM UTC 24 |
Aug 25 07:51:12 AM UTC 24 |
44869833 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1466334981 |
|
|
Aug 25 07:50:58 AM UTC 24 |
Aug 25 07:51:03 AM UTC 24 |
184249095 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2627970465 |
|
|
Aug 25 07:50:59 AM UTC 24 |
Aug 25 07:51:03 AM UTC 24 |
158940882 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.967426385 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:04 AM UTC 24 |
94884226 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3851378266 |
|
|
Aug 25 07:50:59 AM UTC 24 |
Aug 25 07:51:04 AM UTC 24 |
293220537 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1571818314 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:04 AM UTC 24 |
28578527 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2422365516 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:05 AM UTC 24 |
42665937 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2306350286 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:05 AM UTC 24 |
364168351 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1702948688 |
|
|
Aug 25 07:50:57 AM UTC 24 |
Aug 25 07:51:05 AM UTC 24 |
162750790 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3344406526 |
|
|
Aug 25 07:51:03 AM UTC 24 |
Aug 25 07:51:05 AM UTC 24 |
12890466 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1652890944 |
|
|
Aug 25 07:51:03 AM UTC 24 |
Aug 25 07:51:06 AM UTC 24 |
114930418 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.953490518 |
|
|
Aug 25 07:51:03 AM UTC 24 |
Aug 25 07:51:06 AM UTC 24 |
46307578 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2390311103 |
|
|
Aug 25 07:51:03 AM UTC 24 |
Aug 25 07:51:06 AM UTC 24 |
169506367 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4150321281 |
|
|
Aug 25 07:51:03 AM UTC 24 |
Aug 25 07:51:06 AM UTC 24 |
20391562 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.988770900 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:06 AM UTC 24 |
377344299 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2590452997 |
|
|
Aug 25 07:50:45 AM UTC 24 |
Aug 25 07:51:06 AM UTC 24 |
4038081224 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1383853617 |
|
|
Aug 25 07:51:03 AM UTC 24 |
Aug 25 07:51:06 AM UTC 24 |
299592673 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.691227902 |
|
|
Aug 25 07:51:03 AM UTC 24 |
Aug 25 07:51:07 AM UTC 24 |
198819309 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1779904736 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:07 AM UTC 24 |
637296332 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1712064602 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:07 AM UTC 24 |
155673648 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1719753225 |
|
|
Aug 25 07:51:04 AM UTC 24 |
Aug 25 07:51:07 AM UTC 24 |
52217861 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2949185809 |
|
|
Aug 25 07:51:04 AM UTC 24 |
Aug 25 07:51:08 AM UTC 24 |
148099615 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2249841788 |
|
|
Aug 25 07:51:04 AM UTC 24 |
Aug 25 07:51:08 AM UTC 24 |
486112630 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3614047308 |
|
|
Aug 25 07:51:06 AM UTC 24 |
Aug 25 07:51:08 AM UTC 24 |
18593451 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2428538856 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:08 AM UTC 24 |
261056677 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2284722892 |
|
|
Aug 25 07:51:06 AM UTC 24 |
Aug 25 07:51:09 AM UTC 24 |
15596031 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1769965418 |
|
|
Aug 25 07:51:06 AM UTC 24 |
Aug 25 07:51:09 AM UTC 24 |
55943707 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3456173988 |
|
|
Aug 25 07:51:06 AM UTC 24 |
Aug 25 07:51:09 AM UTC 24 |
96384652 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2788516483 |
|
|
Aug 25 07:51:06 AM UTC 24 |
Aug 25 07:51:09 AM UTC 24 |
123193186 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3586727402 |
|
|
Aug 25 07:51:01 AM UTC 24 |
Aug 25 07:51:09 AM UTC 24 |
420905518 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2745886916 |
|
|
Aug 25 07:51:06 AM UTC 24 |
Aug 25 07:51:09 AM UTC 24 |
45296282 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1864021004 |
|
|
Aug 25 07:51:06 AM UTC 24 |
Aug 25 07:51:10 AM UTC 24 |
162911024 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2875764430 |
|
|
Aug 25 07:51:11 AM UTC 24 |
Aug 25 07:51:16 AM UTC 24 |
107144967 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2294035805 |
|
|
Aug 25 07:51:04 AM UTC 24 |
Aug 25 07:51:10 AM UTC 24 |
419843345 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3196162106 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:10 AM UTC 24 |
136610206 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2256600457 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:11 AM UTC 24 |
49851181 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.564714070 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:11 AM UTC 24 |
23283356 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1181781183 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:11 AM UTC 24 |
62952145 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4076272246 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:11 AM UTC 24 |
240344006 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2444544856 |
|
|
Aug 25 07:51:14 AM UTC 24 |
Aug 25 07:51:16 AM UTC 24 |
24408660 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1410101108 |
|
|
Aug 25 07:51:06 AM UTC 24 |
Aug 25 07:51:11 AM UTC 24 |
698084254 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.155965602 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:12 AM UTC 24 |
108065954 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3511801961 |
|
|
Aug 25 07:51:09 AM UTC 24 |
Aug 25 07:51:12 AM UTC 24 |
15458267 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2649572905 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:13 AM UTC 24 |
79973992 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3161305550 |
|
|
Aug 25 07:51:09 AM UTC 24 |
Aug 25 07:51:13 AM UTC 24 |
25529673 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2068013900 |
|
|
Aug 25 07:51:09 AM UTC 24 |
Aug 25 07:51:13 AM UTC 24 |
151231087 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3051162448 |
|
|
Aug 25 07:51:10 AM UTC 24 |
Aug 25 07:51:13 AM UTC 24 |
24009205 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1642390102 |
|
|
Aug 25 07:51:11 AM UTC 24 |
Aug 25 07:51:13 AM UTC 24 |
24490406 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3347790159 |
|
|
Aug 25 07:51:11 AM UTC 24 |
Aug 25 07:51:14 AM UTC 24 |
47086505 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2911222945 |
|
|
Aug 25 07:51:04 AM UTC 24 |
Aug 25 07:51:15 AM UTC 24 |
609221360 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.713123246 |
|
|
Aug 25 07:51:09 AM UTC 24 |
Aug 25 07:51:15 AM UTC 24 |
360610004 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1202215714 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:15 AM UTC 24 |
478634738 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3683010080 |
|
|
Aug 25 07:51:11 AM UTC 24 |
Aug 25 07:51:15 AM UTC 24 |
57671434 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2518103714 |
|
|
Aug 25 07:51:12 AM UTC 24 |
Aug 25 07:51:15 AM UTC 24 |
87992184 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3655877557 |
|
|
Aug 25 07:51:12 AM UTC 24 |
Aug 25 07:51:15 AM UTC 24 |
48750392 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.516783989 |
|
|
Aug 25 07:51:12 AM UTC 24 |
Aug 25 07:51:16 AM UTC 24 |
185965094 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1638244679 |
|
|
Aug 25 07:50:57 AM UTC 24 |
Aug 25 07:51:16 AM UTC 24 |
2222382500 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.238201700 |
|
|
Aug 25 07:51:14 AM UTC 24 |
Aug 25 07:51:17 AM UTC 24 |
51895190 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.455201542 |
|
|
Aug 25 07:51:14 AM UTC 24 |
Aug 25 07:51:17 AM UTC 24 |
16036566 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3966974688 |
|
|
Aug 25 07:51:14 AM UTC 24 |
Aug 25 07:51:18 AM UTC 24 |
335155369 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2294913335 |
|
|
Aug 25 07:51:12 AM UTC 24 |
Aug 25 07:51:18 AM UTC 24 |
98984015 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3315243893 |
|
|
Aug 25 07:51:14 AM UTC 24 |
Aug 25 07:51:18 AM UTC 24 |
588903774 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4200157541 |
|
|
Aug 25 07:51:09 AM UTC 24 |
Aug 25 07:51:18 AM UTC 24 |
1692757262 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2950238189 |
|
|
Aug 25 07:51:11 AM UTC 24 |
Aug 25 07:51:19 AM UTC 24 |
130226541 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3106470207 |
|
|
Aug 25 07:51:14 AM UTC 24 |
Aug 25 07:51:19 AM UTC 24 |
247068201 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.596112729 |
|
|
Aug 25 07:51:14 AM UTC 24 |
Aug 25 07:51:19 AM UTC 24 |
42419371 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.481356773 |
|
|
Aug 25 07:51:17 AM UTC 24 |
Aug 25 07:51:19 AM UTC 24 |
13771295 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3918860040 |
|
|
Aug 25 07:51:16 AM UTC 24 |
Aug 25 07:51:19 AM UTC 24 |
74209539 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2545503765 |
|
|
Aug 25 07:51:12 AM UTC 24 |
Aug 25 07:51:19 AM UTC 24 |
300762346 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3767029792 |
|
|
Aug 25 07:51:15 AM UTC 24 |
Aug 25 07:51:19 AM UTC 24 |
257818210 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.486090254 |
|
|
Aug 25 07:51:17 AM UTC 24 |
Aug 25 07:51:20 AM UTC 24 |
86603365 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3273393358 |
|
|
Aug 25 07:51:17 AM UTC 24 |
Aug 25 07:51:20 AM UTC 24 |
131799717 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2374045296 |
|
|
Aug 25 07:51:04 AM UTC 24 |
Aug 25 07:51:20 AM UTC 24 |
886728370 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.281602145 |
|
|
Aug 25 07:51:16 AM UTC 24 |
Aug 25 07:51:20 AM UTC 24 |
181579232 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.662152832 |
|
|
Aug 25 07:51:14 AM UTC 24 |
Aug 25 07:51:20 AM UTC 24 |
2232464136 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3527429760 |
|
|
Aug 25 07:51:19 AM UTC 24 |
Aug 25 07:51:21 AM UTC 24 |
39986698 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3335505333 |
|
|
Aug 25 07:51:18 AM UTC 24 |
Aug 25 07:51:21 AM UTC 24 |
24273569 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.86459047 |
|
|
Aug 25 07:51:03 AM UTC 24 |
Aug 25 07:51:22 AM UTC 24 |
969266597 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2226671993 |
|
|
Aug 25 07:51:18 AM UTC 24 |
Aug 25 07:51:22 AM UTC 24 |
122686043 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3150549480 |
|
|
Aug 25 07:51:18 AM UTC 24 |
Aug 25 07:51:22 AM UTC 24 |
223630148 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4182688282 |
|
|
Aug 25 07:51:17 AM UTC 24 |
Aug 25 07:51:22 AM UTC 24 |
73388868 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2775357896 |
|
|
Aug 25 07:51:20 AM UTC 24 |
Aug 25 07:51:22 AM UTC 24 |
28602396 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3360811704 |
|
|
Aug 25 07:51:19 AM UTC 24 |
Aug 25 07:51:23 AM UTC 24 |
97151728 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1332630419 |
|
|
Aug 25 07:51:20 AM UTC 24 |
Aug 25 07:51:23 AM UTC 24 |
16600074 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1077911570 |
|
|
Aug 25 07:51:20 AM UTC 24 |
Aug 25 07:51:23 AM UTC 24 |
72111400 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3019056157 |
|
|
Aug 25 07:51:20 AM UTC 24 |
Aug 25 07:51:23 AM UTC 24 |
990590605 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2274618272 |
|
|
Aug 25 07:51:18 AM UTC 24 |
Aug 25 07:51:24 AM UTC 24 |
95505012 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2409126344 |
|
|
Aug 25 07:51:17 AM UTC 24 |
Aug 25 07:51:24 AM UTC 24 |
118313697 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3288776519 |
|
|
Aug 25 07:51:18 AM UTC 24 |
Aug 25 07:51:24 AM UTC 24 |
859412834 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1126176928 |
|
|
Aug 25 07:51:21 AM UTC 24 |
Aug 25 07:51:24 AM UTC 24 |
67003876 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3932711604 |
|
|
Aug 25 07:51:20 AM UTC 24 |
Aug 25 07:51:25 AM UTC 24 |
119572004 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1653290853 |
|
|
Aug 25 07:51:08 AM UTC 24 |
Aug 25 07:51:25 AM UTC 24 |
667281399 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3694564901 |
|
|
Aug 25 07:51:23 AM UTC 24 |
Aug 25 07:51:25 AM UTC 24 |
38920098 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2167999381 |
|
|
Aug 25 07:51:23 AM UTC 24 |
Aug 25 07:51:25 AM UTC 24 |
19088290 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.279832646 |
|
|
Aug 25 07:51:23 AM UTC 24 |
Aug 25 07:51:26 AM UTC 24 |
19473946 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3789059329 |
|
|
Aug 25 07:51:21 AM UTC 24 |
Aug 25 07:51:26 AM UTC 24 |
237798573 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2983262248 |
|
|
Aug 25 07:51:22 AM UTC 24 |
Aug 25 07:51:26 AM UTC 24 |
163070778 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.925011452 |
|
|
Aug 25 07:51:23 AM UTC 24 |
Aug 25 07:51:26 AM UTC 24 |
220976000 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2467244410 |
|
|
Aug 25 07:51:07 AM UTC 24 |
Aug 25 07:51:26 AM UTC 24 |
6070131934 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.525116575 |
|
|
Aug 25 07:51:23 AM UTC 24 |
Aug 25 07:51:26 AM UTC 24 |
64945758 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1218121275 |
|
|
Aug 25 07:51:20 AM UTC 24 |
Aug 25 07:51:26 AM UTC 24 |
818295773 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3502432305 |
|
|
Aug 25 07:51:12 AM UTC 24 |
Aug 25 07:51:27 AM UTC 24 |
591229625 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2159727608 |
|
|
Aug 25 07:51:24 AM UTC 24 |
Aug 25 07:51:27 AM UTC 24 |
25550612 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2626353722 |
|
|
Aug 25 07:51:18 AM UTC 24 |
Aug 25 07:51:27 AM UTC 24 |
2190854902 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3770029383 |
|
|
Aug 25 07:51:24 AM UTC 24 |
Aug 25 07:51:27 AM UTC 24 |
30774245 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2010332900 |
|
|
Aug 25 07:51:22 AM UTC 24 |
Aug 25 07:51:28 AM UTC 24 |
43968012 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.313723567 |
|
|
Aug 25 07:51:26 AM UTC 24 |
Aug 25 07:51:28 AM UTC 24 |
48423663 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.445185277 |
|
|
Aug 25 07:51:23 AM UTC 24 |
Aug 25 07:51:28 AM UTC 24 |
339061802 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2542462679 |
|
|
Aug 25 07:51:24 AM UTC 24 |
Aug 25 07:51:28 AM UTC 24 |
150145009 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2800723932 |
|
|
Aug 25 07:51:15 AM UTC 24 |
Aug 25 07:51:28 AM UTC 24 |
691769452 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.441501061 |
|
|
Aug 25 07:51:21 AM UTC 24 |
Aug 25 07:51:28 AM UTC 24 |
1242819264 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2492984395 |
|
|
Aug 25 07:51:24 AM UTC 24 |
Aug 25 07:51:29 AM UTC 24 |
77685466 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2118800271 |
|
|
Aug 25 07:51:24 AM UTC 24 |
Aug 25 07:51:29 AM UTC 24 |
1604585515 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.993976058 |
|
|
Aug 25 07:51:21 AM UTC 24 |
Aug 25 07:51:29 AM UTC 24 |
848581105 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2096762440 |
|
|
Aug 25 07:51:25 AM UTC 24 |
Aug 25 07:51:29 AM UTC 24 |
23244341 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2018022355 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:29 AM UTC 24 |
28311861 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1309123760 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:30 AM UTC 24 |
47769291 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3989242571 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:30 AM UTC 24 |
48248880 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3941964834 |
|
|
Aug 25 07:51:25 AM UTC 24 |
Aug 25 07:51:30 AM UTC 24 |
175389246 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3615100824 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:30 AM UTC 24 |
217224351 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.275362448 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:30 AM UTC 24 |
64093996 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2127357516 |
|
|
Aug 25 07:51:29 AM UTC 24 |
Aug 25 07:51:31 AM UTC 24 |
17573703 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.120080052 |
|
|
Aug 25 07:50:57 AM UTC 24 |
Aug 25 07:51:31 AM UTC 24 |
2205505994 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2181254092 |
|
|
Aug 25 07:51:29 AM UTC 24 |
Aug 25 07:51:31 AM UTC 24 |
32141889 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4127811158 |
|
|
Aug 25 07:51:23 AM UTC 24 |
Aug 25 07:51:31 AM UTC 24 |
486773511 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.278129842 |
|
|
Aug 25 07:51:29 AM UTC 24 |
Aug 25 07:51:32 AM UTC 24 |
122201783 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.622988712 |
|
|
Aug 25 07:51:29 AM UTC 24 |
Aug 25 07:51:32 AM UTC 24 |
23459099 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3715624780 |
|
|
Aug 25 07:51:26 AM UTC 24 |
Aug 25 07:51:32 AM UTC 24 |
686650702 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2466200271 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:32 AM UTC 24 |
96081310 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2713931136 |
|
|
Aug 25 07:51:21 AM UTC 24 |
Aug 25 07:51:32 AM UTC 24 |
776718131 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.615862156 |
|
|
Aug 25 07:51:29 AM UTC 24 |
Aug 25 07:51:32 AM UTC 24 |
190614127 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4068617605 |
|
|
Aug 25 07:51:29 AM UTC 24 |
Aug 25 07:51:32 AM UTC 24 |
38507567 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1998623889 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:32 AM UTC 24 |
892034712 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3803790829 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:33 AM UTC 24 |
245766118 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2779941927 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:33 AM UTC 24 |
37225788 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3180240163 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:33 AM UTC 24 |
18496206 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.715411625 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:33 AM UTC 24 |
15083018 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3818116708 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
49297797 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.546471482 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
47283959 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.577252970 |
|
|
Aug 25 07:51:32 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
20256042 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4060730423 |
|
|
Aug 25 07:51:27 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
90380665 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2656646840 |
|
|
Aug 25 07:51:32 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
60027182 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3959528260 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
96322724 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.259205913 |
|
|
Aug 25 07:51:29 AM UTC 24 |
Aug 25 07:51:34 AM UTC 24 |
177355808 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3878484279 |
|
|
Aug 25 07:51:31 AM UTC 24 |
Aug 25 07:51:35 AM UTC 24 |
33278089 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3023297508 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:35 AM UTC 24 |
203448679 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.860720107 |
|
|
Aug 25 07:51:32 AM UTC 24 |
Aug 25 07:51:35 AM UTC 24 |
28166930 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3532854860 |
|
|
Aug 25 07:51:32 AM UTC 24 |
Aug 25 07:51:36 AM UTC 24 |
39251361 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.349791336 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:36 AM UTC 24 |
41485547 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1227277842 |
|
|
Aug 25 07:51:29 AM UTC 24 |
Aug 25 07:51:36 AM UTC 24 |
364599882 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.565825390 |
|
|
Aug 25 07:51:30 AM UTC 24 |
Aug 25 07:51:37 AM UTC 24 |
306648673 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2894618872 |
|
|
Aug 25 07:51:34 AM UTC 24 |
Aug 25 07:51:37 AM UTC 24 |
23065327 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1424671065 |
|
|
Aug 25 07:51:34 AM UTC 24 |
Aug 25 07:51:38 AM UTC 24 |
22267479 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2350569897 |
|
|
Aug 25 07:51:34 AM UTC 24 |
Aug 25 07:51:38 AM UTC 24 |
100424547 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3130523439 |
|
|
Aug 25 07:51:32 AM UTC 24 |
Aug 25 07:51:38 AM UTC 24 |
106624300 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.93751183 |
|
|
Aug 25 07:51:34 AM UTC 24 |
Aug 25 07:51:38 AM UTC 24 |
164785404 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1705106981 |
|
|
Aug 25 07:51:34 AM UTC 24 |
Aug 25 07:51:39 AM UTC 24 |
74858039 ps |