| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.27 | 97.92 | 95.93 | 93.40 | 100.00 | 98.52 | 99.00 | 96.11 |
| T1001 | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2376014991 | Aug 25 07:51:09 AM UTC 24 | Aug 25 07:51:47 AM UTC 24 | 8995904756 ps | ||
| T1002 | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3289043346 | Aug 25 07:51:18 AM UTC 24 | Aug 25 07:51:50 AM UTC 24 | 4135717100 ps | ||
| T1003 | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2346206707 | Aug 25 07:51:12 AM UTC 24 | Aug 25 07:51:54 AM UTC 24 | 6915732140 ps | ||
| T1004 | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3884273093 | Aug 25 07:51:15 AM UTC 24 | Aug 25 07:52:03 AM UTC 24 | 7250513363 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1539626687 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 50910960 ps |
| CPU time | 4.86 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:39:45 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539626687 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1539626687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.30179150 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3005000511 ps |
| CPU time | 24.72 seconds |
| Started | Aug 25 07:39:36 AM UTC 24 |
| Finished | Aug 25 07:40:03 AM UTC 24 |
| Peak memory | 261044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30179150 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_state_post_trans.30179150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.647479986 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 226735160 ps |
| CPU time | 15.42 seconds |
| Started | Aug 25 07:39:35 AM UTC 24 |
| Finished | Aug 25 07:39:52 AM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647479986 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.647479986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2881937273 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 315442464 ps |
| CPU time | 18.83 seconds |
| Started | Aug 25 07:39:38 AM UTC 24 |
| Finished | Aug 25 07:39:58 AM UTC 24 |
| Peak memory | 238180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881937273 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2881937273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.284100665 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8207672107 ps |
| CPU time | 54.98 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:40:36 AM UTC 24 |
| Peak memory | 263028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284100665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.284100665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2809155336 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 897297614 ps |
| CPU time | 80.59 seconds |
| Started | Aug 25 07:40:36 AM UTC 24 |
| Finished | Aug 25 07:41:58 AM UTC 24 |
| Peak memory | 298424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809155336 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2809155336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2758384923 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 919260677 ps |
| CPU time | 56.19 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:40:37 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758384923 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2758384923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4178726160 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 38954073 ps |
| CPU time | 1.94 seconds |
| Started | Aug 25 07:50:57 AM UTC 24 |
| Finished | Aug 25 07:51:00 AM UTC 24 |
| Peak memory | 228964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4178726160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4178726160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.658780069 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1730516643 ps |
| CPU time | 23.12 seconds |
| Started | Aug 25 07:39:40 AM UTC 24 |
| Finished | Aug 25 07:40:05 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658780069 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.658780069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.477217609 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 582853260 ps |
| CPU time | 11.54 seconds |
| Started | Aug 25 07:39:45 AM UTC 24 |
| Finished | Aug 25 07:39:58 AM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477217609 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.477217609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.1919348128 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3256472191 ps |
| CPU time | 138.5 seconds |
| Started | Aug 25 07:40:57 AM UTC 24 |
| Finished | Aug 25 07:43:18 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1919348128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 4.lc_ctrl_stress_all.1919348128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.4101831969 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 380610051 ps |
| CPU time | 15.59 seconds |
| Started | Aug 25 07:41:36 AM UTC 24 |
| Finished | Aug 25 07:41:53 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101831969 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_toke n_mux.4101831969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1868393580 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 7418069889 ps |
| CPU time | 214.45 seconds |
| Started | Aug 25 07:43:49 AM UTC 24 |
| Finished | Aug 25 07:47:27 AM UTC 24 |
| Peak memory | 262828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1868393580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 13.lc_ctrl_stress_all.1868393580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.565832917 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1245417016 ps |
| CPU time | 86.71 seconds |
| Started | Aug 25 07:47:27 AM UTC 24 |
| Finished | Aug 25 07:48:57 AM UTC 24 |
| Peak memory | 281272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=565832917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 28.lc_ctrl_stress_all.565832917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2282204583 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14485252 ps |
| CPU time | 1.42 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:39:42 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282204583 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2282204583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2294035805 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 419843345 ps |
| CPU time | 4.34 seconds |
| Started | Aug 25 07:51:04 AM UTC 24 |
| Finished | Aug 25 07:51:10 AM UTC 24 |
| Peak memory | 223932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294035805 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_t l_intg_err.2294035805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.2240060392 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 15216176856 ps |
| CPU time | 163.47 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:42:26 AM UTC 24 |
| Peak memory | 289516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2240060392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.lc_ctrl_stress_all.2240060392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3164718731 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 152425568 ps |
| CPU time | 1.78 seconds |
| Started | Aug 25 07:50:59 AM UTC 24 |
| Finished | Aug 25 07:51:02 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164718731 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_ aliasing.3164718731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2306350286 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 364168351 ps |
| CPU time | 2.61 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:05 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306350286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2306350286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2475224909 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1395925799 ps |
| CPU time | 81.9 seconds |
| Started | Aug 25 07:39:43 AM UTC 24 |
| Finished | Aug 25 07:41:07 AM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475224909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_c trl_jtag_state_failure.2475224909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1341571376 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 109204706 ps |
| CPU time | 2.89 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:39:44 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341571376 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1341571376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1998623889 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 892034712 ps |
| CPU time | 4.19 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:32 AM UTC 24 |
| Peak memory | 236228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998623889 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_ tl_intg_err.1998623889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1336415646 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 7846111651 ps |
| CPU time | 169.29 seconds |
| Started | Aug 25 07:41:21 AM UTC 24 |
| Finished | Aug 25 07:44:14 AM UTC 24 |
| Peak memory | 281344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336415646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1336415646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.155965602 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 108065954 ps |
| CPU time | 2.62 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:12 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155965602 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.155965602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.178654010 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 313599270 ps |
| CPU time | 20.1 seconds |
| Started | Aug 25 07:40:40 AM UTC 24 |
| Finished | Aug 25 07:41:02 AM UTC 24 |
| Peak memory | 262768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178654010 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.178654010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2082876509 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 669935179 ps |
| CPU time | 78.45 seconds |
| Started | Aug 25 07:39:59 AM UTC 24 |
| Finished | Aug 25 07:41:20 AM UTC 24 |
| Peak memory | 290132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082876509 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2082876509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3023297508 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 203448679 ps |
| CPU time | 3.17 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:35 AM UTC 24 |
| Peak memory | 236224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023297508 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_ tl_intg_err.3023297508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3130523439 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 106624300 ps |
| CPU time | 4.8 seconds |
| Started | Aug 25 07:51:32 AM UTC 24 |
| Finished | Aug 25 07:51:38 AM UTC 24 |
| Peak memory | 224132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130523439 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_ tl_intg_err.3130523439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3678835513 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 15363436 ps |
| CPU time | 1.49 seconds |
| Started | Aug 25 07:39:34 AM UTC 24 |
| Finished | Aug 25 07:39:37 AM UTC 24 |
| Peak memory | 223148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678835513 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_volatile_unlock_smoke.3678835513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.980448946 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1479782472 ps |
| CPU time | 102.09 seconds |
| Started | Aug 25 07:40:47 AM UTC 24 |
| Finished | Aug 25 07:42:32 AM UTC 24 |
| Peak memory | 258692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980448946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct rl_jtag_state_failure.980448946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3357175497 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 26029592 ps |
| CPU time | 2.19 seconds |
| Started | Aug 25 07:50:45 AM UTC 24 |
| Finished | Aug 25 07:50:48 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3357175497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3357175497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1064963350 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5327022843 ps |
| CPU time | 86.75 seconds |
| Started | Aug 25 07:43:16 AM UTC 24 |
| Finished | Aug 25 07:44:45 AM UTC 24 |
| Peak memory | 281420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064963350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.1064963350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.347948180 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5898482122 ps |
| CPU time | 32.64 seconds |
| Started | Aug 25 07:39:38 AM UTC 24 |
| Finished | Aug 25 07:40:12 AM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347948180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc _ctrl_jtag_regwen_during_op.347948180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.3549783650 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 454907553 ps |
| CPU time | 21.19 seconds |
| Started | Aug 25 07:39:48 AM UTC 24 |
| Finished | Aug 25 07:40:11 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549783650 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3549783650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3715624780 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 686650702 ps |
| CPU time | 4.82 seconds |
| Started | Aug 25 07:51:26 AM UTC 24 |
| Finished | Aug 25 07:51:32 AM UTC 24 |
| Peak memory | 223940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715624780 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_ tl_intg_err.3715624780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1227277842 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 364599882 ps |
| CPU time | 5.84 seconds |
| Started | Aug 25 07:51:29 AM UTC 24 |
| Finished | Aug 25 07:51:36 AM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227277842 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_ tl_intg_err.1227277842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2409126344 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 118313697 ps |
| CPU time | 6.13 seconds |
| Started | Aug 25 07:51:17 AM UTC 24 |
| Finished | Aug 25 07:51:24 AM UTC 24 |
| Peak memory | 230108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409126344 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_t l_intg_err.2409126344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3907733882 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12763802 ps |
| CPU time | 1.2 seconds |
| Started | Aug 25 07:39:35 AM UTC 24 |
| Finished | Aug 25 07:39:38 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907733882 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3907733882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1185753069 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1240449206 ps |
| CPU time | 28.57 seconds |
| Started | Aug 25 07:43:07 AM UTC 24 |
| Finished | Aug 25 07:43:37 AM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185753069 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1185753069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3546167051 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 21632109 ps |
| CPU time | 1.31 seconds |
| Started | Aug 25 07:40:24 AM UTC 24 |
| Finished | Aug 25 07:40:26 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546167051 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3546167051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.623073741 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 28065323 ps |
| CPU time | 1.2 seconds |
| Started | Aug 25 07:42:11 AM UTC 24 |
| Finished | Aug 25 07:42:14 AM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623073741 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.623073741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2407280480 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 529999716 ps |
| CPU time | 24.27 seconds |
| Started | Aug 25 07:39:35 AM UTC 24 |
| Finished | Aug 25 07:40:01 AM UTC 24 |
| Peak memory | 232540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407280480 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2407280480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3245162025 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 20332686 ps |
| CPU time | 1.41 seconds |
| Started | Aug 25 07:50:47 AM UTC 24 |
| Finished | Aug 25 07:50:50 AM UTC 24 |
| Peak memory | 219100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3245162025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3245162025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.565825390 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 306648673 ps |
| CPU time | 5.12 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:37 AM UTC 24 |
| Peak memory | 236196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565825390 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_t l_intg_err.565825390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1705106981 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 74858039 ps |
| CPU time | 4.17 seconds |
| Started | Aug 25 07:51:34 AM UTC 24 |
| Finished | Aug 25 07:51:39 AM UTC 24 |
| Peak memory | 236496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705106981 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_ tl_intg_err.1705106981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3106470207 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 247068201 ps |
| CPU time | 4.11 seconds |
| Started | Aug 25 07:51:14 AM UTC 24 |
| Finished | Aug 25 07:51:19 AM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106470207 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_t l_intg_err.3106470207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2264977553 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 15317846 ps |
| CPU time | 1.3 seconds |
| Started | Aug 25 07:50:55 AM UTC 24 |
| Finished | Aug 25 07:50:58 AM UTC 24 |
| Peak memory | 219324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264977553 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_ aliasing.2264977553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2486173731 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 91549690 ps |
| CPU time | 3.31 seconds |
| Started | Aug 25 07:50:55 AM UTC 24 |
| Finished | Aug 25 07:50:59 AM UTC 24 |
| Peak memory | 220112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486173731 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_ bit_bash.2486173731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.707180082 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 18084493 ps |
| CPU time | 1.72 seconds |
| Started | Aug 25 07:50:48 AM UTC 24 |
| Finished | Aug 25 07:50:51 AM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707180082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_h w_reset.707180082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2293000010 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 15134364 ps |
| CPU time | 1.75 seconds |
| Started | Aug 25 07:50:55 AM UTC 24 |
| Finished | Aug 25 07:50:58 AM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293000010 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2293000010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2000580026 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1622737220 ps |
| CPU time | 7.59 seconds |
| Started | Aug 25 07:50:45 AM UTC 24 |
| Finished | Aug 25 07:50:54 AM UTC 24 |
| Peak memory | 219080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2000580026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2000580026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2590452997 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 4038081224 ps |
| CPU time | 19.79 seconds |
| Started | Aug 25 07:50:45 AM UTC 24 |
| Finished | Aug 25 07:51:06 AM UTC 24 |
| Peak memory | 219924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2590452997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2590452997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3171293768 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 385340961 ps |
| CPU time | 3.87 seconds |
| Started | Aug 25 07:50:44 AM UTC 24 |
| Finished | Aug 25 07:50:49 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3171293768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3171293768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2864278790 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 134595110 ps |
| CPU time | 3.89 seconds |
| Started | Aug 25 07:50:46 AM UTC 24 |
| Finished | Aug 25 07:50:51 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864278790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2864278790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4026115708 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 96487375 ps |
| CPU time | 2 seconds |
| Started | Aug 25 07:50:44 AM UTC 24 |
| Finished | Aug 25 07:50:47 AM UTC 24 |
| Peak memory | 219316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=4026115708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.lc_ctrl_jtag_csr_rw.4026115708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2335253747 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 94999157 ps |
| CPU time | 1.57 seconds |
| Started | Aug 25 07:50:57 AM UTC 24 |
| Finished | Aug 25 07:51:00 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23352 53747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. lc_ctrl_same_csr_outstanding.2335253747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3864978846 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 344658095 ps |
| CPU time | 5 seconds |
| Started | Aug 25 07:50:47 AM UTC 24 |
| Finished | Aug 25 07:50:53 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864978846 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3864978846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2873774755 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 131241570 ps |
| CPU time | 2.73 seconds |
| Started | Aug 25 07:50:48 AM UTC 24 |
| Finished | Aug 25 07:50:52 AM UTC 24 |
| Peak memory | 235812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873774755 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_t l_intg_err.2873774755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2627970465 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 158940882 ps |
| CPU time | 3.08 seconds |
| Started | Aug 25 07:50:59 AM UTC 24 |
| Finished | Aug 25 07:51:03 AM UTC 24 |
| Peak memory | 220024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627970465 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_ bit_bash.2627970465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2866101903 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 340021722 ps |
| CPU time | 1.67 seconds |
| Started | Aug 25 07:50:58 AM UTC 24 |
| Finished | Aug 25 07:51:01 AM UTC 24 |
| Peak memory | 230888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866101903 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_ hw_reset.2866101903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2328829191 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 84108263 ps |
| CPU time | 2.12 seconds |
| Started | Aug 25 07:50:59 AM UTC 24 |
| Finished | Aug 25 07:51:02 AM UTC 24 |
| Peak memory | 234224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2328829191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2328829191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1871611168 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 12723335 ps |
| CPU time | 1.3 seconds |
| Started | Aug 25 07:50:58 AM UTC 24 |
| Finished | Aug 25 07:51:00 AM UTC 24 |
| Peak memory | 218900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871611168 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1871611168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2336403830 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 90388042 ps |
| CPU time | 2.56 seconds |
| Started | Aug 25 07:50:58 AM UTC 24 |
| Finished | Aug 25 07:51:01 AM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2336403830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2336403830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1638244679 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2222382500 ps |
| CPU time | 17.32 seconds |
| Started | Aug 25 07:50:57 AM UTC 24 |
| Finished | Aug 25 07:51:16 AM UTC 24 |
| Peak memory | 219152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1638244679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1638244679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.120080052 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2205505994 ps |
| CPU time | 32.16 seconds |
| Started | Aug 25 07:50:57 AM UTC 24 |
| Finished | Aug 25 07:51:31 AM UTC 24 |
| Peak memory | 220216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=120080052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.120080052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1702948688 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 162750790 ps |
| CPU time | 6.57 seconds |
| Started | Aug 25 07:50:57 AM UTC 24 |
| Finished | Aug 25 07:51:05 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1702948688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1702948688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3224294299 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 99008340 ps |
| CPU time | 3.27 seconds |
| Started | Aug 25 07:50:58 AM UTC 24 |
| Finished | Aug 25 07:51:02 AM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224294299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3224294299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1171792768 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 149462365 ps |
| CPU time | 1.93 seconds |
| Started | Aug 25 07:50:57 AM UTC 24 |
| Finished | Aug 25 07:51:01 AM UTC 24 |
| Peak memory | 219016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1171792768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.lc_ctrl_jtag_csr_rw.1171792768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2285436566 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 79805672 ps |
| CPU time | 2.21 seconds |
| Started | Aug 25 07:50:58 AM UTC 24 |
| Finished | Aug 25 07:51:01 AM UTC 24 |
| Peak memory | 219748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2285436566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2285436566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3861531460 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 86518408 ps |
| CPU time | 1.88 seconds |
| Started | Aug 25 07:50:59 AM UTC 24 |
| Finished | Aug 25 07:51:02 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38615 31460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. lc_ctrl_same_csr_outstanding.3861531460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1466334981 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 184249095 ps |
| CPU time | 4.32 seconds |
| Started | Aug 25 07:50:58 AM UTC 24 |
| Finished | Aug 25 07:51:03 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466334981 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1466334981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3666971983 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 64831822 ps |
| CPU time | 4.11 seconds |
| Started | Aug 25 07:50:58 AM UTC 24 |
| Finished | Aug 25 07:51:03 AM UTC 24 |
| Peak memory | 230160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666971983 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_t l_intg_err.3666971983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3770029383 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 30774245 ps |
| CPU time | 1.87 seconds |
| Started | Aug 25 07:51:24 AM UTC 24 |
| Finished | Aug 25 07:51:27 AM UTC 24 |
| Peak memory | 228968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3770029383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3770029383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2167999381 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 19088290 ps |
| CPU time | 1.23 seconds |
| Started | Aug 25 07:51:23 AM UTC 24 |
| Finished | Aug 25 07:51:25 AM UTC 24 |
| Peak memory | 219256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167999381 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2167999381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.925011452 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 220976000 ps |
| CPU time | 2.02 seconds |
| Started | Aug 25 07:51:23 AM UTC 24 |
| Finished | Aug 25 07:51:26 AM UTC 24 |
| Peak memory | 230216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92501 1452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. lc_ctrl_same_csr_outstanding.925011452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4127811158 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 486773511 ps |
| CPU time | 7.3 seconds |
| Started | Aug 25 07:51:23 AM UTC 24 |
| Finished | Aug 25 07:51:31 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127811158 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.4127811158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.445185277 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 339061802 ps |
| CPU time | 3.77 seconds |
| Started | Aug 25 07:51:23 AM UTC 24 |
| Finished | Aug 25 07:51:28 AM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445185277 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_t l_intg_err.445185277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2096762440 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 23244341 ps |
| CPU time | 2.48 seconds |
| Started | Aug 25 07:51:25 AM UTC 24 |
| Finished | Aug 25 07:51:29 AM UTC 24 |
| Peak memory | 232116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2096762440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2096762440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2159727608 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 25550612 ps |
| CPU time | 1.36 seconds |
| Started | Aug 25 07:51:24 AM UTC 24 |
| Finished | Aug 25 07:51:27 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159727608 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2159727608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2542462679 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 150145009 ps |
| CPU time | 2.68 seconds |
| Started | Aug 25 07:51:24 AM UTC 24 |
| Finished | Aug 25 07:51:28 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25424 62679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .lc_ctrl_same_csr_outstanding.2542462679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2118800271 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 1604585515 ps |
| CPU time | 3.19 seconds |
| Started | Aug 25 07:51:24 AM UTC 24 |
| Finished | Aug 25 07:51:29 AM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118800271 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2118800271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2492984395 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 77685466 ps |
| CPU time | 3.11 seconds |
| Started | Aug 25 07:51:24 AM UTC 24 |
| Finished | Aug 25 07:51:29 AM UTC 24 |
| Peak memory | 224208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492984395 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_ tl_intg_err.2492984395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2018022355 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 28311861 ps |
| CPU time | 1.42 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:29 AM UTC 24 |
| Peak memory | 230976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2018022355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2018022355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.313723567 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 48423663 ps |
| CPU time | 1.06 seconds |
| Started | Aug 25 07:51:26 AM UTC 24 |
| Finished | Aug 25 07:51:28 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313723567 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.313723567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1309123760 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 47769291 ps |
| CPU time | 1.52 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:30 AM UTC 24 |
| Peak memory | 218636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13091 23760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .lc_ctrl_same_csr_outstanding.1309123760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3941964834 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 175389246 ps |
| CPU time | 3.38 seconds |
| Started | Aug 25 07:51:25 AM UTC 24 |
| Finished | Aug 25 07:51:30 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941964834 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3941964834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3615100824 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 217224351 ps |
| CPU time | 1.76 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:30 AM UTC 24 |
| Peak memory | 231016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3615100824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3615100824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3989242571 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 48248880 ps |
| CPU time | 1.5 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:30 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989242571 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3989242571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.275362448 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 64093996 ps |
| CPU time | 1.85 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:30 AM UTC 24 |
| Peak memory | 221132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27536 2448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. lc_ctrl_same_csr_outstanding.275362448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2466200271 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 96081310 ps |
| CPU time | 3.38 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:32 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466200271 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2466200271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.622988712 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 23459099 ps |
| CPU time | 1.73 seconds |
| Started | Aug 25 07:51:29 AM UTC 24 |
| Finished | Aug 25 07:51:32 AM UTC 24 |
| Peak memory | 228968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=622988712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.622988712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2127357516 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 17573703 ps |
| CPU time | 1.38 seconds |
| Started | Aug 25 07:51:29 AM UTC 24 |
| Finished | Aug 25 07:51:31 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127357516 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2127357516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.278129842 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 122201783 ps |
| CPU time | 1.67 seconds |
| Started | Aug 25 07:51:29 AM UTC 24 |
| Finished | Aug 25 07:51:32 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27812 9842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. lc_ctrl_same_csr_outstanding.278129842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4060730423 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 90380665 ps |
| CPU time | 5.58 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060730423 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4060730423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3803790829 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 245766118 ps |
| CPU time | 3.99 seconds |
| Started | Aug 25 07:51:27 AM UTC 24 |
| Finished | Aug 25 07:51:33 AM UTC 24 |
| Peak memory | 236228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803790829 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_ tl_intg_err.3803790829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4068617605 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 38507567 ps |
| CPU time | 2.02 seconds |
| Started | Aug 25 07:51:29 AM UTC 24 |
| Finished | Aug 25 07:51:32 AM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4068617605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.4068617605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2181254092 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 32141889 ps |
| CPU time | 1.37 seconds |
| Started | Aug 25 07:51:29 AM UTC 24 |
| Finished | Aug 25 07:51:31 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181254092 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2181254092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.615862156 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 190614127 ps |
| CPU time | 1.81 seconds |
| Started | Aug 25 07:51:29 AM UTC 24 |
| Finished | Aug 25 07:51:32 AM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61586 2156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. lc_ctrl_same_csr_outstanding.615862156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.259205913 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 177355808 ps |
| CPU time | 4.51 seconds |
| Started | Aug 25 07:51:29 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259205913 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.259205913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.546471482 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 47283959 ps |
| CPU time | 2.16 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=546471482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.546471482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3180240163 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 18496206 ps |
| CPU time | 1.72 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:33 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180240163 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3180240163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3818116708 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 49297797 ps |
| CPU time | 2.11 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 219864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38181 16708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .lc_ctrl_same_csr_outstanding.3818116708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3959528260 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 96322724 ps |
| CPU time | 2.83 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959528260 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3959528260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3878484279 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 33278089 ps |
| CPU time | 2.55 seconds |
| Started | Aug 25 07:51:31 AM UTC 24 |
| Finished | Aug 25 07:51:35 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3878484279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3878484279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2779941927 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 37225788 ps |
| CPU time | 1.31 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:33 AM UTC 24 |
| Peak memory | 218572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779941927 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2779941927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.715411625 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 15083018 ps |
| CPU time | 1.4 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:33 AM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71541 1625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. lc_ctrl_same_csr_outstanding.715411625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.349791336 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 41485547 ps |
| CPU time | 4.01 seconds |
| Started | Aug 25 07:51:30 AM UTC 24 |
| Finished | Aug 25 07:51:36 AM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349791336 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.349791336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2656646840 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 60027182 ps |
| CPU time | 1.45 seconds |
| Started | Aug 25 07:51:32 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 228968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2656646840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2656646840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.577252970 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 20256042 ps |
| CPU time | 1.21 seconds |
| Started | Aug 25 07:51:32 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577252970 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.577252970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3532854860 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 39251361 ps |
| CPU time | 2.71 seconds |
| Started | Aug 25 07:51:32 AM UTC 24 |
| Finished | Aug 25 07:51:36 AM UTC 24 |
| Peak memory | 230272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35328 54860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .lc_ctrl_same_csr_outstanding.3532854860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.860720107 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 28166930 ps |
| CPU time | 2.71 seconds |
| Started | Aug 25 07:51:32 AM UTC 24 |
| Finished | Aug 25 07:51:35 AM UTC 24 |
| Peak memory | 234424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860720107 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.860720107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1424671065 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 22267479 ps |
| CPU time | 2.03 seconds |
| Started | Aug 25 07:51:34 AM UTC 24 |
| Finished | Aug 25 07:51:38 AM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1424671065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1424671065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2894618872 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 23065327 ps |
| CPU time | 1.54 seconds |
| Started | Aug 25 07:51:34 AM UTC 24 |
| Finished | Aug 25 07:51:37 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894618872 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2894618872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.93751183 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 164785404 ps |
| CPU time | 2.75 seconds |
| Started | Aug 25 07:51:34 AM UTC 24 |
| Finished | Aug 25 07:51:38 AM UTC 24 |
| Peak memory | 219768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93751 183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.l c_ctrl_same_csr_outstanding.93751183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2350569897 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 100424547 ps |
| CPU time | 2.37 seconds |
| Started | Aug 25 07:51:34 AM UTC 24 |
| Finished | Aug 25 07:51:38 AM UTC 24 |
| Peak memory | 230148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350569897 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2350569897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2390311103 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 169506367 ps |
| CPU time | 1.83 seconds |
| Started | Aug 25 07:51:03 AM UTC 24 |
| Finished | Aug 25 07:51:06 AM UTC 24 |
| Peak memory | 219092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390311103 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_ aliasing.2390311103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4150321281 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 20391562 ps |
| CPU time | 1.95 seconds |
| Started | Aug 25 07:51:03 AM UTC 24 |
| Finished | Aug 25 07:51:06 AM UTC 24 |
| Peak memory | 219800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150321281 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_ bit_bash.4150321281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1571818314 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 28578527 ps |
| CPU time | 1.37 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:04 AM UTC 24 |
| Peak memory | 220652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571818314 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_ hw_reset.1571818314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1383853617 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 299592673 ps |
| CPU time | 2.39 seconds |
| Started | Aug 25 07:51:03 AM UTC 24 |
| Finished | Aug 25 07:51:06 AM UTC 24 |
| Peak memory | 232108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1383853617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1383853617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3344406526 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 12890466 ps |
| CPU time | 1.42 seconds |
| Started | Aug 25 07:51:03 AM UTC 24 |
| Finished | Aug 25 07:51:05 AM UTC 24 |
| Peak memory | 218608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344406526 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3344406526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.988770900 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 377344299 ps |
| CPU time | 3.53 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:06 AM UTC 24 |
| Peak memory | 219820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=988770900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.988770900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2428538856 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 261056677 ps |
| CPU time | 6.17 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:08 AM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2428538856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2428538856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3586727402 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 420905518 ps |
| CPU time | 6.93 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:09 AM UTC 24 |
| Peak memory | 219736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3586727402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3586727402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3851378266 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 293220537 ps |
| CPU time | 3.57 seconds |
| Started | Aug 25 07:50:59 AM UTC 24 |
| Finished | Aug 25 07:51:04 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3851378266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3851378266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2422365516 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 42665937 ps |
| CPU time | 2.56 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:05 AM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2422365516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.lc_ctrl_jtag_csr_rw.2422365516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.967426385 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 94884226 ps |
| CPU time | 1.5 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:04 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=967426385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.967426385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1652890944 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 114930418 ps |
| CPU time | 1.61 seconds |
| Started | Aug 25 07:51:03 AM UTC 24 |
| Finished | Aug 25 07:51:06 AM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16528 90944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. lc_ctrl_same_csr_outstanding.1652890944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1712064602 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 155673648 ps |
| CPU time | 4.68 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:07 AM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712064602 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1712064602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1779904736 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 637296332 ps |
| CPU time | 4.24 seconds |
| Started | Aug 25 07:51:01 AM UTC 24 |
| Finished | Aug 25 07:51:07 AM UTC 24 |
| Peak memory | 236280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779904736 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_t l_intg_err.1779904736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1864021004 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 162911024 ps |
| CPU time | 2.79 seconds |
| Started | Aug 25 07:51:06 AM UTC 24 |
| Finished | Aug 25 07:51:10 AM UTC 24 |
| Peak memory | 219836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864021004 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_ aliasing.1864021004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1769965418 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 55943707 ps |
| CPU time | 1.85 seconds |
| Started | Aug 25 07:51:06 AM UTC 24 |
| Finished | Aug 25 07:51:09 AM UTC 24 |
| Peak memory | 219244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769965418 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_ bit_bash.1769965418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3614047308 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 18593451 ps |
| CPU time | 1.35 seconds |
| Started | Aug 25 07:51:06 AM UTC 24 |
| Finished | Aug 25 07:51:08 AM UTC 24 |
| Peak memory | 220652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614047308 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_ hw_reset.3614047308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2788516483 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 123193186 ps |
| CPU time | 1.9 seconds |
| Started | Aug 25 07:51:06 AM UTC 24 |
| Finished | Aug 25 07:51:09 AM UTC 24 |
| Peak memory | 233060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2788516483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2788516483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2284722892 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 15596031 ps |
| CPU time | 1.55 seconds |
| Started | Aug 25 07:51:06 AM UTC 24 |
| Finished | Aug 25 07:51:09 AM UTC 24 |
| Peak memory | 219316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284722892 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2284722892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2249841788 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 486112630 ps |
| CPU time | 2.71 seconds |
| Started | Aug 25 07:51:04 AM UTC 24 |
| Finished | Aug 25 07:51:08 AM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2249841788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2249841788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2374045296 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 886728370 ps |
| CPU time | 14.38 seconds |
| Started | Aug 25 07:51:04 AM UTC 24 |
| Finished | Aug 25 07:51:20 AM UTC 24 |
| Peak memory | 219080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2374045296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2374045296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.86459047 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 969266597 ps |
| CPU time | 17.31 seconds |
| Started | Aug 25 07:51:03 AM UTC 24 |
| Finished | Aug 25 07:51:22 AM UTC 24 |
| Peak memory | 218860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=86459047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.86459047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.953490518 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 46307578 ps |
| CPU time | 1.81 seconds |
| Started | Aug 25 07:51:03 AM UTC 24 |
| Finished | Aug 25 07:51:06 AM UTC 24 |
| Peak memory | 221072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=953490518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.953490518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1719753225 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 52217861 ps |
| CPU time | 1.94 seconds |
| Started | Aug 25 07:51:04 AM UTC 24 |
| Finished | Aug 25 07:51:07 AM UTC 24 |
| Peak memory | 228972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719753225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1719753225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.691227902 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 198819309 ps |
| CPU time | 2.79 seconds |
| Started | Aug 25 07:51:03 AM UTC 24 |
| Finished | Aug 25 07:51:07 AM UTC 24 |
| Peak memory | 220024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=691227902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_rw.691227902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2949185809 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 148099615 ps |
| CPU time | 2.72 seconds |
| Started | Aug 25 07:51:04 AM UTC 24 |
| Finished | Aug 25 07:51:08 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2949185809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2949185809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3456173988 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 96384652 ps |
| CPU time | 1.86 seconds |
| Started | Aug 25 07:51:06 AM UTC 24 |
| Finished | Aug 25 07:51:09 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34561 73988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. lc_ctrl_same_csr_outstanding.3456173988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2911222945 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 609221360 ps |
| CPU time | 8.91 seconds |
| Started | Aug 25 07:51:04 AM UTC 24 |
| Finished | Aug 25 07:51:15 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911222945 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2911222945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1293949990 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 44869833 ps |
| CPU time | 1.59 seconds |
| Started | Aug 25 07:51:09 AM UTC 24 |
| Finished | Aug 25 07:51:12 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293949990 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_ aliasing.1293949990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1181781183 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 62952145 ps |
| CPU time | 1.54 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:11 AM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181781183 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_ bit_bash.1181781183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2256600457 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 49851181 ps |
| CPU time | 1.6 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:11 AM UTC 24 |
| Peak memory | 228844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256600457 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_ hw_reset.2256600457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3161305550 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 25529673 ps |
| CPU time | 2.52 seconds |
| Started | Aug 25 07:51:09 AM UTC 24 |
| Finished | Aug 25 07:51:13 AM UTC 24 |
| Peak memory | 236992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3161305550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3161305550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.564714070 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 23283356 ps |
| CPU time | 1.37 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:11 AM UTC 24 |
| Peak memory | 218828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564714070 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.564714070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4076272246 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 240344006 ps |
| CPU time | 2.48 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:11 AM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4076272246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.4076272246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1653290853 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 667281399 ps |
| CPU time | 16.09 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:25 AM UTC 24 |
| Peak memory | 218544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1653290853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1653290853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2467244410 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 6070131934 ps |
| CPU time | 17.44 seconds |
| Started | Aug 25 07:51:07 AM UTC 24 |
| Finished | Aug 25 07:51:26 AM UTC 24 |
| Peak memory | 220092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2467244410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2467244410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1410101108 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 698084254 ps |
| CPU time | 4.04 seconds |
| Started | Aug 25 07:51:06 AM UTC 24 |
| Finished | Aug 25 07:51:11 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1410101108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1410101108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1202215714 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 478634738 ps |
| CPU time | 5.91 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:15 AM UTC 24 |
| Peak memory | 236224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202215714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1202215714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2745886916 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 45296282 ps |
| CPU time | 2.06 seconds |
| Started | Aug 25 07:51:06 AM UTC 24 |
| Finished | Aug 25 07:51:09 AM UTC 24 |
| Peak memory | 219028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2745886916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.lc_ctrl_jtag_csr_rw.2745886916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3196162106 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 136610206 ps |
| CPU time | 1.41 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:10 AM UTC 24 |
| Peak memory | 219184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3196162106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3196162106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3511801961 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 15458267 ps |
| CPU time | 1.85 seconds |
| Started | Aug 25 07:51:09 AM UTC 24 |
| Finished | Aug 25 07:51:12 AM UTC 24 |
| Peak memory | 219088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35118 01961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. lc_ctrl_same_csr_outstanding.3511801961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2649572905 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 79973992 ps |
| CPU time | 3.77 seconds |
| Started | Aug 25 07:51:08 AM UTC 24 |
| Finished | Aug 25 07:51:13 AM UTC 24 |
| Peak memory | 236152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649572905 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_t l_intg_err.2649572905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2518103714 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 87992184 ps |
| CPU time | 2 seconds |
| Started | Aug 25 07:51:12 AM UTC 24 |
| Finished | Aug 25 07:51:15 AM UTC 24 |
| Peak memory | 228964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2518103714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2518103714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1642390102 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 24490406 ps |
| CPU time | 1.44 seconds |
| Started | Aug 25 07:51:11 AM UTC 24 |
| Finished | Aug 25 07:51:13 AM UTC 24 |
| Peak memory | 218608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642390102 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1642390102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3347790159 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 47086505 ps |
| CPU time | 2.23 seconds |
| Started | Aug 25 07:51:11 AM UTC 24 |
| Finished | Aug 25 07:51:14 AM UTC 24 |
| Peak memory | 219772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3347790159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3347790159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4200157541 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 1692757262 ps |
| CPU time | 7.33 seconds |
| Started | Aug 25 07:51:09 AM UTC 24 |
| Finished | Aug 25 07:51:18 AM UTC 24 |
| Peak memory | 219468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=4200157541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4200157541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2376014991 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 8995904756 ps |
| CPU time | 35.42 seconds |
| Started | Aug 25 07:51:09 AM UTC 24 |
| Finished | Aug 25 07:51:47 AM UTC 24 |
| Peak memory | 220120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2376014991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2376014991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.713123246 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 360610004 ps |
| CPU time | 4.18 seconds |
| Started | Aug 25 07:51:09 AM UTC 24 |
| Finished | Aug 25 07:51:15 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=713123246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.713123246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3683010080 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 57671434 ps |
| CPU time | 3.13 seconds |
| Started | Aug 25 07:51:11 AM UTC 24 |
| Finished | Aug 25 07:51:15 AM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683010080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3683010080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2068013900 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 151231087 ps |
| CPU time | 2.4 seconds |
| Started | Aug 25 07:51:09 AM UTC 24 |
| Finished | Aug 25 07:51:13 AM UTC 24 |
| Peak memory | 219752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2068013900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.lc_ctrl_jtag_csr_rw.2068013900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3051162448 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 24009205 ps |
| CPU time | 1.49 seconds |
| Started | Aug 25 07:51:10 AM UTC 24 |
| Finished | Aug 25 07:51:13 AM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3051162448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3051162448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.516783989 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 185965094 ps |
| CPU time | 2.81 seconds |
| Started | Aug 25 07:51:12 AM UTC 24 |
| Finished | Aug 25 07:51:16 AM UTC 24 |
| Peak memory | 230268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51678 3989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.l c_ctrl_same_csr_outstanding.516783989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2950238189 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 130226541 ps |
| CPU time | 6.95 seconds |
| Started | Aug 25 07:51:11 AM UTC 24 |
| Finished | Aug 25 07:51:19 AM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950238189 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2950238189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2875764430 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 107144967 ps |
| CPU time | 4.49 seconds |
| Started | Aug 25 07:51:11 AM UTC 24 |
| Finished | Aug 25 07:51:16 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875764430 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_t l_intg_err.2875764430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.455201542 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 16036566 ps |
| CPU time | 1.74 seconds |
| Started | Aug 25 07:51:14 AM UTC 24 |
| Finished | Aug 25 07:51:17 AM UTC 24 |
| Peak memory | 233060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=455201542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.455201542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2444544856 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 24408660 ps |
| CPU time | 1.47 seconds |
| Started | Aug 25 07:51:14 AM UTC 24 |
| Finished | Aug 25 07:51:16 AM UTC 24 |
| Peak memory | 218608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444544856 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2444544856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3966974688 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 335155369 ps |
| CPU time | 2.8 seconds |
| Started | Aug 25 07:51:14 AM UTC 24 |
| Finished | Aug 25 07:51:18 AM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3966974688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3966974688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3502432305 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 591229625 ps |
| CPU time | 13.13 seconds |
| Started | Aug 25 07:51:12 AM UTC 24 |
| Finished | Aug 25 07:51:27 AM UTC 24 |
| Peak memory | 219584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3502432305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3502432305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2346206707 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 6915732140 ps |
| CPU time | 40.68 seconds |
| Started | Aug 25 07:51:12 AM UTC 24 |
| Finished | Aug 25 07:51:54 AM UTC 24 |
| Peak memory | 219964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2346206707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2346206707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2294913335 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 98984015 ps |
| CPU time | 4.44 seconds |
| Started | Aug 25 07:51:12 AM UTC 24 |
| Finished | Aug 25 07:51:18 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2294913335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2294913335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.662152832 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2232464136 ps |
| CPU time | 5.3 seconds |
| Started | Aug 25 07:51:14 AM UTC 24 |
| Finished | Aug 25 07:51:20 AM UTC 24 |
| Peak memory | 232244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662152832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_di sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.662152832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2545503765 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 300762346 ps |
| CPU time | 6.16 seconds |
| Started | Aug 25 07:51:12 AM UTC 24 |
| Finished | Aug 25 07:51:19 AM UTC 24 |
| Peak memory | 219696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2545503765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.lc_ctrl_jtag_csr_rw.2545503765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3655877557 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 48750392 ps |
| CPU time | 1.81 seconds |
| Started | Aug 25 07:51:12 AM UTC 24 |
| Finished | Aug 25 07:51:15 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3655877557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3655877557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.238201700 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 51895190 ps |
| CPU time | 1.67 seconds |
| Started | Aug 25 07:51:14 AM UTC 24 |
| Finished | Aug 25 07:51:17 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23820 1700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.l c_ctrl_same_csr_outstanding.238201700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.596112729 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 42419371 ps |
| CPU time | 4.19 seconds |
| Started | Aug 25 07:51:14 AM UTC 24 |
| Finished | Aug 25 07:51:19 AM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596112729 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.596112729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3335505333 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 24273569 ps |
| CPU time | 1.99 seconds |
| Started | Aug 25 07:51:18 AM UTC 24 |
| Finished | Aug 25 07:51:21 AM UTC 24 |
| Peak memory | 231012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3335505333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3335505333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.481356773 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 13771295 ps |
| CPU time | 1.27 seconds |
| Started | Aug 25 07:51:17 AM UTC 24 |
| Finished | Aug 25 07:51:19 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481356773 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.481356773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3273393358 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 131799717 ps |
| CPU time | 2.08 seconds |
| Started | Aug 25 07:51:17 AM UTC 24 |
| Finished | Aug 25 07:51:20 AM UTC 24 |
| Peak memory | 219660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3273393358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3273393358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3884273093 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 7250513363 ps |
| CPU time | 46.08 seconds |
| Started | Aug 25 07:51:15 AM UTC 24 |
| Finished | Aug 25 07:52:03 AM UTC 24 |
| Peak memory | 219480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3884273093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3884273093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2800723932 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 691769452 ps |
| CPU time | 11.98 seconds |
| Started | Aug 25 07:51:15 AM UTC 24 |
| Finished | Aug 25 07:51:28 AM UTC 24 |
| Peak memory | 219752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2800723932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2800723932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3315243893 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 588903774 ps |
| CPU time | 2.7 seconds |
| Started | Aug 25 07:51:14 AM UTC 24 |
| Finished | Aug 25 07:51:18 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3315243893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3315243893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.281602145 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 181579232 ps |
| CPU time | 2.43 seconds |
| Started | Aug 25 07:51:16 AM UTC 24 |
| Finished | Aug 25 07:51:20 AM UTC 24 |
| Peak memory | 232388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281602145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_di sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.281602145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3767029792 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 257818210 ps |
| CPU time | 3.15 seconds |
| Started | Aug 25 07:51:15 AM UTC 24 |
| Finished | Aug 25 07:51:19 AM UTC 24 |
| Peak memory | 219684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3767029792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.lc_ctrl_jtag_csr_rw.3767029792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3918860040 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 74209539 ps |
| CPU time | 1.73 seconds |
| Started | Aug 25 07:51:16 AM UTC 24 |
| Finished | Aug 25 07:51:19 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3918860040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3918860040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.486090254 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 86603365 ps |
| CPU time | 1.95 seconds |
| Started | Aug 25 07:51:17 AM UTC 24 |
| Finished | Aug 25 07:51:20 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48609 0254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.l c_ctrl_same_csr_outstanding.486090254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4182688282 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 73388868 ps |
| CPU time | 4.45 seconds |
| Started | Aug 25 07:51:17 AM UTC 24 |
| Finished | Aug 25 07:51:22 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182688282 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4182688282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1077911570 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 72111400 ps |
| CPU time | 1.99 seconds |
| Started | Aug 25 07:51:20 AM UTC 24 |
| Finished | Aug 25 07:51:23 AM UTC 24 |
| Peak memory | 231012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1077911570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1077911570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2775357896 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 28602396 ps |
| CPU time | 1.27 seconds |
| Started | Aug 25 07:51:20 AM UTC 24 |
| Finished | Aug 25 07:51:22 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775357896 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2775357896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3527429760 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 39986698 ps |
| CPU time | 1.39 seconds |
| Started | Aug 25 07:51:19 AM UTC 24 |
| Finished | Aug 25 07:51:21 AM UTC 24 |
| Peak memory | 219320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3527429760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3527429760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3288776519 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 859412834 ps |
| CPU time | 4.47 seconds |
| Started | Aug 25 07:51:18 AM UTC 24 |
| Finished | Aug 25 07:51:24 AM UTC 24 |
| Peak memory | 219408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3288776519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3288776519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3289043346 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 4135717100 ps |
| CPU time | 30.44 seconds |
| Started | Aug 25 07:51:18 AM UTC 24 |
| Finished | Aug 25 07:51:50 AM UTC 24 |
| Peak memory | 218968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3289043346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3289043346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2626353722 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2190854902 ps |
| CPU time | 7.64 seconds |
| Started | Aug 25 07:51:18 AM UTC 24 |
| Finished | Aug 25 07:51:27 AM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2626353722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2626353722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2274618272 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 95505012 ps |
| CPU time | 4.05 seconds |
| Started | Aug 25 07:51:18 AM UTC 24 |
| Finished | Aug 25 07:51:24 AM UTC 24 |
| Peak memory | 234244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274618272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2274618272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3150549480 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 223630148 ps |
| CPU time | 2.58 seconds |
| Started | Aug 25 07:51:18 AM UTC 24 |
| Finished | Aug 25 07:51:22 AM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3150549480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.lc_ctrl_jtag_csr_rw.3150549480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2226671993 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 122686043 ps |
| CPU time | 1.86 seconds |
| Started | Aug 25 07:51:18 AM UTC 24 |
| Finished | Aug 25 07:51:22 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2226671993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2226671993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1332630419 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 16600074 ps |
| CPU time | 1.55 seconds |
| Started | Aug 25 07:51:20 AM UTC 24 |
| Finished | Aug 25 07:51:23 AM UTC 24 |
| Peak memory | 219176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13326 30419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. lc_ctrl_same_csr_outstanding.1332630419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3360811704 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 97151728 ps |
| CPU time | 2.67 seconds |
| Started | Aug 25 07:51:19 AM UTC 24 |
| Finished | Aug 25 07:51:23 AM UTC 24 |
| Peak memory | 232444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360811704 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3360811704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1218121275 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 818295773 ps |
| CPU time | 5.62 seconds |
| Started | Aug 25 07:51:20 AM UTC 24 |
| Finished | Aug 25 07:51:26 AM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218121275 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_t l_intg_err.1218121275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.525116575 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 64945758 ps |
| CPU time | 2.27 seconds |
| Started | Aug 25 07:51:23 AM UTC 24 |
| Finished | Aug 25 07:51:26 AM UTC 24 |
| Peak memory | 236472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=525116575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.525116575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3694564901 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 38920098 ps |
| CPU time | 1.43 seconds |
| Started | Aug 25 07:51:23 AM UTC 24 |
| Finished | Aug 25 07:51:25 AM UTC 24 |
| Peak memory | 218608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694564901 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3694564901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3789059329 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 237798573 ps |
| CPU time | 2.98 seconds |
| Started | Aug 25 07:51:21 AM UTC 24 |
| Finished | Aug 25 07:51:26 AM UTC 24 |
| Peak memory | 219820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3789059329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3789059329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.993976058 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 848581105 ps |
| CPU time | 6.46 seconds |
| Started | Aug 25 07:51:21 AM UTC 24 |
| Finished | Aug 25 07:51:29 AM UTC 24 |
| Peak memory | 219488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=993976058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.993976058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2713931136 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 776718131 ps |
| CPU time | 9.21 seconds |
| Started | Aug 25 07:51:21 AM UTC 24 |
| Finished | Aug 25 07:51:32 AM UTC 24 |
| Peak memory | 219756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2713931136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2713931136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3932711604 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 119572004 ps |
| CPU time | 3.49 seconds |
| Started | Aug 25 07:51:20 AM UTC 24 |
| Finished | Aug 25 07:51:25 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3932711604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3932711604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.441501061 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 1242819264 ps |
| CPU time | 5.72 seconds |
| Started | Aug 25 07:51:21 AM UTC 24 |
| Finished | Aug 25 07:51:28 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441501061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_di sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.441501061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3019056157 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 990590605 ps |
| CPU time | 1.78 seconds |
| Started | Aug 25 07:51:20 AM UTC 24 |
| Finished | Aug 25 07:51:23 AM UTC 24 |
| Peak memory | 219028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3019056157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.lc_ctrl_jtag_csr_rw.3019056157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1126176928 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 67003876 ps |
| CPU time | 1.9 seconds |
| Started | Aug 25 07:51:21 AM UTC 24 |
| Finished | Aug 25 07:51:24 AM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1126176928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1126176928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.279832646 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 19473946 ps |
| CPU time | 1.56 seconds |
| Started | Aug 25 07:51:23 AM UTC 24 |
| Finished | Aug 25 07:51:26 AM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27983 2646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.l c_ctrl_same_csr_outstanding.279832646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2010332900 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 43968012 ps |
| CPU time | 4.73 seconds |
| Started | Aug 25 07:51:22 AM UTC 24 |
| Finished | Aug 25 07:51:28 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010332900 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2010332900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2983262248 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 163070778 ps |
| CPU time | 3.29 seconds |
| Started | Aug 25 07:51:22 AM UTC 24 |
| Finished | Aug 25 07:51:26 AM UTC 24 |
| Peak memory | 236152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983262248 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_t l_intg_err.2983262248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.908093630 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 641458202 ps |
| CPU time | 21.34 seconds |
| Started | Aug 25 07:39:37 AM UTC 24 |
| Finished | Aug 25 07:40:00 AM UTC 24 |
| Peak memory | 229980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908093630 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.908093630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2320594743 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 6508661700 ps |
| CPU time | 65.96 seconds |
| Started | Aug 25 07:39:37 AM UTC 24 |
| Finished | Aug 25 07:40:45 AM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320594743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_errors.2320594743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3645830130 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1022799691 ps |
| CPU time | 8.08 seconds |
| Started | Aug 25 07:39:38 AM UTC 24 |
| Finished | Aug 25 07:39:47 AM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645830130 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_pri ority.3645830130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.696143294 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 942407836 ps |
| CPU time | 20.37 seconds |
| Started | Aug 25 07:39:36 AM UTC 24 |
| Finished | Aug 25 07:39:59 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696143294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr l_jtag_prog_failure.696143294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.2115709458 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3032062891 ps |
| CPU time | 29.04 seconds |
| Started | Aug 25 07:39:36 AM UTC 24 |
| Finished | Aug 25 07:40:07 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115709458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _smoke.2115709458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3646676012 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4905162760 ps |
| CPU time | 91.14 seconds |
| Started | Aug 25 07:39:36 AM UTC 24 |
| Finished | Aug 25 07:41:10 AM UTC 24 |
| Peak memory | 281256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646676012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_c trl_jtag_state_failure.3646676012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1169043795 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 137011150 ps |
| CPU time | 4.8 seconds |
| Started | Aug 25 07:39:35 AM UTC 24 |
| Finished | Aug 25 07:39:41 AM UTC 24 |
| Peak memory | 232460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169043795 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1169043795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.951578613 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 468281401 ps |
| CPU time | 34.12 seconds |
| Started | Aug 25 07:39:35 AM UTC 24 |
| Finished | Aug 25 07:40:11 AM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951578613 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.951578613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2046012668 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 212259520 ps |
| CPU time | 74.14 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:40:56 AM UTC 24 |
| Peak memory | 290484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046012668 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2046012668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2305476871 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 526451305 ps |
| CPU time | 14.75 seconds |
| Started | Aug 25 07:39:38 AM UTC 24 |
| Finished | Aug 25 07:39:54 AM UTC 24 |
| Peak memory | 237992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305476871 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_t oken_digest.2305476871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3245108180 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1068956957 ps |
| CPU time | 13.08 seconds |
| Started | Aug 25 07:39:38 AM UTC 24 |
| Finished | Aug 25 07:39:52 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245108180 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_toke n_mux.3245108180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.649974617 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 76526572 ps |
| CPU time | 2.82 seconds |
| Started | Aug 25 07:39:34 AM UTC 24 |
| Finished | Aug 25 07:39:38 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649974617 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.649974617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1829563732 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 156466863 ps |
| CPU time | 42.25 seconds |
| Started | Aug 25 07:39:35 AM UTC 24 |
| Finished | Aug 25 07:40:19 AM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829563732 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1829563732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.492936726 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 270675806 ps |
| CPU time | 14.19 seconds |
| Started | Aug 25 07:39:35 AM UTC 24 |
| Finished | Aug 25 07:39:51 AM UTC 24 |
| Peak memory | 263104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492936726 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.492936726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.2122872902 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 19106508 ps |
| CPU time | 1.48 seconds |
| Started | Aug 25 07:39:59 AM UTC 24 |
| Finished | Aug 25 07:40:02 AM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122872902 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2122872902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.1318430392 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 50803746 ps |
| CPU time | 1.3 seconds |
| Started | Aug 25 07:39:42 AM UTC 24 |
| Finished | Aug 25 07:39:44 AM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318430392 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1318430392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.3707568344 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1401983579 ps |
| CPU time | 26.02 seconds |
| Started | Aug 25 07:39:40 AM UTC 24 |
| Finished | Aug 25 07:40:08 AM UTC 24 |
| Peak memory | 238344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707568344 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3707568344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.777659789 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 8907313840 ps |
| CPU time | 84.36 seconds |
| Started | Aug 25 07:39:45 AM UTC 24 |
| Finished | Aug 25 07:41:12 AM UTC 24 |
| Peak memory | 232552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777659789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j tag_errors.777659789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.853442144 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 5258414551 ps |
| CPU time | 47.5 seconds |
| Started | Aug 25 07:39:46 AM UTC 24 |
| Finished | Aug 25 07:40:35 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853442144 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_prio rity.853442144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.1929400365 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2852090847 ps |
| CPU time | 16.11 seconds |
| Started | Aug 25 07:39:44 AM UTC 24 |
| Finished | Aug 25 07:40:01 AM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929400365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_jtag_prog_failure.1929400365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3392746545 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3542075261 ps |
| CPU time | 38.07 seconds |
| Started | Aug 25 07:39:47 AM UTC 24 |
| Finished | Aug 25 07:40:27 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392746545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.l c_ctrl_jtag_regwen_during_op.3392746545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.2799565564 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 565835840 ps |
| CPU time | 2.07 seconds |
| Started | Aug 25 07:39:43 AM UTC 24 |
| Finished | Aug 25 07:39:46 AM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799565564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag _smoke.2799565564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.541812103 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 598786057 ps |
| CPU time | 24.54 seconds |
| Started | Aug 25 07:39:43 AM UTC 24 |
| Finished | Aug 25 07:40:09 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541812103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc _ctrl_jtag_state_post_trans.541812103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1416588346 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1044216243 ps |
| CPU time | 29.79 seconds |
| Started | Aug 25 07:39:42 AM UTC 24 |
| Finished | Aug 25 07:40:13 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416588346 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1416588346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2920163084 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 990913629 ps |
| CPU time | 16.15 seconds |
| Started | Aug 25 07:39:58 AM UTC 24 |
| Finished | Aug 25 07:40:16 AM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920163084 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_t oken_digest.2920163084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.150102194 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 674160034 ps |
| CPU time | 15.9 seconds |
| Started | Aug 25 07:39:51 AM UTC 24 |
| Finished | Aug 25 07:40:09 AM UTC 24 |
| Peak memory | 237876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150102194 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token _mux.150102194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1543244969 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 289759977 ps |
| CPU time | 13.51 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:39:54 AM UTC 24 |
| Peak memory | 263032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543244969 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1543244969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.4022716168 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5187774767 ps |
| CPU time | 272.22 seconds |
| Started | Aug 25 07:39:59 AM UTC 24 |
| Finished | Aug 25 07:44:36 AM UTC 24 |
| Peak memory | 287400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4022716168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.lc_ctrl_stress_all.4022716168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1932633880 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14948268 ps |
| CPU time | 1.53 seconds |
| Started | Aug 25 07:39:39 AM UTC 24 |
| Finished | Aug 25 07:39:42 AM UTC 24 |
| Peak memory | 222892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932633880 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_volatile_unlock_smoke.1932633880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.1176926453 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 77092390 ps |
| CPU time | 1.41 seconds |
| Started | Aug 25 07:42:58 AM UTC 24 |
| Finished | Aug 25 07:43:00 AM UTC 24 |
| Peak memory | 219112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176926453 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1176926453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.905679049 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 388774140 ps |
| CPU time | 18.7 seconds |
| Started | Aug 25 07:42:48 AM UTC 24 |
| Finished | Aug 25 07:43:08 AM UTC 24 |
| Peak memory | 230420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905679049 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.905679049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1551424104 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1002370990 ps |
| CPU time | 9.55 seconds |
| Started | Aug 25 07:42:53 AM UTC 24 |
| Finished | Aug 25 07:43:04 AM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551424104 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_acce ss.1551424104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.4077434659 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 21449499640 ps |
| CPU time | 70.08 seconds |
| Started | Aug 25 07:42:52 AM UTC 24 |
| Finished | Aug 25 07:44:04 AM UTC 24 |
| Peak memory | 232460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077434659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl _jtag_errors.4077434659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.4048460738 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 962719820 ps |
| CPU time | 12.41 seconds |
| Started | Aug 25 07:42:52 AM UTC 24 |
| Finished | Aug 25 07:43:06 AM UTC 24 |
| Peak memory | 236552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048460738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_jtag_prog_failure.4048460738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1726299448 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 135300388 ps |
| CPU time | 6.52 seconds |
| Started | Aug 25 07:42:49 AM UTC 24 |
| Finished | Aug 25 07:42:56 AM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726299448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_smoke.1726299448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.2804605164 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1311540476 ps |
| CPU time | 102.25 seconds |
| Started | Aug 25 07:42:50 AM UTC 24 |
| Finished | Aug 25 07:44:34 AM UTC 24 |
| Peak memory | 283244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804605164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ ctrl_jtag_state_failure.2804605164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.2005492155 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2649482491 ps |
| CPU time | 22.87 seconds |
| Started | Aug 25 07:42:51 AM UTC 24 |
| Finished | Aug 25 07:43:15 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005492155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10. lc_ctrl_jtag_state_post_trans.2005492155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1461853042 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 425170420 ps |
| CPU time | 5.16 seconds |
| Started | Aug 25 07:42:48 AM UTC 24 |
| Finished | Aug 25 07:42:54 AM UTC 24 |
| Peak memory | 236572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461853042 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1461853042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.766206679 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3859803686 ps |
| CPU time | 25.56 seconds |
| Started | Aug 25 07:42:53 AM UTC 24 |
| Finished | Aug 25 07:43:20 AM UTC 24 |
| Peak memory | 237900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766206679 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.766206679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3027837542 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1721976425 ps |
| CPU time | 12.89 seconds |
| Started | Aug 25 07:42:54 AM UTC 24 |
| Finished | Aug 25 07:43:09 AM UTC 24 |
| Peak memory | 237832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027837542 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_ token_digest.3027837542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3224391586 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2030676955 ps |
| CPU time | 26.39 seconds |
| Started | Aug 25 07:42:54 AM UTC 24 |
| Finished | Aug 25 07:43:22 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224391586 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_tok en_mux.3224391586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.686299276 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 328906343 ps |
| CPU time | 16.5 seconds |
| Started | Aug 25 07:42:48 AM UTC 24 |
| Finished | Aug 25 07:43:06 AM UTC 24 |
| Peak memory | 237988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686299276 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.686299276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2197442558 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 243535676 ps |
| CPU time | 4.02 seconds |
| Started | Aug 25 07:42:43 AM UTC 24 |
| Finished | Aug 25 07:42:48 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197442558 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2197442558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.1878653777 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1406255997 ps |
| CPU time | 40.81 seconds |
| Started | Aug 25 07:42:44 AM UTC 24 |
| Finished | Aug 25 07:43:27 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878653777 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1878653777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1298172787 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 89326248 ps |
| CPU time | 10.54 seconds |
| Started | Aug 25 07:42:45 AM UTC 24 |
| Finished | Aug 25 07:42:57 AM UTC 24 |
| Peak memory | 262672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298172787 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1298172787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1709631732 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 53699231182 ps |
| CPU time | 289.25 seconds |
| Started | Aug 25 07:42:56 AM UTC 24 |
| Finished | Aug 25 07:47:49 AM UTC 24 |
| Peak memory | 287476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1709631732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 10.lc_ctrl_stress_all.1709631732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2052046224 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 28221431 ps |
| CPU time | 1.59 seconds |
| Started | Aug 25 07:42:44 AM UTC 24 |
| Finished | Aug 25 07:42:47 AM UTC 24 |
| Peak memory | 222888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052046224 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_volatile_unlock_smoke.2052046224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.1036796892 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 65385820 ps |
| CPU time | 1.73 seconds |
| Started | Aug 25 07:43:18 AM UTC 24 |
| Finished | Aug 25 07:43:21 AM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036796892 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1036796892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.2827156379 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 215068518 ps |
| CPU time | 14.66 seconds |
| Started | Aug 25 07:43:05 AM UTC 24 |
| Finished | Aug 25 07:43:20 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827156379 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2827156379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3348786074 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2463406104 ps |
| CPU time | 22.45 seconds |
| Started | Aug 25 07:43:13 AM UTC 24 |
| Finished | Aug 25 07:43:37 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348786074 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_acce ss.3348786074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.435471914 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1431080952 ps |
| CPU time | 63.94 seconds |
| Started | Aug 25 07:43:11 AM UTC 24 |
| Finished | Aug 25 07:44:17 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435471914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_ jtag_errors.435471914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.1834431374 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 370287701 ps |
| CPU time | 6.95 seconds |
| Started | Aug 25 07:43:09 AM UTC 24 |
| Finished | Aug 25 07:43:17 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834431374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c trl_jtag_prog_failure.1834431374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.4021645454 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2265643258 ps |
| CPU time | 6.22 seconds |
| Started | Aug 25 07:43:07 AM UTC 24 |
| Finished | Aug 25 07:43:14 AM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021645454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta g_smoke.4021645454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.791151581 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1074020269 ps |
| CPU time | 72.99 seconds |
| Started | Aug 25 07:43:07 AM UTC 24 |
| Finished | Aug 25 07:44:22 AM UTC 24 |
| Peak memory | 262956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791151581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c trl_jtag_state_failure.791151581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.1549180770 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 670322989 ps |
| CPU time | 30.8 seconds |
| Started | Aug 25 07:43:09 AM UTC 24 |
| Finished | Aug 25 07:43:42 AM UTC 24 |
| Peak memory | 260712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549180770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11. lc_ctrl_jtag_state_post_trans.1549180770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.107527389 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 262233063 ps |
| CPU time | 4.79 seconds |
| Started | Aug 25 07:43:05 AM UTC 24 |
| Finished | Aug 25 07:43:10 AM UTC 24 |
| Peak memory | 236308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107527389 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.107527389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.1849550647 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 191685487 ps |
| CPU time | 11.34 seconds |
| Started | Aug 25 07:43:13 AM UTC 24 |
| Finished | Aug 25 07:43:26 AM UTC 24 |
| Peak memory | 232480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849550647 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1849550647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3310780365 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1261826766 ps |
| CPU time | 15.3 seconds |
| Started | Aug 25 07:43:16 AM UTC 24 |
| Finished | Aug 25 07:43:32 AM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310780365 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_ token_digest.3310780365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2171995660 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 484866673 ps |
| CPU time | 14.41 seconds |
| Started | Aug 25 07:43:15 AM UTC 24 |
| Finished | Aug 25 07:43:30 AM UTC 24 |
| Peak memory | 232532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171995660 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_tok en_mux.2171995660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1935772282 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 245578514 ps |
| CPU time | 6.19 seconds |
| Started | Aug 25 07:42:58 AM UTC 24 |
| Finished | Aug 25 07:43:05 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935772282 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1935772282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1088187895 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 518327598 ps |
| CPU time | 49.63 seconds |
| Started | Aug 25 07:43:01 AM UTC 24 |
| Finished | Aug 25 07:43:53 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088187895 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1088187895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2802443420 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 240157654 ps |
| CPU time | 14.73 seconds |
| Started | Aug 25 07:43:02 AM UTC 24 |
| Finished | Aug 25 07:43:18 AM UTC 24 |
| Peak memory | 260648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802443420 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2802443420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.3486698218 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3145666776 ps |
| CPU time | 113.67 seconds |
| Started | Aug 25 07:43:16 AM UTC 24 |
| Finished | Aug 25 07:45:12 AM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3486698218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 11.lc_ctrl_stress_all.3486698218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2727860507 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 14359603 ps |
| CPU time | 1.46 seconds |
| Started | Aug 25 07:42:59 AM UTC 24 |
| Finished | Aug 25 07:43:02 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727860507 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_volatile_unlock_smoke.2727860507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.598159378 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 13529263 ps |
| CPU time | 1.39 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:43:46 AM UTC 24 |
| Peak memory | 217708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598159378 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.598159378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.404544227 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 212993399 ps |
| CPU time | 15.3 seconds |
| Started | Aug 25 07:43:22 AM UTC 24 |
| Finished | Aug 25 07:43:39 AM UTC 24 |
| Peak memory | 237876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404544227 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.404544227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1887181465 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 756112441 ps |
| CPU time | 6.24 seconds |
| Started | Aug 25 07:43:27 AM UTC 24 |
| Finished | Aug 25 07:43:35 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887181465 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_acce ss.1887181465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.3815839120 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 26842351880 ps |
| CPU time | 51.45 seconds |
| Started | Aug 25 07:43:27 AM UTC 24 |
| Finished | Aug 25 07:44:20 AM UTC 24 |
| Peak memory | 232524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815839120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_errors.3815839120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.3074242984 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 192730085 ps |
| CPU time | 4.84 seconds |
| Started | Aug 25 07:43:25 AM UTC 24 |
| Finished | Aug 25 07:43:31 AM UTC 24 |
| Peak memory | 232544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074242984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_jtag_prog_failure.3074242984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.4096637304 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 116778208 ps |
| CPU time | 5.93 seconds |
| Started | Aug 25 07:43:24 AM UTC 24 |
| Finished | Aug 25 07:43:31 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096637304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_smoke.4096637304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.2857821858 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1352761347 ps |
| CPU time | 97.17 seconds |
| Started | Aug 25 07:43:24 AM UTC 24 |
| Finished | Aug 25 07:45:03 AM UTC 24 |
| Peak memory | 285288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857821858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ ctrl_jtag_state_failure.2857821858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.2904355204 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 12333203805 ps |
| CPU time | 25.7 seconds |
| Started | Aug 25 07:43:24 AM UTC 24 |
| Finished | Aug 25 07:43:51 AM UTC 24 |
| Peak memory | 236628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904355204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12. lc_ctrl_jtag_state_post_trans.2904355204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.556172922 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 301588237 ps |
| CPU time | 6.18 seconds |
| Started | Aug 25 07:43:21 AM UTC 24 |
| Finished | Aug 25 07:43:29 AM UTC 24 |
| Peak memory | 232532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556172922 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.556172922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.971821930 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 338684345 ps |
| CPU time | 17.63 seconds |
| Started | Aug 25 07:43:27 AM UTC 24 |
| Finished | Aug 25 07:43:46 AM UTC 24 |
| Peak memory | 237920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971821930 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.971821930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.4169767926 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 213368367 ps |
| CPU time | 14.53 seconds |
| Started | Aug 25 07:43:42 AM UTC 24 |
| Finished | Aug 25 07:43:57 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169767926 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_ token_digest.4169767926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.4286684970 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 216175608 ps |
| CPU time | 11.49 seconds |
| Started | Aug 25 07:43:28 AM UTC 24 |
| Finished | Aug 25 07:43:41 AM UTC 24 |
| Peak memory | 230168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286684970 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_tok en_mux.4286684970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.2848680520 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3069972717 ps |
| CPU time | 13.03 seconds |
| Started | Aug 25 07:43:22 AM UTC 24 |
| Finished | Aug 25 07:43:37 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848680520 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2848680520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1357484816 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 37910511 ps |
| CPU time | 3.77 seconds |
| Started | Aug 25 07:43:20 AM UTC 24 |
| Finished | Aug 25 07:43:24 AM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357484816 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1357484816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.621678271 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 955789361 ps |
| CPU time | 60.83 seconds |
| Started | Aug 25 07:43:21 AM UTC 24 |
| Finished | Aug 25 07:44:24 AM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621678271 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.621678271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1019511909 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 77708192 ps |
| CPU time | 4.2 seconds |
| Started | Aug 25 07:43:21 AM UTC 24 |
| Finished | Aug 25 07:43:26 AM UTC 24 |
| Peak memory | 234600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019511909 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1019511909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.3406647774 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 14099589139 ps |
| CPU time | 384.24 seconds |
| Started | Aug 25 07:43:42 AM UTC 24 |
| Finished | Aug 25 07:50:12 AM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3406647774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 12.lc_ctrl_stress_all.3406647774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2122059000 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 21773522 ps |
| CPU time | 1.3 seconds |
| Started | Aug 25 07:43:20 AM UTC 24 |
| Finished | Aug 25 07:43:22 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122059000 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_volatile_unlock_smoke.2122059000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2847106116 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 54093499 ps |
| CPU time | 1.21 seconds |
| Started | Aug 25 07:43:50 AM UTC 24 |
| Finished | Aug 25 07:43:52 AM UTC 24 |
| Peak memory | 219092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847106116 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2847106116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1735342263 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1321232583 ps |
| CPU time | 23.02 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:44:09 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735342263 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1735342263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.902276457 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1857055526 ps |
| CPU time | 7.66 seconds |
| Started | Aug 25 07:43:46 AM UTC 24 |
| Finished | Aug 25 07:43:55 AM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902276457 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.902276457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.1016711028 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 32483874024 ps |
| CPU time | 65.83 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:44:52 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016711028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _jtag_errors.1016711028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.2487258168 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 239682257 ps |
| CPU time | 4.22 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:43:50 AM UTC 24 |
| Peak memory | 234176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487258168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c trl_jtag_prog_failure.2487258168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.676475283 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 561628561 ps |
| CPU time | 4.39 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:43:50 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676475283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag _smoke.676475283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.1030689803 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 23690759771 ps |
| CPU time | 87.82 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:45:14 AM UTC 24 |
| Peak memory | 283300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030689803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ ctrl_jtag_state_failure.1030689803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.2578190010 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 314047063 ps |
| CPU time | 17.86 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:44:04 AM UTC 24 |
| Peak memory | 262624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578190010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13. lc_ctrl_jtag_state_post_trans.2578190010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.3875947523 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 204497169 ps |
| CPU time | 2.63 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:43:48 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875947523 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3875947523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.3080017335 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 290756227 ps |
| CPU time | 20.56 seconds |
| Started | Aug 25 07:43:47 AM UTC 24 |
| Finished | Aug 25 07:44:09 AM UTC 24 |
| Peak memory | 238192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080017335 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3080017335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3370424184 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 586433441 ps |
| CPU time | 18.08 seconds |
| Started | Aug 25 07:43:47 AM UTC 24 |
| Finished | Aug 25 07:44:07 AM UTC 24 |
| Peak memory | 237836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370424184 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_ token_digest.3370424184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3529019311 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 511462700 ps |
| CPU time | 20.14 seconds |
| Started | Aug 25 07:43:47 AM UTC 24 |
| Finished | Aug 25 07:44:09 AM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529019311 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_tok en_mux.3529019311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2072566370 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 492489010 ps |
| CPU time | 19.42 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:44:05 AM UTC 24 |
| Peak memory | 237348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072566370 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2072566370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.2625383736 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 140533716 ps |
| CPU time | 3.18 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:43:48 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625383736 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2625383736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.2389356294 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 192388954 ps |
| CPU time | 38.15 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:44:24 AM UTC 24 |
| Peak memory | 262840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389356294 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2389356294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2402443571 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 128816602 ps |
| CPU time | 4.19 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:43:49 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402443571 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2402443571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1223553011 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 9336502837 ps |
| CPU time | 146.44 seconds |
| Started | Aug 25 07:43:49 AM UTC 24 |
| Finished | Aug 25 07:46:19 AM UTC 24 |
| Peak memory | 279364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223553011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1223553011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.929491768 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 24756646 ps |
| CPU time | 1.3 seconds |
| Started | Aug 25 07:43:44 AM UTC 24 |
| Finished | Aug 25 07:43:46 AM UTC 24 |
| Peak memory | 229100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929491768 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.lc_ctrl_volatile_unlock_smoke.929491768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.4051461815 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 16066215 ps |
| CPU time | 1.39 seconds |
| Started | Aug 25 07:44:08 AM UTC 24 |
| Finished | Aug 25 07:44:10 AM UTC 24 |
| Peak memory | 219032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051461815 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4051461815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.3053564689 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 739101817 ps |
| CPU time | 17.96 seconds |
| Started | Aug 25 07:43:55 AM UTC 24 |
| Finished | Aug 25 07:44:14 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053564689 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3053564689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.2196605483 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 632806486 ps |
| CPU time | 20.42 seconds |
| Started | Aug 25 07:44:06 AM UTC 24 |
| Finished | Aug 25 07:44:28 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196605483 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_acce ss.2196605483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.405868236 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1475507821 ps |
| CPU time | 40.42 seconds |
| Started | Aug 25 07:44:06 AM UTC 24 |
| Finished | Aug 25 07:44:48 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405868236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_ jtag_errors.405868236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1131049655 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 441619300 ps |
| CPU time | 20.16 seconds |
| Started | Aug 25 07:44:06 AM UTC 24 |
| Finished | Aug 25 07:44:28 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131049655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_jtag_prog_failure.1131049655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3777358590 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 611261846 ps |
| CPU time | 17.41 seconds |
| Started | Aug 25 07:43:56 AM UTC 24 |
| Finished | Aug 25 07:44:15 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777358590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_smoke.3777358590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.1594004729 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4111330728 ps |
| CPU time | 142.35 seconds |
| Started | Aug 25 07:43:56 AM UTC 24 |
| Finished | Aug 25 07:46:21 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594004729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ ctrl_jtag_state_failure.1594004729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3654110568 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 483364452 ps |
| CPU time | 33.63 seconds |
| Started | Aug 25 07:44:04 AM UTC 24 |
| Finished | Aug 25 07:44:40 AM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654110568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14. lc_ctrl_jtag_state_post_trans.3654110568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.4265933914 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 193835328 ps |
| CPU time | 2.88 seconds |
| Started | Aug 25 07:43:54 AM UTC 24 |
| Finished | Aug 25 07:43:58 AM UTC 24 |
| Peak memory | 232300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265933914 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4265933914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.714591181 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1579066900 ps |
| CPU time | 27.67 seconds |
| Started | Aug 25 07:44:06 AM UTC 24 |
| Finished | Aug 25 07:44:36 AM UTC 24 |
| Peak memory | 238168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714591181 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.714591181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.1501827141 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1532184612 ps |
| CPU time | 13.99 seconds |
| Started | Aug 25 07:44:06 AM UTC 24 |
| Finished | Aug 25 07:44:22 AM UTC 24 |
| Peak memory | 237832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501827141 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_ token_digest.1501827141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.2265374058 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1586283256 ps |
| CPU time | 18.48 seconds |
| Started | Aug 25 07:44:06 AM UTC 24 |
| Finished | Aug 25 07:44:26 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265374058 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_tok en_mux.2265374058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.2097360876 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 506121765 ps |
| CPU time | 9.52 seconds |
| Started | Aug 25 07:43:56 AM UTC 24 |
| Finished | Aug 25 07:44:06 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097360876 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2097360876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.1293040440 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 32443865 ps |
| CPU time | 1.99 seconds |
| Started | Aug 25 07:43:51 AM UTC 24 |
| Finished | Aug 25 07:43:54 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293040440 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1293040440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.1012996124 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1682520815 ps |
| CPU time | 48.13 seconds |
| Started | Aug 25 07:43:52 AM UTC 24 |
| Finished | Aug 25 07:44:42 AM UTC 24 |
| Peak memory | 263096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012996124 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1012996124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.3419238562 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 308384136 ps |
| CPU time | 12.04 seconds |
| Started | Aug 25 07:43:53 AM UTC 24 |
| Finished | Aug 25 07:44:07 AM UTC 24 |
| Peak memory | 260720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419238562 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3419238562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.4231800631 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2449301986 ps |
| CPU time | 95.92 seconds |
| Started | Aug 25 07:44:08 AM UTC 24 |
| Finished | Aug 25 07:45:46 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4231800631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 14.lc_ctrl_stress_all.4231800631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3399690703 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 12173102 ps |
| CPU time | 1.26 seconds |
| Started | Aug 25 07:43:51 AM UTC 24 |
| Finished | Aug 25 07:43:54 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399690703 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_volatile_unlock_smoke.3399690703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2631593679 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 44014405 ps |
| CPU time | 1.55 seconds |
| Started | Aug 25 07:44:25 AM UTC 24 |
| Finished | Aug 25 07:44:28 AM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631593679 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2631593679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.3257346929 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 403390579 ps |
| CPU time | 20.03 seconds |
| Started | Aug 25 07:44:15 AM UTC 24 |
| Finished | Aug 25 07:44:36 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257346929 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3257346929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.489459369 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 681615555 ps |
| CPU time | 3.99 seconds |
| Started | Aug 25 07:44:23 AM UTC 24 |
| Finished | Aug 25 07:44:28 AM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489459369 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.489459369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.3640794467 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 6679827923 ps |
| CPU time | 78.48 seconds |
| Started | Aug 25 07:44:21 AM UTC 24 |
| Finished | Aug 25 07:45:42 AM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640794467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_errors.3640794467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1440337270 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2448507946 ps |
| CPU time | 8.51 seconds |
| Started | Aug 25 07:44:19 AM UTC 24 |
| Finished | Aug 25 07:44:29 AM UTC 24 |
| Peak memory | 230168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440337270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_jtag_prog_failure.1440337270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3715577623 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 851634889 ps |
| CPU time | 5.42 seconds |
| Started | Aug 25 07:44:16 AM UTC 24 |
| Finished | Aug 25 07:44:22 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715577623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_smoke.3715577623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.48178752 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2730659129 ps |
| CPU time | 91.35 seconds |
| Started | Aug 25 07:44:17 AM UTC 24 |
| Finished | Aug 25 07:45:51 AM UTC 24 |
| Peak memory | 283368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48178752 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct rl_jtag_state_failure.48178752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.3659127203 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1481803915 ps |
| CPU time | 15.59 seconds |
| Started | Aug 25 07:44:18 AM UTC 24 |
| Finished | Aug 25 07:44:35 AM UTC 24 |
| Peak memory | 236900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659127203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15. lc_ctrl_jtag_state_post_trans.3659127203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.3367103782 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 215963629 ps |
| CPU time | 4.25 seconds |
| Started | Aug 25 07:44:13 AM UTC 24 |
| Finished | Aug 25 07:44:19 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367103782 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3367103782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.2973792471 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3381125090 ps |
| CPU time | 19.78 seconds |
| Started | Aug 25 07:44:23 AM UTC 24 |
| Finished | Aug 25 07:44:44 AM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973792471 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2973792471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3176569669 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2390114421 ps |
| CPU time | 25.77 seconds |
| Started | Aug 25 07:44:24 AM UTC 24 |
| Finished | Aug 25 07:44:51 AM UTC 24 |
| Peak memory | 238328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176569669 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_ token_digest.3176569669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.874073877 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 326600314 ps |
| CPU time | 16.04 seconds |
| Started | Aug 25 07:44:23 AM UTC 24 |
| Finished | Aug 25 07:44:40 AM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874073877 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_toke n_mux.874073877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.4213916707 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 349053365 ps |
| CPU time | 9.63 seconds |
| Started | Aug 25 07:44:15 AM UTC 24 |
| Finished | Aug 25 07:44:26 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213916707 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4213916707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.4201610246 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 36632547 ps |
| CPU time | 4.7 seconds |
| Started | Aug 25 07:44:10 AM UTC 24 |
| Finished | Aug 25 07:44:16 AM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201610246 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.4201610246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2052464519 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 656989892 ps |
| CPU time | 66.45 seconds |
| Started | Aug 25 07:44:10 AM UTC 24 |
| Finished | Aug 25 07:45:18 AM UTC 24 |
| Peak memory | 262768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052464519 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2052464519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.101738737 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 80921460 ps |
| CPU time | 10.51 seconds |
| Started | Aug 25 07:44:11 AM UTC 24 |
| Finished | Aug 25 07:44:23 AM UTC 24 |
| Peak memory | 260620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101738737 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.101738737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.2609742888 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 5585287366 ps |
| CPU time | 265.15 seconds |
| Started | Aug 25 07:44:24 AM UTC 24 |
| Finished | Aug 25 07:48:54 AM UTC 24 |
| Peak memory | 289448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2609742888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 15.lc_ctrl_stress_all.2609742888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1939699347 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 14746509 ps |
| CPU time | 1.23 seconds |
| Started | Aug 25 07:44:10 AM UTC 24 |
| Finished | Aug 25 07:44:13 AM UTC 24 |
| Peak memory | 220660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939699347 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_volatile_unlock_smoke.1939699347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.2679173101 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 83763662 ps |
| CPU time | 1.35 seconds |
| Started | Aug 25 07:44:41 AM UTC 24 |
| Finished | Aug 25 07:44:43 AM UTC 24 |
| Peak memory | 219092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679173101 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2679173101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1360032884 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 799219710 ps |
| CPU time | 20.33 seconds |
| Started | Aug 25 07:44:30 AM UTC 24 |
| Finished | Aug 25 07:44:51 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360032884 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1360032884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.1235141065 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 519433992 ps |
| CPU time | 13.73 seconds |
| Started | Aug 25 07:44:35 AM UTC 24 |
| Finished | Aug 25 07:44:50 AM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235141065 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_acce ss.1235141065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.4017615082 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1815972086 ps |
| CPU time | 70.75 seconds |
| Started | Aug 25 07:44:35 AM UTC 24 |
| Finished | Aug 25 07:45:48 AM UTC 24 |
| Peak memory | 237808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017615082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_errors.4017615082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.335295852 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 693455857 ps |
| CPU time | 5.29 seconds |
| Started | Aug 25 07:44:34 AM UTC 24 |
| Finished | Aug 25 07:44:41 AM UTC 24 |
| Peak memory | 234256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335295852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct rl_jtag_prog_failure.335295852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3769070362 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 816998891 ps |
| CPU time | 8.04 seconds |
| Started | Aug 25 07:44:31 AM UTC 24 |
| Finished | Aug 25 07:44:40 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769070362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_smoke.3769070362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1163450771 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1292571712 ps |
| CPU time | 83.51 seconds |
| Started | Aug 25 07:44:33 AM UTC 24 |
| Finished | Aug 25 07:45:59 AM UTC 24 |
| Peak memory | 263156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163450771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ ctrl_jtag_state_failure.1163450771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.1165063797 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 11028311239 ps |
| CPU time | 25.83 seconds |
| Started | Aug 25 07:44:34 AM UTC 24 |
| Finished | Aug 25 07:45:01 AM UTC 24 |
| Peak memory | 260688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165063797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16. lc_ctrl_jtag_state_post_trans.1165063797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.3742349696 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 48840813 ps |
| CPU time | 3.97 seconds |
| Started | Aug 25 07:44:29 AM UTC 24 |
| Finished | Aug 25 07:44:34 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742349696 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3742349696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.3972089172 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 656821940 ps |
| CPU time | 15.97 seconds |
| Started | Aug 25 07:44:37 AM UTC 24 |
| Finished | Aug 25 07:44:55 AM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972089172 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3972089172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.1603021080 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 227536957 ps |
| CPU time | 14.25 seconds |
| Started | Aug 25 07:44:37 AM UTC 24 |
| Finished | Aug 25 07:44:53 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603021080 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_ token_digest.1603021080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3749717777 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1096670980 ps |
| CPU time | 10.07 seconds |
| Started | Aug 25 07:44:37 AM UTC 24 |
| Finished | Aug 25 07:44:49 AM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749717777 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_tok en_mux.3749717777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.2196697424 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 319437982 ps |
| CPU time | 13.29 seconds |
| Started | Aug 25 07:44:30 AM UTC 24 |
| Finished | Aug 25 07:44:44 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196697424 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2196697424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.222369607 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 666555871 ps |
| CPU time | 6.25 seconds |
| Started | Aug 25 07:44:26 AM UTC 24 |
| Finished | Aug 25 07:44:34 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222369607 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.222369607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3797748079 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 148081888 ps |
| CPU time | 34.16 seconds |
| Started | Aug 25 07:44:29 AM UTC 24 |
| Finished | Aug 25 07:45:04 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797748079 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3797748079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.2818476584 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 68046357 ps |
| CPU time | 8.43 seconds |
| Started | Aug 25 07:44:29 AM UTC 24 |
| Finished | Aug 25 07:44:38 AM UTC 24 |
| Peak memory | 263100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818476584 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2818476584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3470059257 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 16565195645 ps |
| CPU time | 192.32 seconds |
| Started | Aug 25 07:44:40 AM UTC 24 |
| Finished | Aug 25 07:47:55 AM UTC 24 |
| Peak memory | 236300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3470059257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 16.lc_ctrl_stress_all.3470059257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2265920805 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 22041742 ps |
| CPU time | 1.2 seconds |
| Started | Aug 25 07:44:28 AM UTC 24 |
| Finished | Aug 25 07:44:30 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265920805 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_volatile_unlock_smoke.2265920805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.1700280138 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 20924353 ps |
| CPU time | 1.45 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:45:14 AM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700280138 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1700280138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.576431010 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 738867764 ps |
| CPU time | 17.37 seconds |
| Started | Aug 25 07:44:46 AM UTC 24 |
| Finished | Aug 25 07:45:05 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576431010 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.576431010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.4228189396 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 375666570 ps |
| CPU time | 4.89 seconds |
| Started | Aug 25 07:44:57 AM UTC 24 |
| Finished | Aug 25 07:45:03 AM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228189396 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_acce ss.4228189396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.2123455489 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2112038708 ps |
| CPU time | 64.9 seconds |
| Started | Aug 25 07:44:49 AM UTC 24 |
| Finished | Aug 25 07:45:55 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123455489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_errors.2123455489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.4066540202 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 816344758 ps |
| CPU time | 9.26 seconds |
| Started | Aug 25 07:44:49 AM UTC 24 |
| Finished | Aug 25 07:44:59 AM UTC 24 |
| Peak memory | 232064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066540202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_jtag_prog_failure.4066540202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.3886745994 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 318047114 ps |
| CPU time | 6.9 seconds |
| Started | Aug 25 07:44:46 AM UTC 24 |
| Finished | Aug 25 07:44:54 AM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886745994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_smoke.3886745994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.41583098 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 5100805674 ps |
| CPU time | 112.03 seconds |
| Started | Aug 25 07:44:46 AM UTC 24 |
| Finished | Aug 25 07:46:41 AM UTC 24 |
| Peak memory | 289516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41583098 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct rl_jtag_state_failure.41583098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.1352845771 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1891651876 ps |
| CPU time | 13.33 seconds |
| Started | Aug 25 07:44:46 AM UTC 24 |
| Finished | Aug 25 07:45:01 AM UTC 24 |
| Peak memory | 238256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352845771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. lc_ctrl_jtag_state_post_trans.1352845771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.1734928450 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 79276217 ps |
| CPU time | 2.48 seconds |
| Started | Aug 25 07:44:44 AM UTC 24 |
| Finished | Aug 25 07:44:48 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734928450 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1734928450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.2149127593 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 702314974 ps |
| CPU time | 19.86 seconds |
| Started | Aug 25 07:44:57 AM UTC 24 |
| Finished | Aug 25 07:45:18 AM UTC 24 |
| Peak memory | 238188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149127593 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2149127593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.727114407 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 443735231 ps |
| CPU time | 20.65 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:45:33 AM UTC 24 |
| Peak memory | 237860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727114407 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_t oken_digest.727114407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.1891726033 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 364472801 ps |
| CPU time | 10.01 seconds |
| Started | Aug 25 07:44:57 AM UTC 24 |
| Finished | Aug 25 07:45:08 AM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891726033 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_tok en_mux.1891726033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.591431275 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 465680471 ps |
| CPU time | 14.84 seconds |
| Started | Aug 25 07:44:46 AM UTC 24 |
| Finished | Aug 25 07:45:02 AM UTC 24 |
| Peak memory | 238176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591431275 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.591431275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.1580130224 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 64202513 ps |
| CPU time | 3.33 seconds |
| Started | Aug 25 07:44:41 AM UTC 24 |
| Finished | Aug 25 07:44:45 AM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580130224 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1580130224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.1763456927 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1471229806 ps |
| CPU time | 42.46 seconds |
| Started | Aug 25 07:44:43 AM UTC 24 |
| Finished | Aug 25 07:45:27 AM UTC 24 |
| Peak memory | 262840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763456927 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1763456927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2339251989 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 75587197 ps |
| CPU time | 5.97 seconds |
| Started | Aug 25 07:44:44 AM UTC 24 |
| Finished | Aug 25 07:44:51 AM UTC 24 |
| Peak memory | 236580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339251989 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2339251989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.1631822714 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 844135041 ps |
| CPU time | 56.59 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:46:09 AM UTC 24 |
| Peak memory | 262760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1631822714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 17.lc_ctrl_stress_all.1631822714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3946245819 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 9378100659 ps |
| CPU time | 139.57 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:47:33 AM UTC 24 |
| Peak memory | 291620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946245819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3946245819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4010243570 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 12658611 ps |
| CPU time | 1.21 seconds |
| Started | Aug 25 07:44:42 AM UTC 24 |
| Finished | Aug 25 07:44:44 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010243570 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_volatile_unlock_smoke.4010243570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.1413524067 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 65574631 ps |
| CPU time | 1.67 seconds |
| Started | Aug 25 07:45:15 AM UTC 24 |
| Finished | Aug 25 07:45:18 AM UTC 24 |
| Peak memory | 218908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413524067 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1413524067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.1019124769 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 945643452 ps |
| CPU time | 13.43 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:45:26 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019124769 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1019124769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.694875888 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 4767903913 ps |
| CPU time | 17.85 seconds |
| Started | Aug 25 07:45:13 AM UTC 24 |
| Finished | Aug 25 07:45:33 AM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694875888 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.694875888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.743800102 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2067886301 ps |
| CPU time | 43.39 seconds |
| Started | Aug 25 07:45:13 AM UTC 24 |
| Finished | Aug 25 07:45:59 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743800102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_ jtag_errors.743800102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.854431507 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1098327184 ps |
| CPU time | 13.24 seconds |
| Started | Aug 25 07:45:13 AM UTC 24 |
| Finished | Aug 25 07:45:28 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854431507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct rl_jtag_prog_failure.854431507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.771541552 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1391643134 ps |
| CPU time | 9.92 seconds |
| Started | Aug 25 07:45:13 AM UTC 24 |
| Finished | Aug 25 07:45:24 AM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771541552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag _smoke.771541552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.773635754 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 5826017953 ps |
| CPU time | 76.56 seconds |
| Started | Aug 25 07:45:13 AM UTC 24 |
| Finished | Aug 25 07:46:32 AM UTC 24 |
| Peak memory | 283376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773635754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_jtag_state_failure.773635754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.1226484152 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 9835206139 ps |
| CPU time | 34.59 seconds |
| Started | Aug 25 07:45:13 AM UTC 24 |
| Finished | Aug 25 07:45:50 AM UTC 24 |
| Peak memory | 262820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226484152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18. lc_ctrl_jtag_state_post_trans.1226484152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1430243832 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 182174398 ps |
| CPU time | 3.49 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:45:16 AM UTC 24 |
| Peak memory | 236568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430243832 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1430243832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.3005251084 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 917283697 ps |
| CPU time | 12.54 seconds |
| Started | Aug 25 07:45:13 AM UTC 24 |
| Finished | Aug 25 07:45:28 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005251084 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3005251084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.2166861133 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1080996495 ps |
| CPU time | 9.02 seconds |
| Started | Aug 25 07:45:14 AM UTC 24 |
| Finished | Aug 25 07:45:24 AM UTC 24 |
| Peak memory | 237844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166861133 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_ token_digest.2166861133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.673203361 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 894578552 ps |
| CPU time | 16.22 seconds |
| Started | Aug 25 07:45:14 AM UTC 24 |
| Finished | Aug 25 07:45:31 AM UTC 24 |
| Peak memory | 232124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673203361 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_toke n_mux.673203361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3910567801 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1099944511 ps |
| CPU time | 13.99 seconds |
| Started | Aug 25 07:45:13 AM UTC 24 |
| Finished | Aug 25 07:45:29 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910567801 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3910567801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.236948580 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 342758791 ps |
| CPU time | 2.74 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:45:15 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236948580 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.236948580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.2116529891 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 710636977 ps |
| CPU time | 52.34 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:46:05 AM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116529891 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2116529891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.3763064771 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 78662362 ps |
| CPU time | 12.54 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:45:25 AM UTC 24 |
| Peak memory | 258996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763064771 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3763064771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.3530265581 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 74232222121 ps |
| CPU time | 764.98 seconds |
| Started | Aug 25 07:45:14 AM UTC 24 |
| Finished | Aug 25 07:58:09 AM UTC 24 |
| Peak memory | 326644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3530265581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 18.lc_ctrl_stress_all.3530265581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3197448249 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1572285473 ps |
| CPU time | 121.61 seconds |
| Started | Aug 25 07:45:15 AM UTC 24 |
| Finished | Aug 25 07:47:19 AM UTC 24 |
| Peak memory | 289548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197448249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3197448249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3705417097 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 21461552 ps |
| CPU time | 1.41 seconds |
| Started | Aug 25 07:45:11 AM UTC 24 |
| Finished | Aug 25 07:45:14 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705417097 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_volatile_unlock_smoke.3705417097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3430571280 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 31175534 ps |
| CPU time | 1.43 seconds |
| Started | Aug 25 07:45:29 AM UTC 24 |
| Finished | Aug 25 07:45:32 AM UTC 24 |
| Peak memory | 219392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430571280 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3430571280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.2717031165 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 694892708 ps |
| CPU time | 12.04 seconds |
| Started | Aug 25 07:45:18 AM UTC 24 |
| Finished | Aug 25 07:45:32 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717031165 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2717031165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.480678536 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 523452978 ps |
| CPU time | 10.26 seconds |
| Started | Aug 25 07:45:25 AM UTC 24 |
| Finished | Aug 25 07:45:37 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480678536 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.480678536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.608835759 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1544013276 ps |
| CPU time | 47.26 seconds |
| Started | Aug 25 07:45:25 AM UTC 24 |
| Finished | Aug 25 07:46:14 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608835759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_ jtag_errors.608835759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.3203304394 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 213437600 ps |
| CPU time | 3.91 seconds |
| Started | Aug 25 07:45:25 AM UTC 24 |
| Finished | Aug 25 07:45:30 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203304394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c trl_jtag_prog_failure.3203304394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.2679307561 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 462584848 ps |
| CPU time | 5.92 seconds |
| Started | Aug 25 07:45:20 AM UTC 24 |
| Finished | Aug 25 07:45:27 AM UTC 24 |
| Peak memory | 230256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679307561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_smoke.2679307561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.2167436553 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1619427045 ps |
| CPU time | 48 seconds |
| Started | Aug 25 07:45:20 AM UTC 24 |
| Finished | Aug 25 07:46:10 AM UTC 24 |
| Peak memory | 262760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167436553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ ctrl_jtag_state_failure.2167436553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.2282801885 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2398094491 ps |
| CPU time | 21.13 seconds |
| Started | Aug 25 07:45:25 AM UTC 24 |
| Finished | Aug 25 07:45:47 AM UTC 24 |
| Peak memory | 263220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282801885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19. lc_ctrl_jtag_state_post_trans.2282801885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3601465461 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 78784370 ps |
| CPU time | 4.39 seconds |
| Started | Aug 25 07:45:18 AM UTC 24 |
| Finished | Aug 25 07:45:24 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601465461 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3601465461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.3446811609 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 397491714 ps |
| CPU time | 24.04 seconds |
| Started | Aug 25 07:45:26 AM UTC 24 |
| Finished | Aug 25 07:45:52 AM UTC 24 |
| Peak memory | 232480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446811609 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3446811609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.2733715408 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 353346058 ps |
| CPU time | 19.83 seconds |
| Started | Aug 25 07:45:27 AM UTC 24 |
| Finished | Aug 25 07:45:49 AM UTC 24 |
| Peak memory | 238168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733715408 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_ token_digest.2733715408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.2380012183 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 335132184 ps |
| CPU time | 14.01 seconds |
| Started | Aug 25 07:45:27 AM UTC 24 |
| Finished | Aug 25 07:45:43 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380012183 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_tok en_mux.2380012183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.1034180784 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 449772010 ps |
| CPU time | 13.54 seconds |
| Started | Aug 25 07:45:20 AM UTC 24 |
| Finished | Aug 25 07:45:35 AM UTC 24 |
| Peak memory | 238188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034180784 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1034180784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.1951449643 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 499462936 ps |
| CPU time | 7.49 seconds |
| Started | Aug 25 07:45:15 AM UTC 24 |
| Finished | Aug 25 07:45:24 AM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951449643 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1951449643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.2488357255 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 884217278 ps |
| CPU time | 56.69 seconds |
| Started | Aug 25 07:45:16 AM UTC 24 |
| Finished | Aug 25 07:46:15 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488357255 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2488357255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.4143020780 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 66583811 ps |
| CPU time | 10.14 seconds |
| Started | Aug 25 07:45:16 AM UTC 24 |
| Finished | Aug 25 07:45:28 AM UTC 24 |
| Peak memory | 263032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143020780 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4143020780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2465536640 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 65692032356 ps |
| CPU time | 360.21 seconds |
| Started | Aug 25 07:45:29 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 432804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2465536640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 19.lc_ctrl_stress_all.2465536640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1055530488 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4937113450 ps |
| CPU time | 159.94 seconds |
| Started | Aug 25 07:45:29 AM UTC 24 |
| Finished | Aug 25 07:48:12 AM UTC 24 |
| Peak memory | 281676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055530488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1055530488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1110421614 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 46555253 ps |
| CPU time | 1.51 seconds |
| Started | Aug 25 07:45:15 AM UTC 24 |
| Finished | Aug 25 07:45:18 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110421614 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_volatile_unlock_smoke.1110421614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1463207031 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 58061507 ps |
| CPU time | 1.47 seconds |
| Started | Aug 25 07:40:17 AM UTC 24 |
| Finished | Aug 25 07:40:20 AM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463207031 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1463207031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.17721301 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 22586890 ps |
| CPU time | 1.31 seconds |
| Started | Aug 25 07:40:11 AM UTC 24 |
| Finished | Aug 25 07:40:14 AM UTC 24 |
| Peak memory | 217112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17721301 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.17721301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2169423350 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 340378991 ps |
| CPU time | 22.22 seconds |
| Started | Aug 25 07:40:03 AM UTC 24 |
| Finished | Aug 25 07:40:27 AM UTC 24 |
| Peak memory | 237860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169423350 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2169423350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.1514356961 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1081856497 ps |
| CPU time | 7.68 seconds |
| Started | Aug 25 07:40:12 AM UTC 24 |
| Finished | Aug 25 07:40:21 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514356961 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1514356961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.462383554 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6072019832 ps |
| CPU time | 64.45 seconds |
| Started | Aug 25 07:40:11 AM UTC 24 |
| Finished | Aug 25 07:41:19 AM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462383554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j tag_errors.462383554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.282621004 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 758410777 ps |
| CPU time | 28.65 seconds |
| Started | Aug 25 07:40:12 AM UTC 24 |
| Finished | Aug 25 07:40:42 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282621004 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_prio rity.282621004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.915090948 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2132501868 ps |
| CPU time | 13.55 seconds |
| Started | Aug 25 07:40:11 AM UTC 24 |
| Finished | Aug 25 07:40:27 AM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915090948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr l_jtag_prog_failure.915090948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1040296511 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1276544807 ps |
| CPU time | 41.25 seconds |
| Started | Aug 25 07:40:12 AM UTC 24 |
| Finished | Aug 25 07:40:56 AM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040296511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l c_ctrl_jtag_regwen_during_op.1040296511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2662360468 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 561817976 ps |
| CPU time | 6.85 seconds |
| Started | Aug 25 07:40:11 AM UTC 24 |
| Finished | Aug 25 07:40:20 AM UTC 24 |
| Peak memory | 230268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662360468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _smoke.2662360468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.3603785842 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1396252311 ps |
| CPU time | 55.08 seconds |
| Started | Aug 25 07:40:11 AM UTC 24 |
| Finished | Aug 25 07:41:09 AM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603785842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_c trl_jtag_state_failure.3603785842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3000311899 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 809792241 ps |
| CPU time | 25.14 seconds |
| Started | Aug 25 07:40:11 AM UTC 24 |
| Finished | Aug 25 07:40:38 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000311899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l c_ctrl_jtag_state_post_trans.3000311899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.3628812897 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 32602892 ps |
| CPU time | 2.97 seconds |
| Started | Aug 25 07:40:03 AM UTC 24 |
| Finished | Aug 25 07:40:07 AM UTC 24 |
| Peak memory | 234508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628812897 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3628812897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2480818324 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 328270411 ps |
| CPU time | 18.99 seconds |
| Started | Aug 25 07:40:11 AM UTC 24 |
| Finished | Aug 25 07:40:32 AM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480818324 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2480818324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1094582428 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 231647525 ps |
| CPU time | 73.72 seconds |
| Started | Aug 25 07:40:17 AM UTC 24 |
| Finished | Aug 25 07:41:33 AM UTC 24 |
| Peak memory | 292248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094582428 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1094582428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1659960994 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 463501894 ps |
| CPU time | 14.45 seconds |
| Started | Aug 25 07:40:12 AM UTC 24 |
| Finished | Aug 25 07:40:28 AM UTC 24 |
| Peak memory | 237844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659960994 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1659960994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3907431840 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3038751964 ps |
| CPU time | 28.14 seconds |
| Started | Aug 25 07:40:17 AM UTC 24 |
| Finished | Aug 25 07:40:46 AM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907431840 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_t oken_digest.3907431840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.3597722450 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 199296798 ps |
| CPU time | 12.5 seconds |
| Started | Aug 25 07:40:16 AM UTC 24 |
| Finished | Aug 25 07:40:31 AM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597722450 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_toke n_mux.3597722450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1611761429 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 951604619 ps |
| CPU time | 13.15 seconds |
| Started | Aug 25 07:40:03 AM UTC 24 |
| Finished | Aug 25 07:40:18 AM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611761429 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1611761429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1382109775 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 69876145 ps |
| CPU time | 4.53 seconds |
| Started | Aug 25 07:40:01 AM UTC 24 |
| Finished | Aug 25 07:40:06 AM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382109775 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1382109775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.4020550156 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 556807035 ps |
| CPU time | 53.4 seconds |
| Started | Aug 25 07:40:01 AM UTC 24 |
| Finished | Aug 25 07:40:56 AM UTC 24 |
| Peak memory | 258668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020550156 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.4020550156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3344197323 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 80968562 ps |
| CPU time | 13.04 seconds |
| Started | Aug 25 07:40:01 AM UTC 24 |
| Finished | Aug 25 07:40:15 AM UTC 24 |
| Peak memory | 263052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344197323 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3344197323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2629496600 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 104737477243 ps |
| CPU time | 365.86 seconds |
| Started | Aug 25 07:40:17 AM UTC 24 |
| Finished | Aug 25 07:46:28 AM UTC 24 |
| Peak memory | 283380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2629496600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.lc_ctrl_stress_all.2629496600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1870901702 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 6652355221 ps |
| CPU time | 120.75 seconds |
| Started | Aug 25 07:40:17 AM UTC 24 |
| Finished | Aug 25 07:42:20 AM UTC 24 |
| Peak memory | 281320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870901702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.1870901702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.13412643 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14033716 ps |
| CPU time | 1.71 seconds |
| Started | Aug 25 07:40:01 AM UTC 24 |
| Finished | Aug 25 07:40:03 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13412643 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. lc_ctrl_volatile_unlock_smoke.13412643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.52803341 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 92153103 ps |
| CPU time | 1.53 seconds |
| Started | Aug 25 07:45:38 AM UTC 24 |
| Finished | Aug 25 07:45:41 AM UTC 24 |
| Peak memory | 219092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52803341 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.52803341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3047471945 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2206314815 ps |
| CPU time | 14.79 seconds |
| Started | Aug 25 07:45:33 AM UTC 24 |
| Finished | Aug 25 07:45:49 AM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047471945 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3047471945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.2606448293 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 34214309 ps |
| CPU time | 1.98 seconds |
| Started | Aug 25 07:45:34 AM UTC 24 |
| Finished | Aug 25 07:45:37 AM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606448293 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_acce ss.2606448293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.2433628631 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 37163694 ps |
| CPU time | 2.77 seconds |
| Started | Aug 25 07:45:32 AM UTC 24 |
| Finished | Aug 25 07:45:37 AM UTC 24 |
| Peak memory | 234124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433628631 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2433628631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1203857210 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 813921445 ps |
| CPU time | 24.49 seconds |
| Started | Aug 25 07:45:34 AM UTC 24 |
| Finished | Aug 25 07:46:00 AM UTC 24 |
| Peak memory | 237928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203857210 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1203857210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1072544409 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 839554217 ps |
| CPU time | 23.74 seconds |
| Started | Aug 25 07:45:36 AM UTC 24 |
| Finished | Aug 25 07:46:01 AM UTC 24 |
| Peak memory | 237836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072544409 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_ token_digest.1072544409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3462319569 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 755651217 ps |
| CPU time | 11.91 seconds |
| Started | Aug 25 07:45:35 AM UTC 24 |
| Finished | Aug 25 07:45:48 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462319569 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_tok en_mux.3462319569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1125442768 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 973707832 ps |
| CPU time | 21.94 seconds |
| Started | Aug 25 07:45:34 AM UTC 24 |
| Finished | Aug 25 07:45:58 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125442768 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1125442768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3079699525 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 194907279 ps |
| CPU time | 4.13 seconds |
| Started | Aug 25 07:45:29 AM UTC 24 |
| Finished | Aug 25 07:45:34 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079699525 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3079699525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.3681269429 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1065865976 ps |
| CPU time | 64.9 seconds |
| Started | Aug 25 07:45:31 AM UTC 24 |
| Finished | Aug 25 07:46:38 AM UTC 24 |
| Peak memory | 262848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681269429 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3681269429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3147004074 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 118237646 ps |
| CPU time | 14.84 seconds |
| Started | Aug 25 07:45:32 AM UTC 24 |
| Finished | Aug 25 07:45:49 AM UTC 24 |
| Peak memory | 262712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147004074 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3147004074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.2169029445 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 8406706556 ps |
| CPU time | 78.77 seconds |
| Started | Aug 25 07:45:38 AM UTC 24 |
| Finished | Aug 25 07:46:59 AM UTC 24 |
| Peak memory | 279520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2169029445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 20.lc_ctrl_stress_all.2169029445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1257601153 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 26267216 ps |
| CPU time | 1.41 seconds |
| Started | Aug 25 07:45:30 AM UTC 24 |
| Finished | Aug 25 07:45:33 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257601153 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_volatile_unlock_smoke.1257601153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.576740220 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 16351295 ps |
| CPU time | 1.56 seconds |
| Started | Aug 25 07:45:52 AM UTC 24 |
| Finished | Aug 25 07:45:55 AM UTC 24 |
| Peak memory | 219036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576740220 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.576740220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1870892614 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 195332380 ps |
| CPU time | 12.85 seconds |
| Started | Aug 25 07:45:48 AM UTC 24 |
| Finished | Aug 25 07:46:02 AM UTC 24 |
| Peak memory | 238232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870892614 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1870892614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1951831532 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 203826494 ps |
| CPU time | 8.2 seconds |
| Started | Aug 25 07:45:50 AM UTC 24 |
| Finished | Aug 25 07:45:59 AM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951831532 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_acce ss.1951831532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2958257613 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 50174927 ps |
| CPU time | 4.14 seconds |
| Started | Aug 25 07:45:47 AM UTC 24 |
| Finished | Aug 25 07:45:53 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958257613 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2958257613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3429515316 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 3530927660 ps |
| CPU time | 16.34 seconds |
| Started | Aug 25 07:45:50 AM UTC 24 |
| Finished | Aug 25 07:46:07 AM UTC 24 |
| Peak memory | 234332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429515316 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3429515316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.3533616713 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1127490731 ps |
| CPU time | 17.84 seconds |
| Started | Aug 25 07:45:51 AM UTC 24 |
| Finished | Aug 25 07:46:10 AM UTC 24 |
| Peak memory | 237832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533616713 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_ token_digest.3533616713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.4054236635 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 189974564 ps |
| CPU time | 11.99 seconds |
| Started | Aug 25 07:45:50 AM UTC 24 |
| Finished | Aug 25 07:46:03 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054236635 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_tok en_mux.4054236635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3064819700 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2869006090 ps |
| CPU time | 20.77 seconds |
| Started | Aug 25 07:45:50 AM UTC 24 |
| Finished | Aug 25 07:46:12 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064819700 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3064819700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.721557606 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 66363308 ps |
| CPU time | 5.79 seconds |
| Started | Aug 25 07:45:43 AM UTC 24 |
| Finished | Aug 25 07:45:50 AM UTC 24 |
| Peak memory | 236116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721557606 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.721557606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2939317028 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 957449473 ps |
| CPU time | 44.79 seconds |
| Started | Aug 25 07:45:44 AM UTC 24 |
| Finished | Aug 25 07:46:30 AM UTC 24 |
| Peak memory | 262840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939317028 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2939317028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.4162565761 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 151991630 ps |
| CPU time | 4.27 seconds |
| Started | Aug 25 07:45:46 AM UTC 24 |
| Finished | Aug 25 07:45:51 AM UTC 24 |
| Peak memory | 234520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162565761 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.4162565761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3548696693 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 15170717179 ps |
| CPU time | 637.8 seconds |
| Started | Aug 25 07:45:51 AM UTC 24 |
| Finished | Aug 25 07:56:39 AM UTC 24 |
| Peak memory | 293548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3548696693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 21.lc_ctrl_stress_all.3548696693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1784994940 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 40424052 ps |
| CPU time | 1.25 seconds |
| Started | Aug 25 07:45:43 AM UTC 24 |
| Finished | Aug 25 07:45:45 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784994940 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_volatile_unlock_smoke.1784994940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.2010226467 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 104117466 ps |
| CPU time | 1.66 seconds |
| Started | Aug 25 07:46:02 AM UTC 24 |
| Finished | Aug 25 07:46:05 AM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010226467 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2010226467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.1822612317 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1660091216 ps |
| CPU time | 31.85 seconds |
| Started | Aug 25 07:45:57 AM UTC 24 |
| Finished | Aug 25 07:46:30 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822612317 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1822612317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.148168326 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 733711392 ps |
| CPU time | 9.46 seconds |
| Started | Aug 25 07:45:59 AM UTC 24 |
| Finished | Aug 25 07:46:10 AM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148168326 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.148168326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2173862398 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 52246979 ps |
| CPU time | 2.98 seconds |
| Started | Aug 25 07:45:56 AM UTC 24 |
| Finished | Aug 25 07:46:00 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173862398 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2173862398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2893489794 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1112020840 ps |
| CPU time | 13.31 seconds |
| Started | Aug 25 07:45:59 AM UTC 24 |
| Finished | Aug 25 07:46:14 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893489794 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2893489794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1118653982 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1452496264 ps |
| CPU time | 18.72 seconds |
| Started | Aug 25 07:46:01 AM UTC 24 |
| Finished | Aug 25 07:46:21 AM UTC 24 |
| Peak memory | 238172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118653982 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_ token_digest.1118653982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.3272728795 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 562003635 ps |
| CPU time | 13.24 seconds |
| Started | Aug 25 07:45:59 AM UTC 24 |
| Finished | Aug 25 07:46:14 AM UTC 24 |
| Peak memory | 231984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272728795 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_tok en_mux.3272728795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.857434626 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 441782329 ps |
| CPU time | 16.86 seconds |
| Started | Aug 25 07:45:58 AM UTC 24 |
| Finished | Aug 25 07:46:17 AM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857434626 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.857434626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.1133295020 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 53536005 ps |
| CPU time | 4.35 seconds |
| Started | Aug 25 07:45:52 AM UTC 24 |
| Finished | Aug 25 07:45:58 AM UTC 24 |
| Peak memory | 226060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133295020 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1133295020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.3847444057 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 308688054 ps |
| CPU time | 48.93 seconds |
| Started | Aug 25 07:45:54 AM UTC 24 |
| Finished | Aug 25 07:46:44 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847444057 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3847444057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.994231882 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 69453249 ps |
| CPU time | 11.82 seconds |
| Started | Aug 25 07:45:56 AM UTC 24 |
| Finished | Aug 25 07:46:09 AM UTC 24 |
| Peak memory | 260712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994231882 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.994231882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.4019852565 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 7397393175 ps |
| CPU time | 66.08 seconds |
| Started | Aug 25 07:46:01 AM UTC 24 |
| Finished | Aug 25 07:47:09 AM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4019852565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 22.lc_ctrl_stress_all.4019852565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3251255526 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 20237855 ps |
| CPU time | 1.24 seconds |
| Started | Aug 25 07:45:52 AM UTC 24 |
| Finished | Aug 25 07:45:55 AM UTC 24 |
| Peak memory | 219272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251255526 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_volatile_unlock_smoke.3251255526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.460378800 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 15648727 ps |
| CPU time | 1.36 seconds |
| Started | Aug 25 07:46:20 AM UTC 24 |
| Finished | Aug 25 07:46:23 AM UTC 24 |
| Peak memory | 217768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460378800 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.460378800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3678975201 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 378391083 ps |
| CPU time | 17.67 seconds |
| Started | Aug 25 07:46:09 AM UTC 24 |
| Finished | Aug 25 07:46:28 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678975201 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3678975201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.646530578 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 860152701 ps |
| CPU time | 6.01 seconds |
| Started | Aug 25 07:46:10 AM UTC 24 |
| Finished | Aug 25 07:46:17 AM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646530578 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.646530578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.321445517 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 146853521 ps |
| CPU time | 5.82 seconds |
| Started | Aug 25 07:46:07 AM UTC 24 |
| Finished | Aug 25 07:46:14 AM UTC 24 |
| Peak memory | 236236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321445517 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.321445517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.1483879575 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 350494153 ps |
| CPU time | 16.45 seconds |
| Started | Aug 25 07:46:10 AM UTC 24 |
| Finished | Aug 25 07:46:28 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483879575 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1483879575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.3195076279 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1220037876 ps |
| CPU time | 13.8 seconds |
| Started | Aug 25 07:46:18 AM UTC 24 |
| Finished | Aug 25 07:46:33 AM UTC 24 |
| Peak memory | 238168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195076279 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_ token_digest.3195076279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.2224541899 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1896800621 ps |
| CPU time | 18.06 seconds |
| Started | Aug 25 07:46:18 AM UTC 24 |
| Finished | Aug 25 07:46:37 AM UTC 24 |
| Peak memory | 238180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224541899 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_tok en_mux.2224541899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3807327676 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 676972304 ps |
| CPU time | 10.67 seconds |
| Started | Aug 25 07:46:10 AM UTC 24 |
| Finished | Aug 25 07:46:22 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807327676 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3807327676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.2574364096 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 653779657 ps |
| CPU time | 4.55 seconds |
| Started | Aug 25 07:46:03 AM UTC 24 |
| Finished | Aug 25 07:46:09 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574364096 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2574364096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.35084174 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 267655880 ps |
| CPU time | 55.8 seconds |
| Started | Aug 25 07:46:06 AM UTC 24 |
| Finished | Aug 25 07:47:04 AM UTC 24 |
| Peak memory | 263100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35084174 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.35084174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.3180219586 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 135177357 ps |
| CPU time | 10.03 seconds |
| Started | Aug 25 07:46:06 AM UTC 24 |
| Finished | Aug 25 07:46:18 AM UTC 24 |
| Peak memory | 260652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180219586 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3180219586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.1768962413 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 14938514730 ps |
| CPU time | 165.23 seconds |
| Started | Aug 25 07:46:18 AM UTC 24 |
| Finished | Aug 25 07:49:06 AM UTC 24 |
| Peak memory | 240188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1768962413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 23.lc_ctrl_stress_all.1768962413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1640755602 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 38262777 ps |
| CPU time | 1.44 seconds |
| Started | Aug 25 07:46:04 AM UTC 24 |
| Finished | Aug 25 07:46:07 AM UTC 24 |
| Peak memory | 220660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640755602 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_volatile_unlock_smoke.1640755602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.3684212874 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 17356036 ps |
| CPU time | 1.81 seconds |
| Started | Aug 25 07:46:23 AM UTC 24 |
| Finished | Aug 25 07:46:26 AM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684212874 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3684212874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.426873886 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 919112494 ps |
| CPU time | 29.51 seconds |
| Started | Aug 25 07:46:21 AM UTC 24 |
| Finished | Aug 25 07:46:52 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426873886 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.426873886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.799324852 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 129773450 ps |
| CPU time | 2.99 seconds |
| Started | Aug 25 07:46:21 AM UTC 24 |
| Finished | Aug 25 07:46:25 AM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799324852 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.799324852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2603237487 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 257470023 ps |
| CPU time | 4.49 seconds |
| Started | Aug 25 07:46:21 AM UTC 24 |
| Finished | Aug 25 07:46:26 AM UTC 24 |
| Peak memory | 236248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603237487 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2603237487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.4248609976 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 786074246 ps |
| CPU time | 21.19 seconds |
| Started | Aug 25 07:46:21 AM UTC 24 |
| Finished | Aug 25 07:46:43 AM UTC 24 |
| Peak memory | 237976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248609976 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4248609976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1012087630 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 272828500 ps |
| CPU time | 14.9 seconds |
| Started | Aug 25 07:46:22 AM UTC 24 |
| Finished | Aug 25 07:46:38 AM UTC 24 |
| Peak memory | 237836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012087630 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_ token_digest.1012087630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3110183137 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1797589724 ps |
| CPU time | 10.34 seconds |
| Started | Aug 25 07:46:21 AM UTC 24 |
| Finished | Aug 25 07:46:32 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110183137 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_tok en_mux.3110183137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.3639669047 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 164270684 ps |
| CPU time | 9.68 seconds |
| Started | Aug 25 07:46:21 AM UTC 24 |
| Finished | Aug 25 07:46:32 AM UTC 24 |
| Peak memory | 237996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639669047 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3639669047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3476644032 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 139515318 ps |
| CPU time | 4.13 seconds |
| Started | Aug 25 07:46:20 AM UTC 24 |
| Finished | Aug 25 07:46:26 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476644032 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3476644032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.2924434330 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 558609570 ps |
| CPU time | 49.2 seconds |
| Started | Aug 25 07:46:20 AM UTC 24 |
| Finished | Aug 25 07:47:11 AM UTC 24 |
| Peak memory | 262836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924434330 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2924434330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.3601470407 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 240097589 ps |
| CPU time | 8.76 seconds |
| Started | Aug 25 07:46:21 AM UTC 24 |
| Finished | Aug 25 07:46:31 AM UTC 24 |
| Peak memory | 256976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601470407 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3601470407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.4163821216 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 5915756703 ps |
| CPU time | 80.43 seconds |
| Started | Aug 25 07:46:22 AM UTC 24 |
| Finished | Aug 25 07:47:45 AM UTC 24 |
| Peak memory | 237988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4163821216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 24.lc_ctrl_stress_all.4163821216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1988577641 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 16689005 ps |
| CPU time | 1.46 seconds |
| Started | Aug 25 07:46:20 AM UTC 24 |
| Finished | Aug 25 07:46:23 AM UTC 24 |
| Peak memory | 229032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988577641 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_volatile_unlock_smoke.1988577641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3900126318 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 75117534 ps |
| CPU time | 1.54 seconds |
| Started | Aug 25 07:46:31 AM UTC 24 |
| Finished | Aug 25 07:46:34 AM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900126318 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3900126318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1603358476 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2266462211 ps |
| CPU time | 29.85 seconds |
| Started | Aug 25 07:46:30 AM UTC 24 |
| Finished | Aug 25 07:47:01 AM UTC 24 |
| Peak memory | 237940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603358476 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1603358476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.3172998068 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 64080702 ps |
| CPU time | 1.73 seconds |
| Started | Aug 25 07:46:30 AM UTC 24 |
| Finished | Aug 25 07:46:33 AM UTC 24 |
| Peak memory | 228376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172998068 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_acce ss.3172998068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.253720477 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 63302433 ps |
| CPU time | 3.25 seconds |
| Started | Aug 25 07:46:28 AM UTC 24 |
| Finished | Aug 25 07:46:32 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253720477 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.253720477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.925245031 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1259051059 ps |
| CPU time | 15.91 seconds |
| Started | Aug 25 07:46:30 AM UTC 24 |
| Finished | Aug 25 07:46:47 AM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925245031 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.925245031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1114015011 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 252661153 ps |
| CPU time | 14.53 seconds |
| Started | Aug 25 07:46:30 AM UTC 24 |
| Finished | Aug 25 07:46:46 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114015011 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_ token_digest.1114015011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.3756541891 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1252992944 ps |
| CPU time | 14.91 seconds |
| Started | Aug 25 07:46:30 AM UTC 24 |
| Finished | Aug 25 07:46:46 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756541891 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_tok en_mux.3756541891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.2744855261 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 275614724 ps |
| CPU time | 10.55 seconds |
| Started | Aug 25 07:46:30 AM UTC 24 |
| Finished | Aug 25 07:46:42 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744855261 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2744855261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2202323744 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 174879432 ps |
| CPU time | 3.82 seconds |
| Started | Aug 25 07:46:23 AM UTC 24 |
| Finished | Aug 25 07:46:28 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202323744 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2202323744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1859164208 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 192041778 ps |
| CPU time | 59.37 seconds |
| Started | Aug 25 07:46:27 AM UTC 24 |
| Finished | Aug 25 07:47:28 AM UTC 24 |
| Peak memory | 263096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859164208 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1859164208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.770866696 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 582554319 ps |
| CPU time | 7.17 seconds |
| Started | Aug 25 07:46:28 AM UTC 24 |
| Finished | Aug 25 07:46:36 AM UTC 24 |
| Peak memory | 234848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770866696 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.770866696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.2387528544 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 11009712090 ps |
| CPU time | 66.23 seconds |
| Started | Aug 25 07:46:31 AM UTC 24 |
| Finished | Aug 25 07:47:39 AM UTC 24 |
| Peak memory | 262436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2387528544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 25.lc_ctrl_stress_all.2387528544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.774628241 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 31011870 ps |
| CPU time | 1.23 seconds |
| Started | Aug 25 07:46:25 AM UTC 24 |
| Finished | Aug 25 07:46:28 AM UTC 24 |
| Peak memory | 218596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774628241 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.lc_ctrl_volatile_unlock_smoke.774628241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2752331929 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 64696017 ps |
| CPU time | 1.63 seconds |
| Started | Aug 25 07:46:40 AM UTC 24 |
| Finished | Aug 25 07:46:43 AM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752331929 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2752331929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.3134903212 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 286997701 ps |
| CPU time | 16.53 seconds |
| Started | Aug 25 07:46:34 AM UTC 24 |
| Finished | Aug 25 07:46:52 AM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134903212 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3134903212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3331100807 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1901521362 ps |
| CPU time | 15.59 seconds |
| Started | Aug 25 07:46:36 AM UTC 24 |
| Finished | Aug 25 07:46:53 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331100807 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_acce ss.3331100807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.3182364322 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 981374788 ps |
| CPU time | 3.74 seconds |
| Started | Aug 25 07:46:34 AM UTC 24 |
| Finished | Aug 25 07:46:39 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182364322 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3182364322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2800717006 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2011710125 ps |
| CPU time | 19.47 seconds |
| Started | Aug 25 07:46:36 AM UTC 24 |
| Finished | Aug 25 07:46:57 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800717006 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2800717006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.3881827584 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 611767755 ps |
| CPU time | 21.01 seconds |
| Started | Aug 25 07:46:40 AM UTC 24 |
| Finished | Aug 25 07:47:02 AM UTC 24 |
| Peak memory | 238036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881827584 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_ token_digest.3881827584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.935756781 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 829260767 ps |
| CPU time | 14.3 seconds |
| Started | Aug 25 07:46:38 AM UTC 24 |
| Finished | Aug 25 07:46:54 AM UTC 24 |
| Peak memory | 237840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935756781 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_toke n_mux.935756781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1990025055 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 595546716 ps |
| CPU time | 26.86 seconds |
| Started | Aug 25 07:46:35 AM UTC 24 |
| Finished | Aug 25 07:47:04 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990025055 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1990025055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.166680134 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 286349554 ps |
| CPU time | 4.55 seconds |
| Started | Aug 25 07:46:33 AM UTC 24 |
| Finished | Aug 25 07:46:38 AM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166680134 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.166680134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.2556938232 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1248236122 ps |
| CPU time | 60.13 seconds |
| Started | Aug 25 07:46:33 AM UTC 24 |
| Finished | Aug 25 07:47:35 AM UTC 24 |
| Peak memory | 258672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556938232 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2556938232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1988874841 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 81939452 ps |
| CPU time | 5 seconds |
| Started | Aug 25 07:46:34 AM UTC 24 |
| Finished | Aug 25 07:46:40 AM UTC 24 |
| Peak memory | 234600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988874841 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1988874841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.1674056064 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 4951117063 ps |
| CPU time | 143.21 seconds |
| Started | Aug 25 07:46:40 AM UTC 24 |
| Finished | Aug 25 07:49:06 AM UTC 24 |
| Peak memory | 289448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1674056064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 26.lc_ctrl_stress_all.1674056064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1661693903 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 13042818 ps |
| CPU time | 1.58 seconds |
| Started | Aug 25 07:46:33 AM UTC 24 |
| Finished | Aug 25 07:46:36 AM UTC 24 |
| Peak memory | 220660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661693903 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_volatile_unlock_smoke.1661693903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.453956296 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 37564745 ps |
| CPU time | 1.49 seconds |
| Started | Aug 25 07:46:54 AM UTC 24 |
| Finished | Aug 25 07:46:56 AM UTC 24 |
| Peak memory | 219036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453956296 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.453956296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.198865297 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 260764795 ps |
| CPU time | 18.75 seconds |
| Started | Aug 25 07:46:45 AM UTC 24 |
| Finished | Aug 25 07:47:05 AM UTC 24 |
| Peak memory | 237608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198865297 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.198865297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.371279562 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 8600316733 ps |
| CPU time | 16.88 seconds |
| Started | Aug 25 07:46:47 AM UTC 24 |
| Finished | Aug 25 07:47:05 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371279562 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.371279562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3292525438 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 189748885 ps |
| CPU time | 4.2 seconds |
| Started | Aug 25 07:46:45 AM UTC 24 |
| Finished | Aug 25 07:46:50 AM UTC 24 |
| Peak memory | 236312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292525438 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3292525438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.3586055136 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 207468198 ps |
| CPU time | 12.17 seconds |
| Started | Aug 25 07:46:47 AM UTC 24 |
| Finished | Aug 25 07:47:01 AM UTC 24 |
| Peak memory | 238188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586055136 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3586055136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.2507988315 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 424569807 ps |
| CPU time | 17.28 seconds |
| Started | Aug 25 07:46:48 AM UTC 24 |
| Finished | Aug 25 07:47:07 AM UTC 24 |
| Peak memory | 238172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507988315 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_ token_digest.2507988315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.743227229 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1502606308 ps |
| CPU time | 18.12 seconds |
| Started | Aug 25 07:46:47 AM UTC 24 |
| Finished | Aug 25 07:47:07 AM UTC 24 |
| Peak memory | 232336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743227229 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_toke n_mux.743227229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2176166626 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 6296720736 ps |
| CPU time | 19.02 seconds |
| Started | Aug 25 07:46:45 AM UTC 24 |
| Finished | Aug 25 07:47:05 AM UTC 24 |
| Peak memory | 232600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176166626 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2176166626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3268894719 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 220711971 ps |
| CPU time | 3.9 seconds |
| Started | Aug 25 07:46:41 AM UTC 24 |
| Finished | Aug 25 07:46:46 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268894719 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3268894719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.486210504 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1357610676 ps |
| CPU time | 59.08 seconds |
| Started | Aug 25 07:46:43 AM UTC 24 |
| Finished | Aug 25 07:47:43 AM UTC 24 |
| Peak memory | 262840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486210504 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.486210504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.2330983823 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 51089663 ps |
| CPU time | 12.82 seconds |
| Started | Aug 25 07:46:44 AM UTC 24 |
| Finished | Aug 25 07:46:58 AM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330983823 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2330983823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.623447957 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 19371168776 ps |
| CPU time | 467.22 seconds |
| Started | Aug 25 07:46:52 AM UTC 24 |
| Finished | Aug 25 07:54:46 AM UTC 24 |
| Peak memory | 295748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=623447957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 27.lc_ctrl_stress_all.623447957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1446367609 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 25788889 ps |
| CPU time | 1.33 seconds |
| Started | Aug 25 07:46:41 AM UTC 24 |
| Finished | Aug 25 07:46:44 AM UTC 24 |
| Peak memory | 222964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446367609 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_volatile_unlock_smoke.1446367609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.1874420250 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 89790454 ps |
| CPU time | 1.34 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:30 AM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874420250 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1874420250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2508341837 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 499981371 ps |
| CPU time | 24.96 seconds |
| Started | Aug 25 07:46:58 AM UTC 24 |
| Finished | Aug 25 07:47:25 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508341837 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2508341837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.1097361416 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 3689855770 ps |
| CPU time | 14.18 seconds |
| Started | Aug 25 07:46:59 AM UTC 24 |
| Finished | Aug 25 07:47:14 AM UTC 24 |
| Peak memory | 230424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097361416 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_acce ss.1097361416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.1284923970 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 57326276 ps |
| CPU time | 4.52 seconds |
| Started | Aug 25 07:46:57 AM UTC 24 |
| Finished | Aug 25 07:47:03 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284923970 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1284923970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.3775650075 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 213152772 ps |
| CPU time | 15.56 seconds |
| Started | Aug 25 07:47:24 AM UTC 24 |
| Finished | Aug 25 07:47:41 AM UTC 24 |
| Peak memory | 237856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775650075 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3775650075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2761741023 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1558948019 ps |
| CPU time | 17.37 seconds |
| Started | Aug 25 07:47:24 AM UTC 24 |
| Finished | Aug 25 07:47:43 AM UTC 24 |
| Peak memory | 232124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761741023 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_ token_digest.2761741023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.2668952174 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 981931249 ps |
| CPU time | 10.29 seconds |
| Started | Aug 25 07:47:24 AM UTC 24 |
| Finished | Aug 25 07:47:35 AM UTC 24 |
| Peak memory | 232532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668952174 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_tok en_mux.2668952174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1394090346 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2548594903 ps |
| CPU time | 8.41 seconds |
| Started | Aug 25 07:46:58 AM UTC 24 |
| Finished | Aug 25 07:47:08 AM UTC 24 |
| Peak memory | 237996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394090346 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1394090346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.4221358768 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 16318997 ps |
| CPU time | 1.96 seconds |
| Started | Aug 25 07:46:54 AM UTC 24 |
| Finished | Aug 25 07:46:57 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221358768 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4221358768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.1111337511 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 809444081 ps |
| CPU time | 54.08 seconds |
| Started | Aug 25 07:46:55 AM UTC 24 |
| Finished | Aug 25 07:47:51 AM UTC 24 |
| Peak memory | 262840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111337511 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1111337511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.3839687962 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 357064354 ps |
| CPU time | 11.08 seconds |
| Started | Aug 25 07:46:57 AM UTC 24 |
| Finished | Aug 25 07:47:09 AM UTC 24 |
| Peak memory | 260624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839687962 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3839687962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1618791926 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 18859194659 ps |
| CPU time | 104.61 seconds |
| Started | Aug 25 07:47:27 AM UTC 24 |
| Finished | Aug 25 07:49:15 AM UTC 24 |
| Peak memory | 281508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618791926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1618791926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3830763227 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 21736633 ps |
| CPU time | 1.21 seconds |
| Started | Aug 25 07:46:54 AM UTC 24 |
| Finished | Aug 25 07:46:56 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830763227 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_volatile_unlock_smoke.3830763227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2504501787 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 43407536 ps |
| CPU time | 2.26 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:32 AM UTC 24 |
| Peak memory | 219380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504501787 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2504501787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.4030415427 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 254427673 ps |
| CPU time | 16.12 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:46 AM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030415427 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4030415427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3503830367 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1632447721 ps |
| CPU time | 3.38 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:33 AM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503830367 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_acce ss.3503830367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2458463234 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 91324924 ps |
| CPU time | 5.63 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:35 AM UTC 24 |
| Peak memory | 232344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458463234 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2458463234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.870643143 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1150124634 ps |
| CPU time | 14.38 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:44 AM UTC 24 |
| Peak memory | 232460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870643143 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.870643143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.2409162823 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1075769902 ps |
| CPU time | 12.11 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:42 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409162823 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_ token_digest.2409162823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.1916545846 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 4716043966 ps |
| CPU time | 25.91 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:56 AM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916545846 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_tok en_mux.1916545846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1544875633 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 773299580 ps |
| CPU time | 18.71 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:49 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544875633 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1544875633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.3272613094 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 15739383 ps |
| CPU time | 1.53 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:31 AM UTC 24 |
| Peak memory | 222704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272613094 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3272613094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.3967879362 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1545314521 ps |
| CPU time | 50.6 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:48:20 AM UTC 24 |
| Peak memory | 258744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967879362 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3967879362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.1984139191 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 665096631 ps |
| CPU time | 4.37 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:34 AM UTC 24 |
| Peak memory | 234528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984139191 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1984139191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.1833085530 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 7050127870 ps |
| CPU time | 79.01 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:48:49 AM UTC 24 |
| Peak memory | 262836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1833085530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 29.lc_ctrl_stress_all.1833085530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2002504824 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 13162075706 ps |
| CPU time | 106.36 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:49:17 AM UTC 24 |
| Peak memory | 281412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002504824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2002504824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.266082209 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 19639870 ps |
| CPU time | 1.33 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:30 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266082209 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.lc_ctrl_volatile_unlock_smoke.266082209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.3538814613 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 20630044 ps |
| CPU time | 1.52 seconds |
| Started | Aug 25 07:40:37 AM UTC 24 |
| Finished | Aug 25 07:40:40 AM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538814613 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3538814613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1367720590 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1521847157 ps |
| CPU time | 30.91 seconds |
| Started | Aug 25 07:40:20 AM UTC 24 |
| Finished | Aug 25 07:40:53 AM UTC 24 |
| Peak memory | 238188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367720590 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1367720590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2220649787 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 155261452 ps |
| CPU time | 2.81 seconds |
| Started | Aug 25 07:40:28 AM UTC 24 |
| Finished | Aug 25 07:40:32 AM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220649787 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2220649787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.3512345121 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 11411734358 ps |
| CPU time | 55.94 seconds |
| Started | Aug 25 07:40:28 AM UTC 24 |
| Finished | Aug 25 07:41:26 AM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512345121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_errors.3512345121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.67602402 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 498285804 ps |
| CPU time | 10.44 seconds |
| Started | Aug 25 07:40:28 AM UTC 24 |
| Finished | Aug 25 07:40:40 AM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67602402 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.67602402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1740345516 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 156759358 ps |
| CPU time | 4.78 seconds |
| Started | Aug 25 07:40:28 AM UTC 24 |
| Finished | Aug 25 07:40:34 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740345516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct rl_jtag_prog_failure.1740345516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1373828759 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 4116201350 ps |
| CPU time | 28.37 seconds |
| Started | Aug 25 07:40:29 AM UTC 24 |
| Finished | Aug 25 07:40:59 AM UTC 24 |
| Peak memory | 230160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373828759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.l c_ctrl_jtag_regwen_during_op.1373828759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.3496859080 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 969588627 ps |
| CPU time | 12.99 seconds |
| Started | Aug 25 07:40:24 AM UTC 24 |
| Finished | Aug 25 07:40:38 AM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496859080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _smoke.3496859080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.6372585 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1511487452 ps |
| CPU time | 103.65 seconds |
| Started | Aug 25 07:40:27 AM UTC 24 |
| Finished | Aug 25 07:42:13 AM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6372585 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _jtag_state_failure.6372585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.4259487731 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 408972817 ps |
| CPU time | 16.53 seconds |
| Started | Aug 25 07:40:28 AM UTC 24 |
| Finished | Aug 25 07:40:46 AM UTC 24 |
| Peak memory | 256616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259487731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.l c_ctrl_jtag_state_post_trans.4259487731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.4238039919 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 162720455 ps |
| CPU time | 5.97 seconds |
| Started | Aug 25 07:40:20 AM UTC 24 |
| Finished | Aug 25 07:40:28 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238039919 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4238039919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.884997835 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3303812540 ps |
| CPU time | 24.05 seconds |
| Started | Aug 25 07:40:22 AM UTC 24 |
| Finished | Aug 25 07:40:48 AM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884997835 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.884997835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.73916883 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 543220994 ps |
| CPU time | 22.89 seconds |
| Started | Aug 25 07:40:29 AM UTC 24 |
| Finished | Aug 25 07:40:54 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73916883 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.73916883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2862564399 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 334368646 ps |
| CPU time | 19.97 seconds |
| Started | Aug 25 07:40:33 AM UTC 24 |
| Finished | Aug 25 07:40:54 AM UTC 24 |
| Peak memory | 237856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862564399 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_t oken_digest.2862564399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3261957596 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 351816053 ps |
| CPU time | 14.57 seconds |
| Started | Aug 25 07:40:31 AM UTC 24 |
| Finished | Aug 25 07:40:48 AM UTC 24 |
| Peak memory | 238200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261957596 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_toke n_mux.3261957596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3989828367 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 301328354 ps |
| CPU time | 19.27 seconds |
| Started | Aug 25 07:40:20 AM UTC 24 |
| Finished | Aug 25 07:40:41 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989828367 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3989828367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.203721711 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 60907686 ps |
| CPU time | 4.66 seconds |
| Started | Aug 25 07:40:17 AM UTC 24 |
| Finished | Aug 25 07:40:23 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203721711 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.203721711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.4006352007 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 267797964 ps |
| CPU time | 73.31 seconds |
| Started | Aug 25 07:40:20 AM UTC 24 |
| Finished | Aug 25 07:41:36 AM UTC 24 |
| Peak memory | 260720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006352007 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.4006352007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1440567054 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 515091168 ps |
| CPU time | 5.3 seconds |
| Started | Aug 25 07:40:20 AM UTC 24 |
| Finished | Aug 25 07:40:27 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440567054 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1440567054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3910361490 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 304147049325 ps |
| CPU time | 508.66 seconds |
| Started | Aug 25 07:40:33 AM UTC 24 |
| Finished | Aug 25 07:49:09 AM UTC 24 |
| Peak memory | 291588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3910361490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 3.lc_ctrl_stress_all.3910361490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2303956690 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 47242675 ps |
| CPU time | 1.35 seconds |
| Started | Aug 25 07:40:17 AM UTC 24 |
| Finished | Aug 25 07:40:20 AM UTC 24 |
| Peak memory | 220664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303956690 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_volatile_unlock_smoke.2303956690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2383018480 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 15332207 ps |
| CPU time | 1.3 seconds |
| Started | Aug 25 07:47:36 AM UTC 24 |
| Finished | Aug 25 07:47:38 AM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383018480 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2383018480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.2329469395 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1646173592 ps |
| CPU time | 19.12 seconds |
| Started | Aug 25 07:47:31 AM UTC 24 |
| Finished | Aug 25 07:47:51 AM UTC 24 |
| Peak memory | 238080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329469395 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2329469395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.3680561720 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1675624033 ps |
| CPU time | 10.01 seconds |
| Started | Aug 25 07:47:32 AM UTC 24 |
| Finished | Aug 25 07:47:43 AM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680561720 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_acce ss.3680561720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.4121126142 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 219402789 ps |
| CPU time | 4.53 seconds |
| Started | Aug 25 07:47:30 AM UTC 24 |
| Finished | Aug 25 07:47:35 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121126142 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.4121126142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.853230551 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2375606132 ps |
| CPU time | 40.8 seconds |
| Started | Aug 25 07:47:32 AM UTC 24 |
| Finished | Aug 25 07:48:15 AM UTC 24 |
| Peak memory | 237896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853230551 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.853230551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.2273152223 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1653790709 ps |
| CPU time | 16.05 seconds |
| Started | Aug 25 07:47:34 AM UTC 24 |
| Finished | Aug 25 07:47:52 AM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273152223 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_ token_digest.2273152223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1099863247 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 236355041 ps |
| CPU time | 10.36 seconds |
| Started | Aug 25 07:47:33 AM UTC 24 |
| Finished | Aug 25 07:47:45 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099863247 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_tok en_mux.1099863247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.305900364 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 681639328 ps |
| CPU time | 14.1 seconds |
| Started | Aug 25 07:47:31 AM UTC 24 |
| Finished | Aug 25 07:47:46 AM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305900364 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.305900364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.2007270614 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 198543825 ps |
| CPU time | 5.43 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:35 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007270614 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2007270614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1518329627 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 255428573 ps |
| CPU time | 44.49 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:48:15 AM UTC 24 |
| Peak memory | 260788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518329627 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1518329627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.2150195411 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 158467930 ps |
| CPU time | 4.34 seconds |
| Started | Aug 25 07:47:30 AM UTC 24 |
| Finished | Aug 25 07:47:35 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150195411 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2150195411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.698456060 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 152748122375 ps |
| CPU time | 485.42 seconds |
| Started | Aug 25 07:47:34 AM UTC 24 |
| Finished | Aug 25 07:55:47 AM UTC 24 |
| Peak memory | 262864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=698456060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 30.lc_ctrl_stress_all.698456060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2928533164 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1474103450 ps |
| CPU time | 73.54 seconds |
| Started | Aug 25 07:47:34 AM UTC 24 |
| Finished | Aug 25 07:48:50 AM UTC 24 |
| Peak memory | 262880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928533164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2928533164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3949651035 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 15226584 ps |
| CPU time | 1.49 seconds |
| Started | Aug 25 07:47:28 AM UTC 24 |
| Finished | Aug 25 07:47:31 AM UTC 24 |
| Peak memory | 220664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949651035 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_volatile_unlock_smoke.3949651035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.536471846 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 26821534 ps |
| CPU time | 1.26 seconds |
| Started | Aug 25 07:47:44 AM UTC 24 |
| Finished | Aug 25 07:47:47 AM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536471846 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.536471846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.87362400 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3786632582 ps |
| CPU time | 20.04 seconds |
| Started | Aug 25 07:47:38 AM UTC 24 |
| Finished | Aug 25 07:48:00 AM UTC 24 |
| Peak memory | 237992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87362400 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.87362400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.4199020563 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 155530601 ps |
| CPU time | 4.01 seconds |
| Started | Aug 25 07:47:39 AM UTC 24 |
| Finished | Aug 25 07:47:45 AM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199020563 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_acce ss.4199020563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.915916872 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 364184842 ps |
| CPU time | 4.69 seconds |
| Started | Aug 25 07:47:37 AM UTC 24 |
| Finished | Aug 25 07:47:43 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915916872 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.915916872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2638087575 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 291245163 ps |
| CPU time | 14.02 seconds |
| Started | Aug 25 07:47:39 AM UTC 24 |
| Finished | Aug 25 07:47:55 AM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638087575 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2638087575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.4121851833 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1313794519 ps |
| CPU time | 15.52 seconds |
| Started | Aug 25 07:47:42 AM UTC 24 |
| Finished | Aug 25 07:47:59 AM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121851833 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_ token_digest.4121851833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.2343115225 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1112727367 ps |
| CPU time | 14.65 seconds |
| Started | Aug 25 07:47:41 AM UTC 24 |
| Finished | Aug 25 07:47:57 AM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343115225 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_tok en_mux.2343115225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.3305729629 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 884733543 ps |
| CPU time | 10.68 seconds |
| Started | Aug 25 07:47:39 AM UTC 24 |
| Finished | Aug 25 07:47:51 AM UTC 24 |
| Peak memory | 237124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305729629 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3305729629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2472586125 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 16211166 ps |
| CPU time | 1.49 seconds |
| Started | Aug 25 07:47:36 AM UTC 24 |
| Finished | Aug 25 07:47:39 AM UTC 24 |
| Peak memory | 228832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472586125 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2472586125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.428667853 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 597148205 ps |
| CPU time | 37.12 seconds |
| Started | Aug 25 07:47:36 AM UTC 24 |
| Finished | Aug 25 07:48:15 AM UTC 24 |
| Peak memory | 258676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428667853 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.428667853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.1891433999 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 597800386 ps |
| CPU time | 12.85 seconds |
| Started | Aug 25 07:47:37 AM UTC 24 |
| Finished | Aug 25 07:47:51 AM UTC 24 |
| Peak memory | 262688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891433999 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1891433999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.365842946 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 9446267282 ps |
| CPU time | 206.37 seconds |
| Started | Aug 25 07:47:43 AM UTC 24 |
| Finished | Aug 25 07:51:13 AM UTC 24 |
| Peak memory | 262828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=365842946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 31.lc_ctrl_stress_all.365842946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2437859677 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 44225426 ps |
| CPU time | 1.25 seconds |
| Started | Aug 25 07:47:36 AM UTC 24 |
| Finished | Aug 25 07:47:38 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437859677 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_volatile_unlock_smoke.2437859677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.289119205 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 35840622 ps |
| CPU time | 1.64 seconds |
| Started | Aug 25 07:47:52 AM UTC 24 |
| Finished | Aug 25 07:47:54 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289119205 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.289119205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.1796837354 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 1928695557 ps |
| CPU time | 20.44 seconds |
| Started | Aug 25 07:47:46 AM UTC 24 |
| Finished | Aug 25 07:48:08 AM UTC 24 |
| Peak memory | 237840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796837354 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1796837354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.609456644 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 325528179 ps |
| CPU time | 8 seconds |
| Started | Aug 25 07:47:47 AM UTC 24 |
| Finished | Aug 25 07:47:56 AM UTC 24 |
| Peak memory | 230264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609456644 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.609456644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.3667611990 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 159412377 ps |
| CPU time | 8.96 seconds |
| Started | Aug 25 07:47:46 AM UTC 24 |
| Finished | Aug 25 07:47:56 AM UTC 24 |
| Peak memory | 236240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667611990 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3667611990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.27506021 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1416128926 ps |
| CPU time | 16.05 seconds |
| Started | Aug 25 07:47:47 AM UTC 24 |
| Finished | Aug 25 07:48:04 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27506021 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.27506021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2635483614 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2372506275 ps |
| CPU time | 30.39 seconds |
| Started | Aug 25 07:47:48 AM UTC 24 |
| Finished | Aug 25 07:48:20 AM UTC 24 |
| Peak memory | 237976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635483614 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_ token_digest.2635483614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.4127911476 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1065835585 ps |
| CPU time | 14.06 seconds |
| Started | Aug 25 07:47:47 AM UTC 24 |
| Finished | Aug 25 07:48:02 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127911476 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_tok en_mux.4127911476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.1534153861 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1156902574 ps |
| CPU time | 16.38 seconds |
| Started | Aug 25 07:47:47 AM UTC 24 |
| Finished | Aug 25 07:48:05 AM UTC 24 |
| Peak memory | 238188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534153861 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1534153861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.988306457 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 68990075 ps |
| CPU time | 2.04 seconds |
| Started | Aug 25 07:47:44 AM UTC 24 |
| Finished | Aug 25 07:47:48 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988306457 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.988306457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.4019223490 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 351031417 ps |
| CPU time | 63.7 seconds |
| Started | Aug 25 07:47:46 AM UTC 24 |
| Finished | Aug 25 07:48:51 AM UTC 24 |
| Peak memory | 260940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019223490 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4019223490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.2737519492 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 76069132 ps |
| CPU time | 11.69 seconds |
| Started | Aug 25 07:47:46 AM UTC 24 |
| Finished | Aug 25 07:47:59 AM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737519492 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2737519492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.2298459047 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 5329579334 ps |
| CPU time | 164.18 seconds |
| Started | Aug 25 07:47:50 AM UTC 24 |
| Finished | Aug 25 07:50:37 AM UTC 24 |
| Peak memory | 281336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2298459047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 32.lc_ctrl_stress_all.2298459047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1118211552 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 15433906279 ps |
| CPU time | 200.52 seconds |
| Started | Aug 25 07:47:52 AM UTC 24 |
| Finished | Aug 25 07:51:16 AM UTC 24 |
| Peak memory | 311792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118211552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1118211552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.778115174 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 45194856 ps |
| CPU time | 1.21 seconds |
| Started | Aug 25 07:47:44 AM UTC 24 |
| Finished | Aug 25 07:47:47 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778115174 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.lc_ctrl_volatile_unlock_smoke.778115174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.1044724216 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 76288471 ps |
| CPU time | 1.57 seconds |
| Started | Aug 25 07:47:58 AM UTC 24 |
| Finished | Aug 25 07:48:01 AM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044724216 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1044724216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3372712201 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 599234406 ps |
| CPU time | 26.72 seconds |
| Started | Aug 25 07:47:56 AM UTC 24 |
| Finished | Aug 25 07:48:24 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372712201 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3372712201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3917468901 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 6111590414 ps |
| CPU time | 31.08 seconds |
| Started | Aug 25 07:47:57 AM UTC 24 |
| Finished | Aug 25 07:48:29 AM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917468901 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_acce ss.3917468901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.361122961 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 17820089 ps |
| CPU time | 2.28 seconds |
| Started | Aug 25 07:47:53 AM UTC 24 |
| Finished | Aug 25 07:47:57 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361122961 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.361122961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.840135250 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 391388542 ps |
| CPU time | 18.52 seconds |
| Started | Aug 25 07:47:57 AM UTC 24 |
| Finished | Aug 25 07:48:17 AM UTC 24 |
| Peak memory | 238172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840135250 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.840135250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1632463152 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 318964175 ps |
| CPU time | 21.7 seconds |
| Started | Aug 25 07:47:57 AM UTC 24 |
| Finished | Aug 25 07:48:20 AM UTC 24 |
| Peak memory | 237836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632463152 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_ token_digest.1632463152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3365856431 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 202981917 ps |
| CPU time | 11.25 seconds |
| Started | Aug 25 07:47:57 AM UTC 24 |
| Finished | Aug 25 07:48:09 AM UTC 24 |
| Peak memory | 237980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365856431 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_tok en_mux.3365856431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3358080788 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 593223013 ps |
| CPU time | 12.56 seconds |
| Started | Aug 25 07:47:56 AM UTC 24 |
| Finished | Aug 25 07:48:09 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358080788 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3358080788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2491545329 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 86448712 ps |
| CPU time | 5.56 seconds |
| Started | Aug 25 07:47:53 AM UTC 24 |
| Finished | Aug 25 07:48:00 AM UTC 24 |
| Peak memory | 230264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491545329 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2491545329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.641295493 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 580282273 ps |
| CPU time | 37.94 seconds |
| Started | Aug 25 07:47:53 AM UTC 24 |
| Finished | Aug 25 07:48:33 AM UTC 24 |
| Peak memory | 262840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641295493 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.641295493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2521002572 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 88377118 ps |
| CPU time | 14.19 seconds |
| Started | Aug 25 07:47:53 AM UTC 24 |
| Finished | Aug 25 07:48:09 AM UTC 24 |
| Peak memory | 261048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521002572 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2521002572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3929583206 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3794196518 ps |
| CPU time | 130.12 seconds |
| Started | Aug 25 07:47:57 AM UTC 24 |
| Finished | Aug 25 07:50:10 AM UTC 24 |
| Peak memory | 234248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3929583206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 33.lc_ctrl_stress_all.3929583206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4216039661 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 21629342 ps |
| CPU time | 1.22 seconds |
| Started | Aug 25 07:47:53 AM UTC 24 |
| Finished | Aug 25 07:47:55 AM UTC 24 |
| Peak memory | 222688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216039661 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_volatile_unlock_smoke.4216039661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.1188926869 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 21139218 ps |
| CPU time | 1.36 seconds |
| Started | Aug 25 07:48:11 AM UTC 24 |
| Finished | Aug 25 07:48:14 AM UTC 24 |
| Peak memory | 219092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188926869 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1188926869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.2029165532 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1026316278 ps |
| CPU time | 15.37 seconds |
| Started | Aug 25 07:48:03 AM UTC 24 |
| Finished | Aug 25 07:48:20 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029165532 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2029165532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3597585333 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3120774505 ps |
| CPU time | 6.37 seconds |
| Started | Aug 25 07:48:05 AM UTC 24 |
| Finished | Aug 25 07:48:13 AM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597585333 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_acce ss.3597585333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3465668853 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 23812874 ps |
| CPU time | 2.43 seconds |
| Started | Aug 25 07:48:02 AM UTC 24 |
| Finished | Aug 25 07:48:05 AM UTC 24 |
| Peak memory | 234348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465668853 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3465668853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.2273627457 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 792259268 ps |
| CPU time | 22.44 seconds |
| Started | Aug 25 07:48:05 AM UTC 24 |
| Finished | Aug 25 07:48:29 AM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273627457 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2273627457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.758048253 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 286397846 ps |
| CPU time | 13.1 seconds |
| Started | Aug 25 07:48:09 AM UTC 24 |
| Finished | Aug 25 07:48:23 AM UTC 24 |
| Peak memory | 237936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758048253 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_t oken_digest.758048253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.472351622 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 404447867 ps |
| CPU time | 16.87 seconds |
| Started | Aug 25 07:48:07 AM UTC 24 |
| Finished | Aug 25 07:48:25 AM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472351622 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_toke n_mux.472351622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.749830252 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 427694573 ps |
| CPU time | 14.22 seconds |
| Started | Aug 25 07:48:03 AM UTC 24 |
| Finished | Aug 25 07:48:19 AM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749830252 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.749830252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.4130891459 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 381650318 ps |
| CPU time | 13.73 seconds |
| Started | Aug 25 07:48:00 AM UTC 24 |
| Finished | Aug 25 07:48:15 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130891459 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4130891459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.937640392 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 273441858 ps |
| CPU time | 58.32 seconds |
| Started | Aug 25 07:48:01 AM UTC 24 |
| Finished | Aug 25 07:49:01 AM UTC 24 |
| Peak memory | 262768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937640392 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.937640392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.661598008 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 94413486 ps |
| CPU time | 9.84 seconds |
| Started | Aug 25 07:48:01 AM UTC 24 |
| Finished | Aug 25 07:48:12 AM UTC 24 |
| Peak memory | 258864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661598008 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.661598008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.4174945593 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 7213566150 ps |
| CPU time | 132.29 seconds |
| Started | Aug 25 07:48:10 AM UTC 24 |
| Finished | Aug 25 07:50:25 AM UTC 24 |
| Peak memory | 289524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4174945593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 34.lc_ctrl_stress_all.4174945593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.259701922 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2558679326 ps |
| CPU time | 128.86 seconds |
| Started | Aug 25 07:48:10 AM UTC 24 |
| Finished | Aug 25 07:50:21 AM UTC 24 |
| Peak memory | 281384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259701922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.259701922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3116974644 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 11488084 ps |
| CPU time | 1.45 seconds |
| Started | Aug 25 07:48:00 AM UTC 24 |
| Finished | Aug 25 07:48:02 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116974644 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_volatile_unlock_smoke.3116974644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1339298717 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 151672797 ps |
| CPU time | 1.62 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:48:47 AM UTC 24 |
| Peak memory | 218648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339298717 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1339298717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1414724681 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1296698967 ps |
| CPU time | 18.71 seconds |
| Started | Aug 25 07:48:16 AM UTC 24 |
| Finished | Aug 25 07:48:36 AM UTC 24 |
| Peak memory | 238004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414724681 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1414724681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.177873549 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 128531155 ps |
| CPU time | 5.56 seconds |
| Started | Aug 25 07:48:16 AM UTC 24 |
| Finished | Aug 25 07:48:23 AM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177873549 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.177873549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.3357136403 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 39937689 ps |
| CPU time | 3.19 seconds |
| Started | Aug 25 07:48:16 AM UTC 24 |
| Finished | Aug 25 07:48:20 AM UTC 24 |
| Peak memory | 231852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357136403 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3357136403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.964615937 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 247837948 ps |
| CPU time | 12.84 seconds |
| Started | Aug 25 07:48:17 AM UTC 24 |
| Finished | Aug 25 07:48:31 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964615937 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.964615937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.635680511 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3090633100 ps |
| CPU time | 19.88 seconds |
| Started | Aug 25 07:48:30 AM UTC 24 |
| Finished | Aug 25 07:48:51 AM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635680511 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_t oken_digest.635680511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.2407791578 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 344056056 ps |
| CPU time | 13.8 seconds |
| Started | Aug 25 07:48:17 AM UTC 24 |
| Finished | Aug 25 07:48:32 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407791578 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_tok en_mux.2407791578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2937751176 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 319394709 ps |
| CPU time | 12.99 seconds |
| Started | Aug 25 07:48:16 AM UTC 24 |
| Finished | Aug 25 07:48:30 AM UTC 24 |
| Peak memory | 237068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937751176 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2937751176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.1347211876 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 211241682 ps |
| CPU time | 4.09 seconds |
| Started | Aug 25 07:48:12 AM UTC 24 |
| Finished | Aug 25 07:48:17 AM UTC 24 |
| Peak memory | 226164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347211876 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1347211876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.815025126 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 221356508 ps |
| CPU time | 44.1 seconds |
| Started | Aug 25 07:48:14 AM UTC 24 |
| Finished | Aug 25 07:48:59 AM UTC 24 |
| Peak memory | 262844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815025126 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.815025126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1598272327 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 93613133 ps |
| CPU time | 12.29 seconds |
| Started | Aug 25 07:48:15 AM UTC 24 |
| Finished | Aug 25 07:48:28 AM UTC 24 |
| Peak memory | 260648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598272327 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1598272327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.1109561088 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 16918113488 ps |
| CPU time | 475.28 seconds |
| Started | Aug 25 07:48:30 AM UTC 24 |
| Finished | Aug 25 07:56:32 AM UTC 24 |
| Peak memory | 344824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1109561088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 35.lc_ctrl_stress_all.1109561088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.870996174 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 27601034 ps |
| CPU time | 1.28 seconds |
| Started | Aug 25 07:48:13 AM UTC 24 |
| Finished | Aug 25 07:48:16 AM UTC 24 |
| Peak memory | 222912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870996174 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.lc_ctrl_volatile_unlock_smoke.870996174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1181208208 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 89937242 ps |
| CPU time | 1.28 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:48:47 AM UTC 24 |
| Peak memory | 217704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181208208 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1181208208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.1233317410 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 5413417665 ps |
| CPU time | 21.09 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:49:07 AM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233317410 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1233317410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.403370782 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1933505234 ps |
| CPU time | 9.19 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:48:55 AM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403370782 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.403370782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.438015911 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 50838158 ps |
| CPU time | 2.05 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:48:48 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438015911 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.438015911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.4122956538 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1165338274 ps |
| CPU time | 22.08 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:49:08 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122956538 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4122956538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3386788114 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 363607015 ps |
| CPU time | 18.33 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:49:04 AM UTC 24 |
| Peak memory | 232124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386788114 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_ token_digest.3386788114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.1283421833 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 525573498 ps |
| CPU time | 17.73 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:49:03 AM UTC 24 |
| Peak memory | 230172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283421833 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_tok en_mux.1283421833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1742433587 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 281735943 ps |
| CPU time | 12.1 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:48:58 AM UTC 24 |
| Peak memory | 236480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742433587 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1742433587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3868277126 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 134997008 ps |
| CPU time | 2.62 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:48:48 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868277126 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3868277126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2033174889 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1688398200 ps |
| CPU time | 79.61 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:50:06 AM UTC 24 |
| Peak memory | 263032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033174889 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2033174889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.1145163737 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 80216395 ps |
| CPU time | 10.66 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:48:56 AM UTC 24 |
| Peak memory | 260936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145163737 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1145163737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1613142400 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 8853604126 ps |
| CPU time | 123.2 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:50:51 AM UTC 24 |
| Peak memory | 281212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1613142400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 36.lc_ctrl_stress_all.1613142400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1866263368 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3471210983 ps |
| CPU time | 137.26 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:51:05 AM UTC 24 |
| Peak memory | 281380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866263368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1866263368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.15088207 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 10155321 ps |
| CPU time | 1.23 seconds |
| Started | Aug 25 07:48:44 AM UTC 24 |
| Finished | Aug 25 07:48:46 AM UTC 24 |
| Peak memory | 218052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15088207 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36 .lc_ctrl_volatile_unlock_smoke.15088207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3441530625 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 58026623 ps |
| CPU time | 1.58 seconds |
| Started | Aug 25 07:48:53 AM UTC 24 |
| Finished | Aug 25 07:48:56 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441530625 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3441530625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.1531706689 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 614253875 ps |
| CPU time | 22.05 seconds |
| Started | Aug 25 07:48:51 AM UTC 24 |
| Finished | Aug 25 07:49:15 AM UTC 24 |
| Peak memory | 232284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531706689 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1531706689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.3208822502 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 331192332 ps |
| CPU time | 9.57 seconds |
| Started | Aug 25 07:48:52 AM UTC 24 |
| Finished | Aug 25 07:49:02 AM UTC 24 |
| Peak memory | 229952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208822502 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_acce ss.3208822502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.512496124 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 85413016 ps |
| CPU time | 5.16 seconds |
| Started | Aug 25 07:48:51 AM UTC 24 |
| Finished | Aug 25 07:48:58 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512496124 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.512496124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.840954568 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 555031613 ps |
| CPU time | 12.74 seconds |
| Started | Aug 25 07:48:53 AM UTC 24 |
| Finished | Aug 25 07:49:08 AM UTC 24 |
| Peak memory | 237696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840954568 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.840954568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3834887682 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 163144733 ps |
| CPU time | 13.16 seconds |
| Started | Aug 25 07:48:53 AM UTC 24 |
| Finished | Aug 25 07:49:08 AM UTC 24 |
| Peak memory | 238036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834887682 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_ token_digest.3834887682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.4074857933 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 265489972 ps |
| CPU time | 10.85 seconds |
| Started | Aug 25 07:48:53 AM UTC 24 |
| Finished | Aug 25 07:49:06 AM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074857933 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_tok en_mux.4074857933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.206811400 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 758311690 ps |
| CPU time | 14.94 seconds |
| Started | Aug 25 07:48:51 AM UTC 24 |
| Finished | Aug 25 07:49:08 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206811400 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.206811400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.3092090089 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 37312773 ps |
| CPU time | 3.44 seconds |
| Started | Aug 25 07:48:46 AM UTC 24 |
| Finished | Aug 25 07:48:50 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092090089 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3092090089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.1712048169 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 338054045 ps |
| CPU time | 34.31 seconds |
| Started | Aug 25 07:48:46 AM UTC 24 |
| Finished | Aug 25 07:49:22 AM UTC 24 |
| Peak memory | 262700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712048169 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1712048169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.2040740187 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 141578162 ps |
| CPU time | 4.33 seconds |
| Started | Aug 25 07:48:47 AM UTC 24 |
| Finished | Aug 25 07:48:53 AM UTC 24 |
| Peak memory | 238264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040740187 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2040740187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1607207865 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 4558653016 ps |
| CPU time | 210.76 seconds |
| Started | Aug 25 07:48:53 AM UTC 24 |
| Finished | Aug 25 07:52:28 AM UTC 24 |
| Peak memory | 262824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1607207865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 37.lc_ctrl_stress_all.1607207865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1890510849 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 46373589 ps |
| CPU time | 1.31 seconds |
| Started | Aug 25 07:48:46 AM UTC 24 |
| Finished | Aug 25 07:48:48 AM UTC 24 |
| Peak memory | 222636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890510849 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_volatile_unlock_smoke.1890510849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.3787662850 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 173449135 ps |
| CPU time | 1.86 seconds |
| Started | Aug 25 07:49:00 AM UTC 24 |
| Finished | Aug 25 07:49:03 AM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787662850 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3787662850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1496246342 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 2078456969 ps |
| CPU time | 21.48 seconds |
| Started | Aug 25 07:48:57 AM UTC 24 |
| Finished | Aug 25 07:49:20 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496246342 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1496246342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2504463131 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 254415339 ps |
| CPU time | 5.74 seconds |
| Started | Aug 25 07:48:58 AM UTC 24 |
| Finished | Aug 25 07:49:04 AM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504463131 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_acce ss.2504463131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.2000144834 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 303228011 ps |
| CPU time | 3.9 seconds |
| Started | Aug 25 07:48:57 AM UTC 24 |
| Finished | Aug 25 07:49:02 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000144834 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2000144834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2382752192 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 298474195 ps |
| CPU time | 15.5 seconds |
| Started | Aug 25 07:48:58 AM UTC 24 |
| Finished | Aug 25 07:49:14 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382752192 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2382752192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.460768217 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1421483056 ps |
| CPU time | 15.5 seconds |
| Started | Aug 25 07:48:59 AM UTC 24 |
| Finished | Aug 25 07:49:16 AM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460768217 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_t oken_digest.460768217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3963692651 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 299820234 ps |
| CPU time | 15.29 seconds |
| Started | Aug 25 07:48:59 AM UTC 24 |
| Finished | Aug 25 07:49:15 AM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963692651 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_tok en_mux.3963692651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.1719387534 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1292286976 ps |
| CPU time | 12.24 seconds |
| Started | Aug 25 07:48:58 AM UTC 24 |
| Finished | Aug 25 07:49:11 AM UTC 24 |
| Peak memory | 232284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719387534 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1719387534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1973366269 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 31014355 ps |
| CPU time | 1.68 seconds |
| Started | Aug 25 07:48:53 AM UTC 24 |
| Finished | Aug 25 07:48:57 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973366269 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1973366269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2236018166 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1257488770 ps |
| CPU time | 66.49 seconds |
| Started | Aug 25 07:48:55 AM UTC 24 |
| Finished | Aug 25 07:50:03 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236018166 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2236018166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.451906527 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 197157066 ps |
| CPU time | 15.66 seconds |
| Started | Aug 25 07:48:56 AM UTC 24 |
| Finished | Aug 25 07:49:13 AM UTC 24 |
| Peak memory | 263152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451906527 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.451906527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.1788435152 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 8078531481 ps |
| CPU time | 123.03 seconds |
| Started | Aug 25 07:48:59 AM UTC 24 |
| Finished | Aug 25 07:51:05 AM UTC 24 |
| Peak memory | 238244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1788435152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 38.lc_ctrl_stress_all.1788435152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.274154667 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 18355581288 ps |
| CPU time | 117.39 seconds |
| Started | Aug 25 07:48:59 AM UTC 24 |
| Finished | Aug 25 07:50:59 AM UTC 24 |
| Peak memory | 291952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274154667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.274154667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.327416569 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 11167806 ps |
| CPU time | 1.27 seconds |
| Started | Aug 25 07:48:54 AM UTC 24 |
| Finished | Aug 25 07:48:56 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327416569 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.lc_ctrl_volatile_unlock_smoke.327416569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2087649109 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 77816305 ps |
| CPU time | 1.4 seconds |
| Started | Aug 25 07:49:14 AM UTC 24 |
| Finished | Aug 25 07:49:17 AM UTC 24 |
| Peak memory | 218904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087649109 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2087649109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.2547583246 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 491708657 ps |
| CPU time | 13.1 seconds |
| Started | Aug 25 07:49:05 AM UTC 24 |
| Finished | Aug 25 07:49:20 AM UTC 24 |
| Peak memory | 237840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547583246 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2547583246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.1357091107 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2256936835 ps |
| CPU time | 8.24 seconds |
| Started | Aug 25 07:49:06 AM UTC 24 |
| Finished | Aug 25 07:49:16 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357091107 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_acce ss.1357091107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.3095908418 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 45581264 ps |
| CPU time | 2.27 seconds |
| Started | Aug 25 07:49:05 AM UTC 24 |
| Finished | Aug 25 07:49:09 AM UTC 24 |
| Peak memory | 232300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095908418 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3095908418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.2397879511 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1387070531 ps |
| CPU time | 20.49 seconds |
| Started | Aug 25 07:49:08 AM UTC 24 |
| Finished | Aug 25 07:49:30 AM UTC 24 |
| Peak memory | 237928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397879511 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2397879511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.1478406162 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 6990592290 ps |
| CPU time | 16.26 seconds |
| Started | Aug 25 07:49:08 AM UTC 24 |
| Finished | Aug 25 07:49:26 AM UTC 24 |
| Peak memory | 237872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478406162 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_ token_digest.1478406162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.103418479 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 699335256 ps |
| CPU time | 12.8 seconds |
| Started | Aug 25 07:49:08 AM UTC 24 |
| Finished | Aug 25 07:49:22 AM UTC 24 |
| Peak memory | 237920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103418479 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_toke n_mux.103418479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.666652589 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 292303680 ps |
| CPU time | 16.58 seconds |
| Started | Aug 25 07:49:05 AM UTC 24 |
| Finished | Aug 25 07:49:23 AM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666652589 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.666652589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3033491783 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 159391450 ps |
| CPU time | 3.53 seconds |
| Started | Aug 25 07:49:02 AM UTC 24 |
| Finished | Aug 25 07:49:07 AM UTC 24 |
| Peak memory | 230072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033491783 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3033491783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.993158138 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2032530571 ps |
| CPU time | 53.47 seconds |
| Started | Aug 25 07:49:04 AM UTC 24 |
| Finished | Aug 25 07:49:59 AM UTC 24 |
| Peak memory | 260792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993158138 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.993158138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.694453073 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 166677429 ps |
| CPU time | 6.99 seconds |
| Started | Aug 25 07:49:04 AM UTC 24 |
| Finished | Aug 25 07:49:12 AM UTC 24 |
| Peak memory | 238196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694453073 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.694453073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.838783356 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 36519539777 ps |
| CPU time | 352.66 seconds |
| Started | Aug 25 07:49:08 AM UTC 24 |
| Finished | Aug 25 07:55:06 AM UTC 24 |
| Peak memory | 287476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=838783356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 39.lc_ctrl_stress_all.838783356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3437054199 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 6183958332 ps |
| CPU time | 80.83 seconds |
| Started | Aug 25 07:49:08 AM UTC 24 |
| Finished | Aug 25 07:50:32 AM UTC 24 |
| Peak memory | 285444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437054199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3437054199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1322405525 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 12485252 ps |
| CPU time | 1.6 seconds |
| Started | Aug 25 07:49:03 AM UTC 24 |
| Finished | Aug 25 07:49:06 AM UTC 24 |
| Peak memory | 220660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322405525 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_volatile_unlock_smoke.1322405525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.4035075767 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 14885371 ps |
| CPU time | 1.39 seconds |
| Started | Aug 25 07:41:00 AM UTC 24 |
| Finished | Aug 25 07:41:03 AM UTC 24 |
| Peak memory | 217704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035075767 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.4035075767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2273677927 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 19830897 ps |
| CPU time | 1.46 seconds |
| Started | Aug 25 07:40:44 AM UTC 24 |
| Finished | Aug 25 07:40:47 AM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273677927 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2273677927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.86119367 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7829803175 ps |
| CPU time | 23.72 seconds |
| Started | Aug 25 07:40:43 AM UTC 24 |
| Finished | Aug 25 07:41:08 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86119367 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.86119367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.3017863404 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1504100026 ps |
| CPU time | 10.44 seconds |
| Started | Aug 25 07:40:49 AM UTC 24 |
| Finished | Aug 25 07:41:00 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017863404 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3017863404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.682084857 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 15305325877 ps |
| CPU time | 159.61 seconds |
| Started | Aug 25 07:40:49 AM UTC 24 |
| Finished | Aug 25 07:43:31 AM UTC 24 |
| Peak memory | 237984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682084857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j tag_errors.682084857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2861147893 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 377961857 ps |
| CPU time | 11.57 seconds |
| Started | Aug 25 07:40:50 AM UTC 24 |
| Finished | Aug 25 07:41:03 AM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861147893 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_pri ority.2861147893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2849595301 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1278236107 ps |
| CPU time | 9.59 seconds |
| Started | Aug 25 07:40:47 AM UTC 24 |
| Finished | Aug 25 07:40:58 AM UTC 24 |
| Peak memory | 236164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849595301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct rl_jtag_prog_failure.2849595301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3937713400 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 6860815250 ps |
| CPU time | 31.12 seconds |
| Started | Aug 25 07:40:52 AM UTC 24 |
| Finished | Aug 25 07:41:24 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937713400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.l c_ctrl_jtag_regwen_during_op.3937713400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.558798721 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 600535864 ps |
| CPU time | 3.18 seconds |
| Started | Aug 25 07:40:46 AM UTC 24 |
| Finished | Aug 25 07:40:50 AM UTC 24 |
| Peak memory | 230012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558798721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ smoke.558798721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.91985618 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 737768315 ps |
| CPU time | 36.73 seconds |
| Started | Aug 25 07:40:47 AM UTC 24 |
| Finished | Aug 25 07:41:26 AM UTC 24 |
| Peak memory | 262744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91985618 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ ctrl_jtag_state_post_trans.91985618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.555008506 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 74987623 ps |
| CPU time | 5.45 seconds |
| Started | Aug 25 07:40:41 AM UTC 24 |
| Finished | Aug 25 07:40:48 AM UTC 24 |
| Peak memory | 232488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555008506 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.555008506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.544340926 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 999813788 ps |
| CPU time | 19.94 seconds |
| Started | Aug 25 07:40:43 AM UTC 24 |
| Finished | Aug 25 07:41:04 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544340926 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.544340926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2689361203 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 418452991 ps |
| CPU time | 87.22 seconds |
| Started | Aug 25 07:40:57 AM UTC 24 |
| Finished | Aug 25 07:42:26 AM UTC 24 |
| Peak memory | 292184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689361203 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2689361203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.875945792 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 967809250 ps |
| CPU time | 36.24 seconds |
| Started | Aug 25 07:40:54 AM UTC 24 |
| Finished | Aug 25 07:41:32 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875945792 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.875945792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.4225606668 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 227713090 ps |
| CPU time | 16.27 seconds |
| Started | Aug 25 07:40:55 AM UTC 24 |
| Finished | Aug 25 07:41:13 AM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225606668 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_t oken_digest.4225606668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3708346456 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 597153943 ps |
| CPU time | 12.5 seconds |
| Started | Aug 25 07:40:54 AM UTC 24 |
| Finished | Aug 25 07:41:08 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708346456 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_toke n_mux.3708346456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.73507560 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 496620941 ps |
| CPU time | 16.52 seconds |
| Started | Aug 25 07:40:43 AM UTC 24 |
| Finished | Aug 25 07:41:01 AM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73507560 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.73507560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.1847004831 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 26691552 ps |
| CPU time | 1.98 seconds |
| Started | Aug 25 07:40:38 AM UTC 24 |
| Finished | Aug 25 07:40:42 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847004831 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1847004831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2278240718 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 189012089 ps |
| CPU time | 42.15 seconds |
| Started | Aug 25 07:40:39 AM UTC 24 |
| Finished | Aug 25 07:41:23 AM UTC 24 |
| Peak memory | 260720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278240718 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2278240718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.502290816 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2868147859 ps |
| CPU time | 135.47 seconds |
| Started | Aug 25 07:40:57 AM UTC 24 |
| Finished | Aug 25 07:43:15 AM UTC 24 |
| Peak memory | 281720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502290816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.502290816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3600513602 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 14544886 ps |
| CPU time | 1.42 seconds |
| Started | Aug 25 07:40:39 AM UTC 24 |
| Finished | Aug 25 07:40:42 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600513602 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_volatile_unlock_smoke.3600513602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.955070299 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 11216438 ps |
| CPU time | 1.32 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:49:20 AM UTC 24 |
| Peak memory | 217708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955070299 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.955070299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.1086694687 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 288107641 ps |
| CPU time | 19.3 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:49:37 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086694687 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1086694687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.2039363127 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1477266920 ps |
| CPU time | 3.41 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:49:21 AM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039363127 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_acce ss.2039363127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2875999459 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 137099342 ps |
| CPU time | 2.8 seconds |
| Started | Aug 25 07:49:14 AM UTC 24 |
| Finished | Aug 25 07:49:18 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875999459 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2875999459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.3664451156 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2086175696 ps |
| CPU time | 23.85 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:49:42 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664451156 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3664451156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.1510681285 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1446641883 ps |
| CPU time | 23.37 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:49:42 AM UTC 24 |
| Peak memory | 232120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510681285 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_ token_digest.1510681285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.931616004 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 171080873 ps |
| CPU time | 9.54 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:49:28 AM UTC 24 |
| Peak memory | 230164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931616004 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_toke n_mux.931616004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.2126693686 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 2671491688 ps |
| CPU time | 27.92 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:49:46 AM UTC 24 |
| Peak memory | 232544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126693686 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2126693686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.3982535241 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 274429651 ps |
| CPU time | 5.55 seconds |
| Started | Aug 25 07:49:14 AM UTC 24 |
| Finished | Aug 25 07:49:21 AM UTC 24 |
| Peak memory | 230264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982535241 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3982535241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.3139108032 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 626741387 ps |
| CPU time | 57.16 seconds |
| Started | Aug 25 07:49:14 AM UTC 24 |
| Finished | Aug 25 07:50:13 AM UTC 24 |
| Peak memory | 260716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139108032 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3139108032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.4040514366 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 87090433 ps |
| CPU time | 15.17 seconds |
| Started | Aug 25 07:49:14 AM UTC 24 |
| Finished | Aug 25 07:49:31 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040514366 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.4040514366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.981905424 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 5381760307 ps |
| CPU time | 191.41 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:52:32 AM UTC 24 |
| Peak memory | 281256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=981905424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 40.lc_ctrl_stress_all.981905424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1214617132 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 13165763 ps |
| CPU time | 1.51 seconds |
| Started | Aug 25 07:49:14 AM UTC 24 |
| Finished | Aug 25 07:49:17 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214617132 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_volatile_unlock_smoke.1214617132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.1652561799 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 28697019 ps |
| CPU time | 2.1 seconds |
| Started | Aug 25 07:49:23 AM UTC 24 |
| Finished | Aug 25 07:49:27 AM UTC 24 |
| Peak memory | 219268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652561799 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1652561799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.2108205713 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1775890054 ps |
| CPU time | 23.61 seconds |
| Started | Aug 25 07:49:21 AM UTC 24 |
| Finished | Aug 25 07:49:45 AM UTC 24 |
| Peak memory | 237840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108205713 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2108205713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.451957945 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 141037016 ps |
| CPU time | 3.46 seconds |
| Started | Aug 25 07:49:22 AM UTC 24 |
| Finished | Aug 25 07:49:26 AM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451957945 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.451957945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.3221951033 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 30115251 ps |
| CPU time | 2.31 seconds |
| Started | Aug 25 07:49:19 AM UTC 24 |
| Finished | Aug 25 07:49:23 AM UTC 24 |
| Peak memory | 234188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221951033 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3221951033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2122064590 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 360499488 ps |
| CPU time | 16.44 seconds |
| Started | Aug 25 07:49:22 AM UTC 24 |
| Finished | Aug 25 07:49:39 AM UTC 24 |
| Peak memory | 237856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122064590 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2122064590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2804950299 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 725280855 ps |
| CPU time | 21.92 seconds |
| Started | Aug 25 07:49:22 AM UTC 24 |
| Finished | Aug 25 07:49:45 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804950299 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_ token_digest.2804950299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3359871159 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 277878427 ps |
| CPU time | 15.08 seconds |
| Started | Aug 25 07:49:22 AM UTC 24 |
| Finished | Aug 25 07:49:38 AM UTC 24 |
| Peak memory | 237860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359871159 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_tok en_mux.3359871159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.2834008327 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2324247955 ps |
| CPU time | 11.55 seconds |
| Started | Aug 25 07:49:21 AM UTC 24 |
| Finished | Aug 25 07:49:33 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834008327 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2834008327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2028387246 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 29704693 ps |
| CPU time | 3.19 seconds |
| Started | Aug 25 07:49:17 AM UTC 24 |
| Finished | Aug 25 07:49:22 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028387246 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2028387246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2343449168 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 259337065 ps |
| CPU time | 34.72 seconds |
| Started | Aug 25 07:49:18 AM UTC 24 |
| Finished | Aug 25 07:49:54 AM UTC 24 |
| Peak memory | 262524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343449168 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2343449168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.548570035 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 70151031 ps |
| CPU time | 10.01 seconds |
| Started | Aug 25 07:49:18 AM UTC 24 |
| Finished | Aug 25 07:49:30 AM UTC 24 |
| Peak memory | 256596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548570035 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.548570035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2852597040 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2686062156 ps |
| CPU time | 127.24 seconds |
| Started | Aug 25 07:49:23 AM UTC 24 |
| Finished | Aug 25 07:51:34 AM UTC 24 |
| Peak memory | 283312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2852597040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 41.lc_ctrl_stress_all.2852597040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.486347040 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 54743320 ps |
| CPU time | 1.22 seconds |
| Started | Aug 25 07:49:18 AM UTC 24 |
| Finished | Aug 25 07:49:21 AM UTC 24 |
| Peak memory | 220448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486347040 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.lc_ctrl_volatile_unlock_smoke.486347040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3010434736 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 26147965 ps |
| CPU time | 1.68 seconds |
| Started | Aug 25 07:49:41 AM UTC 24 |
| Finished | Aug 25 07:49:44 AM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010434736 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3010434736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.3632491451 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 360605268 ps |
| CPU time | 19.63 seconds |
| Started | Aug 25 07:49:28 AM UTC 24 |
| Finished | Aug 25 07:49:49 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632491451 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3632491451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.47833029 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 229086771 ps |
| CPU time | 6.61 seconds |
| Started | Aug 25 07:49:31 AM UTC 24 |
| Finished | Aug 25 07:49:39 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47833029 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.47833029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.3241695586 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 107623618 ps |
| CPU time | 4.1 seconds |
| Started | Aug 25 07:49:28 AM UTC 24 |
| Finished | Aug 25 07:49:33 AM UTC 24 |
| Peak memory | 234264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241695586 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3241695586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1138716967 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1291455585 ps |
| CPU time | 17.44 seconds |
| Started | Aug 25 07:49:31 AM UTC 24 |
| Finished | Aug 25 07:49:50 AM UTC 24 |
| Peak memory | 238248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138716967 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1138716967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.656085235 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 2605437446 ps |
| CPU time | 23.87 seconds |
| Started | Aug 25 07:49:41 AM UTC 24 |
| Finished | Aug 25 07:50:06 AM UTC 24 |
| Peak memory | 238316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656085235 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_t oken_digest.656085235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1849854306 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1278053263 ps |
| CPU time | 13.99 seconds |
| Started | Aug 25 07:49:31 AM UTC 24 |
| Finished | Aug 25 07:49:47 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849854306 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_tok en_mux.1849854306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3777481564 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1206104835 ps |
| CPU time | 16.6 seconds |
| Started | Aug 25 07:49:29 AM UTC 24 |
| Finished | Aug 25 07:49:47 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777481564 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3777481564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1623250522 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 2824078962 ps |
| CPU time | 14.85 seconds |
| Started | Aug 25 07:49:23 AM UTC 24 |
| Finished | Aug 25 07:49:40 AM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623250522 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1623250522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.21255918 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 176722752 ps |
| CPU time | 36.93 seconds |
| Started | Aug 25 07:49:27 AM UTC 24 |
| Finished | Aug 25 07:50:05 AM UTC 24 |
| Peak memory | 260876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21255918 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.21255918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.3407600432 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 218971105 ps |
| CPU time | 5.14 seconds |
| Started | Aug 25 07:49:28 AM UTC 24 |
| Finished | Aug 25 07:49:34 AM UTC 24 |
| Peak memory | 236988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407600432 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3407600432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1578103846 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 12608906015 ps |
| CPU time | 126.41 seconds |
| Started | Aug 25 07:49:41 AM UTC 24 |
| Finished | Aug 25 07:51:50 AM UTC 24 |
| Peak memory | 291920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1578103846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 42.lc_ctrl_stress_all.1578103846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.1758043430 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 1175732519 ps |
| CPU time | 38.51 seconds |
| Started | Aug 25 07:49:41 AM UTC 24 |
| Finished | Aug 25 07:50:21 AM UTC 24 |
| Peak memory | 240392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758043430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.1758043430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3634769057 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 42562126 ps |
| CPU time | 1.23 seconds |
| Started | Aug 25 07:49:24 AM UTC 24 |
| Finished | Aug 25 07:49:27 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634769057 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_volatile_unlock_smoke.3634769057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.1704477963 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 36270206 ps |
| CPU time | 1.73 seconds |
| Started | Aug 25 07:49:57 AM UTC 24 |
| Finished | Aug 25 07:49:59 AM UTC 24 |
| Peak memory | 218916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704477963 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1704477963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1614967623 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1991721467 ps |
| CPU time | 19.79 seconds |
| Started | Aug 25 07:49:53 AM UTC 24 |
| Finished | Aug 25 07:50:15 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614967623 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1614967623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.280022242 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 537483542 ps |
| CPU time | 3.55 seconds |
| Started | Aug 25 07:49:54 AM UTC 24 |
| Finished | Aug 25 07:49:58 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280022242 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.280022242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.1590088640 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 881856521 ps |
| CPU time | 2.98 seconds |
| Started | Aug 25 07:49:53 AM UTC 24 |
| Finished | Aug 25 07:49:58 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590088640 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1590088640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.2477455858 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 293007561 ps |
| CPU time | 19.13 seconds |
| Started | Aug 25 07:49:56 AM UTC 24 |
| Finished | Aug 25 07:50:17 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477455858 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2477455858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3402597912 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 524528156 ps |
| CPU time | 16.64 seconds |
| Started | Aug 25 07:49:56 AM UTC 24 |
| Finished | Aug 25 07:50:14 AM UTC 24 |
| Peak memory | 237920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402597912 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_ token_digest.3402597912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.2698768413 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 184637399 ps |
| CPU time | 12.11 seconds |
| Started | Aug 25 07:49:56 AM UTC 24 |
| Finished | Aug 25 07:50:10 AM UTC 24 |
| Peak memory | 237844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698768413 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_tok en_mux.2698768413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1263231716 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1141817478 ps |
| CPU time | 15.01 seconds |
| Started | Aug 25 07:49:54 AM UTC 24 |
| Finished | Aug 25 07:50:10 AM UTC 24 |
| Peak memory | 236936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263231716 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1263231716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.2651036277 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 196884771 ps |
| CPU time | 3.08 seconds |
| Started | Aug 25 07:49:53 AM UTC 24 |
| Finished | Aug 25 07:49:58 AM UTC 24 |
| Peak memory | 225900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651036277 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2651036277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.1529659980 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 263648799 ps |
| CPU time | 61.18 seconds |
| Started | Aug 25 07:49:53 AM UTC 24 |
| Finished | Aug 25 07:50:56 AM UTC 24 |
| Peak memory | 262772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529659980 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1529659980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.1072711844 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 247632862 ps |
| CPU time | 3.6 seconds |
| Started | Aug 25 07:49:53 AM UTC 24 |
| Finished | Aug 25 07:49:58 AM UTC 24 |
| Peak memory | 234520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072711844 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1072711844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.722723002 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2863833104 ps |
| CPU time | 32.28 seconds |
| Started | Aug 25 07:49:56 AM UTC 24 |
| Finished | Aug 25 07:50:30 AM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=722723002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 43.lc_ctrl_stress_all.722723002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2646618682 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 13037971 ps |
| CPU time | 1.52 seconds |
| Started | Aug 25 07:49:53 AM UTC 24 |
| Finished | Aug 25 07:49:56 AM UTC 24 |
| Peak memory | 222616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646618682 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_volatile_unlock_smoke.2646618682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.2597265340 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 51013342 ps |
| CPU time | 1.42 seconds |
| Started | Aug 25 07:50:00 AM UTC 24 |
| Finished | Aug 25 07:50:03 AM UTC 24 |
| Peak memory | 219092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597265340 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2597265340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3636056279 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 735043530 ps |
| CPU time | 19.53 seconds |
| Started | Aug 25 07:49:57 AM UTC 24 |
| Finished | Aug 25 07:50:18 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636056279 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3636056279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.3533199896 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 528930509 ps |
| CPU time | 12.27 seconds |
| Started | Aug 25 07:49:58 AM UTC 24 |
| Finished | Aug 25 07:50:11 AM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533199896 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_acce ss.3533199896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1873331415 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 182332325 ps |
| CPU time | 3.66 seconds |
| Started | Aug 25 07:49:57 AM UTC 24 |
| Finished | Aug 25 07:50:02 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873331415 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1873331415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.1693553361 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 825088644 ps |
| CPU time | 13.19 seconds |
| Started | Aug 25 07:49:59 AM UTC 24 |
| Finished | Aug 25 07:50:13 AM UTC 24 |
| Peak memory | 238188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693553361 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1693553361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2999376708 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 533177798 ps |
| CPU time | 12.37 seconds |
| Started | Aug 25 07:49:59 AM UTC 24 |
| Finished | Aug 25 07:50:13 AM UTC 24 |
| Peak memory | 237872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999376708 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_ token_digest.2999376708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.4088614144 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 802411921 ps |
| CPU time | 17.05 seconds |
| Started | Aug 25 07:49:59 AM UTC 24 |
| Finished | Aug 25 07:50:17 AM UTC 24 |
| Peak memory | 232564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088614144 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_tok en_mux.4088614144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.1973648528 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1892075457 ps |
| CPU time | 14.86 seconds |
| Started | Aug 25 07:49:57 AM UTC 24 |
| Finished | Aug 25 07:50:13 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973648528 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1973648528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.4158582427 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 40885093 ps |
| CPU time | 3.08 seconds |
| Started | Aug 25 07:49:57 AM UTC 24 |
| Finished | Aug 25 07:50:01 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158582427 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4158582427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.4284267923 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 229552567 ps |
| CPU time | 48.68 seconds |
| Started | Aug 25 07:49:57 AM UTC 24 |
| Finished | Aug 25 07:50:47 AM UTC 24 |
| Peak memory | 258768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284267923 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.4284267923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.3381201934 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 60964057 ps |
| CPU time | 13.89 seconds |
| Started | Aug 25 07:49:57 AM UTC 24 |
| Finished | Aug 25 07:50:12 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381201934 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3381201934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3418543020 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 4766820726 ps |
| CPU time | 156.11 seconds |
| Started | Aug 25 07:50:00 AM UTC 24 |
| Finished | Aug 25 07:52:39 AM UTC 24 |
| Peak memory | 281672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3418543020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 44.lc_ctrl_stress_all.3418543020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1747659060 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 41217552 ps |
| CPU time | 1.41 seconds |
| Started | Aug 25 07:49:57 AM UTC 24 |
| Finished | Aug 25 07:49:59 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747659060 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_volatile_unlock_smoke.1747659060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2023991177 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 14271210 ps |
| CPU time | 1.13 seconds |
| Started | Aug 25 07:50:12 AM UTC 24 |
| Finished | Aug 25 07:50:14 AM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023991177 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2023991177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.4067997136 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 693102538 ps |
| CPU time | 17.32 seconds |
| Started | Aug 25 07:50:05 AM UTC 24 |
| Finished | Aug 25 07:50:24 AM UTC 24 |
| Peak memory | 238164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067997136 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4067997136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1770836618 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 679823998 ps |
| CPU time | 11.3 seconds |
| Started | Aug 25 07:50:07 AM UTC 24 |
| Finished | Aug 25 07:50:19 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770836618 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_acce ss.1770836618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1244565994 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 54469631 ps |
| CPU time | 3.71 seconds |
| Started | Aug 25 07:50:04 AM UTC 24 |
| Finished | Aug 25 07:50:09 AM UTC 24 |
| Peak memory | 236664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244565994 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1244565994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.1802600066 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2367374634 ps |
| CPU time | 18.85 seconds |
| Started | Aug 25 07:50:07 AM UTC 24 |
| Finished | Aug 25 07:50:27 AM UTC 24 |
| Peak memory | 238252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802600066 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1802600066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1950231477 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 299165674 ps |
| CPU time | 13.15 seconds |
| Started | Aug 25 07:50:10 AM UTC 24 |
| Finished | Aug 25 07:50:24 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950231477 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_ token_digest.1950231477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.844265666 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 3043832662 ps |
| CPU time | 26.94 seconds |
| Started | Aug 25 07:50:08 AM UTC 24 |
| Finished | Aug 25 07:50:36 AM UTC 24 |
| Peak memory | 237984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844265666 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_toke n_mux.844265666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2167417322 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 260755054 ps |
| CPU time | 11.72 seconds |
| Started | Aug 25 07:50:07 AM UTC 24 |
| Finished | Aug 25 07:50:20 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167417322 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2167417322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3241554696 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 49266102 ps |
| CPU time | 3.4 seconds |
| Started | Aug 25 07:50:02 AM UTC 24 |
| Finished | Aug 25 07:50:07 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241554696 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3241554696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1391055791 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 160371195 ps |
| CPU time | 38.41 seconds |
| Started | Aug 25 07:50:03 AM UTC 24 |
| Finished | Aug 25 07:50:43 AM UTC 24 |
| Peak memory | 261052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391055791 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1391055791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.1423914844 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 260814359 ps |
| CPU time | 13.24 seconds |
| Started | Aug 25 07:50:04 AM UTC 24 |
| Finished | Aug 25 07:50:19 AM UTC 24 |
| Peak memory | 262668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423914844 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1423914844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1892705141 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 19909698755 ps |
| CPU time | 85.11 seconds |
| Started | Aug 25 07:50:11 AM UTC 24 |
| Finished | Aug 25 07:51:39 AM UTC 24 |
| Peak memory | 287564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1892705141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 45.lc_ctrl_stress_all.1892705141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.275063356 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 13189723 ps |
| CPU time | 1.3 seconds |
| Started | Aug 25 07:50:02 AM UTC 24 |
| Finished | Aug 25 07:50:04 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275063356 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.lc_ctrl_volatile_unlock_smoke.275063356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.676602786 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 51155217 ps |
| CPU time | 1.48 seconds |
| Started | Aug 25 07:50:17 AM UTC 24 |
| Finished | Aug 25 07:50:20 AM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676602786 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.676602786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.594145505 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 198966763 ps |
| CPU time | 15.67 seconds |
| Started | Aug 25 07:50:15 AM UTC 24 |
| Finished | Aug 25 07:50:32 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594145505 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.594145505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3261412308 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 4691955844 ps |
| CPU time | 40.93 seconds |
| Started | Aug 25 07:50:15 AM UTC 24 |
| Finished | Aug 25 07:50:57 AM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261412308 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_acce ss.3261412308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.3473258074 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 73628976 ps |
| CPU time | 4.19 seconds |
| Started | Aug 25 07:50:15 AM UTC 24 |
| Finished | Aug 25 07:50:20 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473258074 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3473258074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.3695539016 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1649454105 ps |
| CPU time | 26.02 seconds |
| Started | Aug 25 07:50:15 AM UTC 24 |
| Finished | Aug 25 07:50:42 AM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695539016 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3695539016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.3624962275 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1597549701 ps |
| CPU time | 14.44 seconds |
| Started | Aug 25 07:50:16 AM UTC 24 |
| Finished | Aug 25 07:50:32 AM UTC 24 |
| Peak memory | 238168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624962275 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_ token_digest.3624962275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.589330032 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 636526463 ps |
| CPU time | 14.63 seconds |
| Started | Aug 25 07:50:16 AM UTC 24 |
| Finished | Aug 25 07:50:32 AM UTC 24 |
| Peak memory | 238172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589330032 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_toke n_mux.589330032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.2011763481 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 233176332 ps |
| CPU time | 11.31 seconds |
| Started | Aug 25 07:50:15 AM UTC 24 |
| Finished | Aug 25 07:50:27 AM UTC 24 |
| Peak memory | 237644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011763481 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2011763481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.2216433601 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 101838751 ps |
| CPU time | 1.58 seconds |
| Started | Aug 25 07:50:13 AM UTC 24 |
| Finished | Aug 25 07:50:16 AM UTC 24 |
| Peak memory | 229032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216433601 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2216433601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.4088343698 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 232317307 ps |
| CPU time | 47.17 seconds |
| Started | Aug 25 07:50:13 AM UTC 24 |
| Finished | Aug 25 07:51:02 AM UTC 24 |
| Peak memory | 263100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088343698 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4088343698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2158314309 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 173423993 ps |
| CPU time | 5.26 seconds |
| Started | Aug 25 07:50:14 AM UTC 24 |
| Finished | Aug 25 07:50:21 AM UTC 24 |
| Peak memory | 232384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158314309 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2158314309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3500701609 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 4816793830 ps |
| CPU time | 266.25 seconds |
| Started | Aug 25 07:50:16 AM UTC 24 |
| Finished | Aug 25 07:54:47 AM UTC 24 |
| Peak memory | 293628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3500701609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 46.lc_ctrl_stress_all.3500701609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3988852567 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 9852158010 ps |
| CPU time | 148.89 seconds |
| Started | Aug 25 07:50:16 AM UTC 24 |
| Finished | Aug 25 07:52:48 AM UTC 24 |
| Peak memory | 289932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988852567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3988852567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3666519186 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 29647798 ps |
| CPU time | 1.43 seconds |
| Started | Aug 25 07:50:13 AM UTC 24 |
| Finished | Aug 25 07:50:15 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666519186 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_volatile_unlock_smoke.3666519186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.950806446 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 16777975 ps |
| CPU time | 1.4 seconds |
| Started | Aug 25 07:50:25 AM UTC 24 |
| Finished | Aug 25 07:50:28 AM UTC 24 |
| Peak memory | 217104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950806446 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.950806446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1397287637 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1404810024 ps |
| CPU time | 19.74 seconds |
| Started | Aug 25 07:50:21 AM UTC 24 |
| Finished | Aug 25 07:50:42 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397287637 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1397287637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.527083203 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1890959614 ps |
| CPU time | 8.3 seconds |
| Started | Aug 25 07:50:23 AM UTC 24 |
| Finished | Aug 25 07:50:32 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527083203 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.527083203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.701226810 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 74485313 ps |
| CPU time | 4.39 seconds |
| Started | Aug 25 07:50:21 AM UTC 24 |
| Finished | Aug 25 07:50:27 AM UTC 24 |
| Peak memory | 236304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701226810 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.701226810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.4042612634 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1321915987 ps |
| CPU time | 30.05 seconds |
| Started | Aug 25 07:50:23 AM UTC 24 |
| Finished | Aug 25 07:50:55 AM UTC 24 |
| Peak memory | 238124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042612634 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.4042612634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3502678074 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 542146252 ps |
| CPU time | 18.09 seconds |
| Started | Aug 25 07:50:23 AM UTC 24 |
| Finished | Aug 25 07:50:43 AM UTC 24 |
| Peak memory | 238168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502678074 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_ token_digest.3502678074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1061801603 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 893473619 ps |
| CPU time | 16.76 seconds |
| Started | Aug 25 07:50:23 AM UTC 24 |
| Finished | Aug 25 07:50:41 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061801603 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_tok en_mux.1061801603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2874291341 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 358351650 ps |
| CPU time | 17.28 seconds |
| Started | Aug 25 07:50:21 AM UTC 24 |
| Finished | Aug 25 07:50:40 AM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874291341 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2874291341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.2085227519 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 60747324 ps |
| CPU time | 4.53 seconds |
| Started | Aug 25 07:50:19 AM UTC 24 |
| Finished | Aug 25 07:50:25 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085227519 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2085227519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1955409923 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1025321873 ps |
| CPU time | 40.18 seconds |
| Started | Aug 25 07:50:20 AM UTC 24 |
| Finished | Aug 25 07:51:02 AM UTC 24 |
| Peak memory | 262768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955409923 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1955409923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3510213949 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 599803376 ps |
| CPU time | 12.2 seconds |
| Started | Aug 25 07:50:20 AM UTC 24 |
| Finished | Aug 25 07:50:33 AM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510213949 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3510213949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.3747963590 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 24473947479 ps |
| CPU time | 147.73 seconds |
| Started | Aug 25 07:50:23 AM UTC 24 |
| Finished | Aug 25 07:52:54 AM UTC 24 |
| Peak memory | 262780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3747963590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 47.lc_ctrl_stress_all.3747963590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1970722196 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2131430785 ps |
| CPU time | 106.54 seconds |
| Started | Aug 25 07:50:25 AM UTC 24 |
| Finished | Aug 25 07:52:14 AM UTC 24 |
| Peak memory | 283548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970722196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1970722196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2777756349 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 15267533 ps |
| CPU time | 1.35 seconds |
| Started | Aug 25 07:50:19 AM UTC 24 |
| Finished | Aug 25 07:50:22 AM UTC 24 |
| Peak memory | 220660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777756349 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_volatile_unlock_smoke.2777756349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1315849566 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 61162232 ps |
| CPU time | 1.62 seconds |
| Started | Aug 25 07:50:33 AM UTC 24 |
| Finished | Aug 25 07:50:36 AM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315849566 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1315849566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.4205213633 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1521237992 ps |
| CPU time | 23.97 seconds |
| Started | Aug 25 07:50:29 AM UTC 24 |
| Finished | Aug 25 07:50:55 AM UTC 24 |
| Peak memory | 237776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205213633 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4205213633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2583133082 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 174267582 ps |
| CPU time | 4.86 seconds |
| Started | Aug 25 07:50:30 AM UTC 24 |
| Finished | Aug 25 07:50:36 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583133082 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_acce ss.2583133082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.2548689708 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 63111859 ps |
| CPU time | 3.98 seconds |
| Started | Aug 25 07:50:28 AM UTC 24 |
| Finished | Aug 25 07:50:33 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548689708 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2548689708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.3539743875 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 307819900 ps |
| CPU time | 21.1 seconds |
| Started | Aug 25 07:50:31 AM UTC 24 |
| Finished | Aug 25 07:50:54 AM UTC 24 |
| Peak memory | 237788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539743875 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3539743875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.615529396 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2547995775 ps |
| CPU time | 16.16 seconds |
| Started | Aug 25 07:50:33 AM UTC 24 |
| Finished | Aug 25 07:50:50 AM UTC 24 |
| Peak memory | 238252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615529396 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_t oken_digest.615529396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1082274962 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2525831239 ps |
| CPU time | 21.48 seconds |
| Started | Aug 25 07:50:33 AM UTC 24 |
| Finished | Aug 25 07:50:56 AM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082274962 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_tok en_mux.1082274962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3475321154 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 208738445 ps |
| CPU time | 10.39 seconds |
| Started | Aug 25 07:50:30 AM UTC 24 |
| Finished | Aug 25 07:50:42 AM UTC 24 |
| Peak memory | 232480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475321154 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3475321154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.878458673 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 165963293 ps |
| CPU time | 3.06 seconds |
| Started | Aug 25 07:50:25 AM UTC 24 |
| Finished | Aug 25 07:50:30 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878458673 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.878458673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2959939924 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 234623729 ps |
| CPU time | 33.84 seconds |
| Started | Aug 25 07:50:28 AM UTC 24 |
| Finished | Aug 25 07:51:04 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959939924 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2959939924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.141246927 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 85780454 ps |
| CPU time | 13.2 seconds |
| Started | Aug 25 07:50:28 AM UTC 24 |
| Finished | Aug 25 07:50:42 AM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141246927 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.141246927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.346460259 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 24435412810 ps |
| CPU time | 194.98 seconds |
| Started | Aug 25 07:50:33 AM UTC 24 |
| Finished | Aug 25 07:53:51 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=346460259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 48.lc_ctrl_stress_all.346460259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1116529772 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3744934580 ps |
| CPU time | 135.13 seconds |
| Started | Aug 25 07:50:33 AM UTC 24 |
| Finished | Aug 25 07:52:51 AM UTC 24 |
| Peak memory | 281348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116529772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1116529772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1551021769 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 36414950 ps |
| CPU time | 1.38 seconds |
| Started | Aug 25 07:50:27 AM UTC 24 |
| Finished | Aug 25 07:50:29 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551021769 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_volatile_unlock_smoke.1551021769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.4095257739 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 22177054 ps |
| CPU time | 1.34 seconds |
| Started | Aug 25 07:50:43 AM UTC 24 |
| Finished | Aug 25 07:50:46 AM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095257739 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4095257739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.214724304 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2310392241 ps |
| CPU time | 13.78 seconds |
| Started | Aug 25 07:50:38 AM UTC 24 |
| Finished | Aug 25 07:50:53 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214724304 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.214724304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.4103132423 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 268092889 ps |
| CPU time | 6.81 seconds |
| Started | Aug 25 07:50:38 AM UTC 24 |
| Finished | Aug 25 07:50:46 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103132423 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_acce ss.4103132423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.193279245 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 325377122 ps |
| CPU time | 4.73 seconds |
| Started | Aug 25 07:50:38 AM UTC 24 |
| Finished | Aug 25 07:50:44 AM UTC 24 |
| Peak memory | 236564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193279245 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.193279245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3325430337 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 324100743 ps |
| CPU time | 15.53 seconds |
| Started | Aug 25 07:50:41 AM UTC 24 |
| Finished | Aug 25 07:50:58 AM UTC 24 |
| Peak memory | 237812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325430337 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3325430337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.253225958 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 5626806561 ps |
| CPU time | 31.99 seconds |
| Started | Aug 25 07:50:42 AM UTC 24 |
| Finished | Aug 25 07:51:16 AM UTC 24 |
| Peak memory | 238248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253225958 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_t oken_digest.253225958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2901601280 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 7062370008 ps |
| CPU time | 18.13 seconds |
| Started | Aug 25 07:50:41 AM UTC 24 |
| Finished | Aug 25 07:51:00 AM UTC 24 |
| Peak memory | 237776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901601280 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_tok en_mux.2901601280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1281609208 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1490284010 ps |
| CPU time | 19.16 seconds |
| Started | Aug 25 07:50:38 AM UTC 24 |
| Finished | Aug 25 07:50:59 AM UTC 24 |
| Peak memory | 238184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281609208 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1281609208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.1113339294 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 181945149 ps |
| CPU time | 4.5 seconds |
| Started | Aug 25 07:50:34 AM UTC 24 |
| Finished | Aug 25 07:50:40 AM UTC 24 |
| Peak memory | 226196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113339294 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1113339294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.4063536589 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 282452905 ps |
| CPU time | 29.81 seconds |
| Started | Aug 25 07:50:35 AM UTC 24 |
| Finished | Aug 25 07:51:06 AM UTC 24 |
| Peak memory | 256884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063536589 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.4063536589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.3977631885 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 477404472 ps |
| CPU time | 7.36 seconds |
| Started | Aug 25 07:50:37 AM UTC 24 |
| Finished | Aug 25 07:50:45 AM UTC 24 |
| Peak memory | 236568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977631885 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3977631885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2495511984 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 42174227381 ps |
| CPU time | 338.98 seconds |
| Started | Aug 25 07:50:43 AM UTC 24 |
| Finished | Aug 25 07:56:28 AM UTC 24 |
| Peak memory | 263028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2495511984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 49.lc_ctrl_stress_all.2495511984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.753118854 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3373048232 ps |
| CPU time | 108.33 seconds |
| Started | Aug 25 07:50:43 AM UTC 24 |
| Finished | Aug 25 07:52:34 AM UTC 24 |
| Peak memory | 283856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753118854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.753118854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.494372925 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 74516446 ps |
| CPU time | 1.66 seconds |
| Started | Aug 25 07:50:34 AM UTC 24 |
| Finished | Aug 25 07:50:37 AM UTC 24 |
| Peak memory | 222976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494372925 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.lc_ctrl_volatile_unlock_smoke.494372925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2221147185 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 21934054 ps |
| CPU time | 1.95 seconds |
| Started | Aug 25 07:41:21 AM UTC 24 |
| Finished | Aug 25 07:41:24 AM UTC 24 |
| Peak memory | 218872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221147185 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2221147185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3422899146 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 16739754 ps |
| CPU time | 1.31 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:14 AM UTC 24 |
| Peak memory | 219420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422899146 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3422899146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1503061447 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 253667102 ps |
| CPU time | 16.34 seconds |
| Started | Aug 25 07:41:05 AM UTC 24 |
| Finished | Aug 25 07:41:22 AM UTC 24 |
| Peak memory | 237860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503061447 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1503061447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.38623930 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5387828201 ps |
| CPU time | 23.2 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:37 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38623930 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.38623930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.2783683995 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 9883137330 ps |
| CPU time | 59.51 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:42:14 AM UTC 24 |
| Peak memory | 238236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783683995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_errors.2783683995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2690414895 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 271171518 ps |
| CPU time | 6.88 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:20 AM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690414895 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_pri ority.2690414895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.3149762945 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 294870805 ps |
| CPU time | 7.87 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:21 AM UTC 24 |
| Peak memory | 234256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149762945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct rl_jtag_prog_failure.3149762945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.852215413 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1866544324 ps |
| CPU time | 22.47 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:36 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852215413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc _ctrl_jtag_regwen_during_op.852215413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3966726909 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 302004401 ps |
| CPU time | 3.68 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:17 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966726909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag _smoke.3966726909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.3799426558 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 17261730355 ps |
| CPU time | 77.05 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:42:31 AM UTC 24 |
| Peak memory | 285344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799426558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_c trl_jtag_state_failure.3799426558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.3616123179 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1549950227 ps |
| CPU time | 21.17 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:35 AM UTC 24 |
| Peak memory | 263096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616123179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l c_ctrl_jtag_state_post_trans.3616123179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.2825601503 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 90117100 ps |
| CPU time | 5.06 seconds |
| Started | Aug 25 07:41:05 AM UTC 24 |
| Finished | Aug 25 07:41:11 AM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825601503 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2825601503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.573318059 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 749590979 ps |
| CPU time | 18.48 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:32 AM UTC 24 |
| Peak memory | 229788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573318059 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.573318059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1185990017 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1674415233 ps |
| CPU time | 24.24 seconds |
| Started | Aug 25 07:41:15 AM UTC 24 |
| Finished | Aug 25 07:41:40 AM UTC 24 |
| Peak memory | 238180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185990017 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1185990017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.966204049 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 950611464 ps |
| CPU time | 16.13 seconds |
| Started | Aug 25 07:41:17 AM UTC 24 |
| Finished | Aug 25 07:41:34 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966204049 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_to ken_digest.966204049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.4071495934 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 229192022 ps |
| CPU time | 10.98 seconds |
| Started | Aug 25 07:41:15 AM UTC 24 |
| Finished | Aug 25 07:41:27 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071495934 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_toke n_mux.4071495934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.1248834216 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1047036628 ps |
| CPU time | 9.61 seconds |
| Started | Aug 25 07:41:12 AM UTC 24 |
| Finished | Aug 25 07:41:23 AM UTC 24 |
| Peak memory | 232532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248834216 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1248834216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.3704626037 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 184709070 ps |
| CPU time | 4.15 seconds |
| Started | Aug 25 07:41:00 AM UTC 24 |
| Finished | Aug 25 07:41:06 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704626037 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3704626037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.2315228877 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 531790250 ps |
| CPU time | 45.91 seconds |
| Started | Aug 25 07:41:02 AM UTC 24 |
| Finished | Aug 25 07:41:50 AM UTC 24 |
| Peak memory | 260792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315228877 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2315228877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.1789883106 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 80238934 ps |
| CPU time | 4.28 seconds |
| Started | Aug 25 07:41:05 AM UTC 24 |
| Finished | Aug 25 07:41:10 AM UTC 24 |
| Peak memory | 234596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789883106 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1789883106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.370263254 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 7073728387 ps |
| CPU time | 62.29 seconds |
| Started | Aug 25 07:41:19 AM UTC 24 |
| Finished | Aug 25 07:42:23 AM UTC 24 |
| Peak memory | 238244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=370263254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 5.lc_ctrl_stress_all.370263254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.60070634 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 16714567 ps |
| CPU time | 1.17 seconds |
| Started | Aug 25 07:41:02 AM UTC 24 |
| Finished | Aug 25 07:41:05 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60070634 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5. lc_ctrl_volatile_unlock_smoke.60070634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.394939818 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 42890524 ps |
| CPU time | 1.54 seconds |
| Started | Aug 25 07:41:38 AM UTC 24 |
| Finished | Aug 25 07:41:40 AM UTC 24 |
| Peak memory | 219092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394939818 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.394939818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2396095679 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 147598397 ps |
| CPU time | 1.26 seconds |
| Started | Aug 25 07:41:28 AM UTC 24 |
| Finished | Aug 25 07:41:31 AM UTC 24 |
| Peak memory | 218700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396095679 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2396095679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3133734026 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1337074578 ps |
| CPU time | 14.31 seconds |
| Started | Aug 25 07:41:26 AM UTC 24 |
| Finished | Aug 25 07:41:41 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133734026 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3133734026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.187494381 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1558263299 ps |
| CPU time | 27.02 seconds |
| Started | Aug 25 07:41:34 AM UTC 24 |
| Finished | Aug 25 07:42:02 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187494381 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.187494381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2622408424 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4171143164 ps |
| CPU time | 48.07 seconds |
| Started | Aug 25 07:41:34 AM UTC 24 |
| Finished | Aug 25 07:42:24 AM UTC 24 |
| Peak memory | 238272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622408424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_errors.2622408424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3215062178 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 428692250 ps |
| CPU time | 17.24 seconds |
| Started | Aug 25 07:41:34 AM UTC 24 |
| Finished | Aug 25 07:41:53 AM UTC 24 |
| Peak memory | 230056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215062178 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_pri ority.3215062178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3760392489 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 835143482 ps |
| CPU time | 9.52 seconds |
| Started | Aug 25 07:41:31 AM UTC 24 |
| Finished | Aug 25 07:41:42 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760392489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct rl_jtag_prog_failure.3760392489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3047833507 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1225756281 ps |
| CPU time | 48.25 seconds |
| Started | Aug 25 07:41:34 AM UTC 24 |
| Finished | Aug 25 07:42:24 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047833507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l c_ctrl_jtag_regwen_during_op.3047833507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3436666446 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 218592515 ps |
| CPU time | 7.53 seconds |
| Started | Aug 25 07:41:28 AM UTC 24 |
| Finished | Aug 25 07:41:37 AM UTC 24 |
| Peak memory | 230272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436666446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag _smoke.3436666446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3459149897 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 11684504370 ps |
| CPU time | 109.12 seconds |
| Started | Aug 25 07:41:28 AM UTC 24 |
| Finished | Aug 25 07:43:20 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459149897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_c trl_jtag_state_failure.3459149897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.390607370 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 591585577 ps |
| CPU time | 37.89 seconds |
| Started | Aug 25 07:41:28 AM UTC 24 |
| Finished | Aug 25 07:42:08 AM UTC 24 |
| Peak memory | 262776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390607370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc _ctrl_jtag_state_post_trans.390607370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1973416542 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 74909257 ps |
| CPU time | 5.05 seconds |
| Started | Aug 25 07:41:26 AM UTC 24 |
| Finished | Aug 25 07:41:32 AM UTC 24 |
| Peak memory | 236624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973416542 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1973416542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1512729078 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1409091003 ps |
| CPU time | 32.18 seconds |
| Started | Aug 25 07:41:26 AM UTC 24 |
| Finished | Aug 25 07:42:00 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512729078 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1512729078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2390003356 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1413676497 ps |
| CPU time | 17.54 seconds |
| Started | Aug 25 07:41:36 AM UTC 24 |
| Finished | Aug 25 07:41:55 AM UTC 24 |
| Peak memory | 237844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390003356 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2390003356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.1701663024 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 655322966 ps |
| CPU time | 30.63 seconds |
| Started | Aug 25 07:41:36 AM UTC 24 |
| Finished | Aug 25 07:42:08 AM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701663024 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_t oken_digest.1701663024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1815800883 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 269107041 ps |
| CPU time | 11.2 seconds |
| Started | Aug 25 07:41:26 AM UTC 24 |
| Finished | Aug 25 07:41:38 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815800883 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1815800883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2264885297 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 29741857 ps |
| CPU time | 2.48 seconds |
| Started | Aug 25 07:41:21 AM UTC 24 |
| Finished | Aug 25 07:41:25 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264885297 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2264885297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1584948977 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1077243957 ps |
| CPU time | 60.35 seconds |
| Started | Aug 25 07:41:24 AM UTC 24 |
| Finished | Aug 25 07:42:26 AM UTC 24 |
| Peak memory | 260716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584948977 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1584948977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.1815260912 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 185034537 ps |
| CPU time | 12.69 seconds |
| Started | Aug 25 07:41:24 AM UTC 24 |
| Finished | Aug 25 07:41:38 AM UTC 24 |
| Peak memory | 262840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815260912 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1815260912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1732986404 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 12452206243 ps |
| CPU time | 286.06 seconds |
| Started | Aug 25 07:41:37 AM UTC 24 |
| Finished | Aug 25 07:46:28 AM UTC 24 |
| Peak memory | 281252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1732986404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 6.lc_ctrl_stress_all.1732986404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.912843555 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 32009458 ps |
| CPU time | 1.26 seconds |
| Started | Aug 25 07:41:24 AM UTC 24 |
| Finished | Aug 25 07:41:26 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912843555 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6 .lc_ctrl_volatile_unlock_smoke.912843555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.538581630 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 79059779 ps |
| CPU time | 1.61 seconds |
| Started | Aug 25 07:42:07 AM UTC 24 |
| Finished | Aug 25 07:42:09 AM UTC 24 |
| Peak memory | 218912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538581630 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.538581630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2387186072 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 11254941 ps |
| CPU time | 1.17 seconds |
| Started | Aug 25 07:41:44 AM UTC 24 |
| Finished | Aug 25 07:41:47 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387186072 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2387186072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.2821910386 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1134801748 ps |
| CPU time | 27.21 seconds |
| Started | Aug 25 07:41:42 AM UTC 24 |
| Finished | Aug 25 07:42:11 AM UTC 24 |
| Peak memory | 238188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821910386 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2821910386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.613449311 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 151112443 ps |
| CPU time | 3.93 seconds |
| Started | Aug 25 07:42:02 AM UTC 24 |
| Finished | Aug 25 07:42:07 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613449311 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.613449311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3021825872 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1874365295 ps |
| CPU time | 40.62 seconds |
| Started | Aug 25 07:41:54 AM UTC 24 |
| Finished | Aug 25 07:42:37 AM UTC 24 |
| Peak memory | 238232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021825872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_errors.3021825872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1225827204 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 113312680 ps |
| CPU time | 5.59 seconds |
| Started | Aug 25 07:42:02 AM UTC 24 |
| Finished | Aug 25 07:42:09 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225827204 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_pri ority.1225827204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3816361040 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 822794048 ps |
| CPU time | 11.28 seconds |
| Started | Aug 25 07:41:53 AM UTC 24 |
| Finished | Aug 25 07:42:05 AM UTC 24 |
| Peak memory | 236316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816361040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_jtag_prog_failure.3816361040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.419365268 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4897067787 ps |
| CPU time | 38.45 seconds |
| Started | Aug 25 07:42:02 AM UTC 24 |
| Finished | Aug 25 07:42:42 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419365268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc _ctrl_jtag_regwen_during_op.419365268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.3528071516 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 822327771 ps |
| CPU time | 18.58 seconds |
| Started | Aug 25 07:41:46 AM UTC 24 |
| Finished | Aug 25 07:42:06 AM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528071516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag _smoke.3528071516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.2401191626 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 8274721241 ps |
| CPU time | 183.72 seconds |
| Started | Aug 25 07:41:48 AM UTC 24 |
| Finished | Aug 25 07:44:55 AM UTC 24 |
| Peak memory | 295584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401191626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_c trl_jtag_state_failure.2401191626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1199536918 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3127554070 ps |
| CPU time | 18.67 seconds |
| Started | Aug 25 07:41:51 AM UTC 24 |
| Finished | Aug 25 07:42:11 AM UTC 24 |
| Peak memory | 238328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199536918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l c_ctrl_jtag_state_post_trans.1199536918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2809068408 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 35127759 ps |
| CPU time | 2.95 seconds |
| Started | Aug 25 07:41:41 AM UTC 24 |
| Finished | Aug 25 07:41:45 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809068408 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2809068408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.116817690 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 374195052 ps |
| CPU time | 9.29 seconds |
| Started | Aug 25 07:41:43 AM UTC 24 |
| Finished | Aug 25 07:41:54 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116817690 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.116817690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.814884365 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 972140764 ps |
| CPU time | 22.55 seconds |
| Started | Aug 25 07:42:03 AM UTC 24 |
| Finished | Aug 25 07:42:27 AM UTC 24 |
| Peak memory | 237840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814884365 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.814884365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.377008594 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 567772737 ps |
| CPU time | 17.97 seconds |
| Started | Aug 25 07:42:03 AM UTC 24 |
| Finished | Aug 25 07:42:23 AM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377008594 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_to ken_digest.377008594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3001700137 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1204577068 ps |
| CPU time | 11.25 seconds |
| Started | Aug 25 07:42:03 AM UTC 24 |
| Finished | Aug 25 07:42:16 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001700137 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_toke n_mux.3001700137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.681548858 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 897558170 ps |
| CPU time | 10.81 seconds |
| Started | Aug 25 07:41:42 AM UTC 24 |
| Finished | Aug 25 07:41:54 AM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681548858 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.681548858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3272765872 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 218558708 ps |
| CPU time | 4 seconds |
| Started | Aug 25 07:41:39 AM UTC 24 |
| Finished | Aug 25 07:41:44 AM UTC 24 |
| Peak memory | 230268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272765872 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3272765872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.282634120 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 199079206 ps |
| CPU time | 40.06 seconds |
| Started | Aug 25 07:41:40 AM UTC 24 |
| Finished | Aug 25 07:42:22 AM UTC 24 |
| Peak memory | 262700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282634120 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.282634120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3622302210 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 199884423 ps |
| CPU time | 15.64 seconds |
| Started | Aug 25 07:41:41 AM UTC 24 |
| Finished | Aug 25 07:41:58 AM UTC 24 |
| Peak memory | 262720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622302210 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3622302210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.1919287891 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2362235090 ps |
| CPU time | 161.48 seconds |
| Started | Aug 25 07:42:03 AM UTC 24 |
| Finished | Aug 25 07:44:48 AM UTC 24 |
| Peak memory | 289520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1919287891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 7.lc_ctrl_stress_all.1919287891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1523673595 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 34164587 ps |
| CPU time | 1.34 seconds |
| Started | Aug 25 07:41:39 AM UTC 24 |
| Finished | Aug 25 07:41:41 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523673595 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_volatile_unlock_smoke.1523673595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1611243999 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 25958214 ps |
| CPU time | 1.4 seconds |
| Started | Aug 25 07:42:36 AM UTC 24 |
| Finished | Aug 25 07:42:39 AM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611243999 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1611243999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2592455274 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1724680360 ps |
| CPU time | 19.14 seconds |
| Started | Aug 25 07:42:10 AM UTC 24 |
| Finished | Aug 25 07:42:31 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592455274 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2592455274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.398544157 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 722554789 ps |
| CPU time | 9.33 seconds |
| Started | Aug 25 07:42:20 AM UTC 24 |
| Finished | Aug 25 07:42:31 AM UTC 24 |
| Peak memory | 229992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398544157 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.398544157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.4138150951 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 8370491976 ps |
| CPU time | 60.89 seconds |
| Started | Aug 25 07:42:20 AM UTC 24 |
| Finished | Aug 25 07:43:23 AM UTC 24 |
| Peak memory | 232548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138150951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_errors.4138150951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.23458997 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 452214261 ps |
| CPU time | 4.03 seconds |
| Started | Aug 25 07:42:20 AM UTC 24 |
| Finished | Aug 25 07:42:26 AM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23458997 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.23458997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.648548943 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 12666729626 ps |
| CPU time | 32.38 seconds |
| Started | Aug 25 07:42:20 AM UTC 24 |
| Finished | Aug 25 07:42:54 AM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648548943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr l_jtag_prog_failure.648548943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1371564997 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1352095017 ps |
| CPU time | 59.47 seconds |
| Started | Aug 25 07:42:20 AM UTC 24 |
| Finished | Aug 25 07:43:22 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371564997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l c_ctrl_jtag_regwen_during_op.1371564997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1604861340 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 693999639 ps |
| CPU time | 7.75 seconds |
| Started | Aug 25 07:42:19 AM UTC 24 |
| Finished | Aug 25 07:42:28 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604861340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _smoke.1604861340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3039961217 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4253733425 ps |
| CPU time | 130.83 seconds |
| Started | Aug 25 07:42:19 AM UTC 24 |
| Finished | Aug 25 07:44:32 AM UTC 24 |
| Peak memory | 295668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039961217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_c trl_jtag_state_failure.3039961217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1787738618 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 658061303 ps |
| CPU time | 15.12 seconds |
| Started | Aug 25 07:42:19 AM UTC 24 |
| Finished | Aug 25 07:42:35 AM UTC 24 |
| Peak memory | 262840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787738618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l c_ctrl_jtag_state_post_trans.1787738618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2516690995 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 30928174 ps |
| CPU time | 3.16 seconds |
| Started | Aug 25 07:42:10 AM UTC 24 |
| Finished | Aug 25 07:42:14 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516690995 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2516690995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2828234934 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 619679054 ps |
| CPU time | 29.38 seconds |
| Started | Aug 25 07:42:11 AM UTC 24 |
| Finished | Aug 25 07:42:42 AM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828234934 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2828234934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1500398907 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 359856965 ps |
| CPU time | 21.01 seconds |
| Started | Aug 25 07:42:22 AM UTC 24 |
| Finished | Aug 25 07:42:44 AM UTC 24 |
| Peak memory | 232460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500398907 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1500398907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1979205944 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1214621212 ps |
| CPU time | 14.54 seconds |
| Started | Aug 25 07:42:23 AM UTC 24 |
| Finished | Aug 25 07:42:38 AM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979205944 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_t oken_digest.1979205944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3907561900 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 335647808 ps |
| CPU time | 13.65 seconds |
| Started | Aug 25 07:42:22 AM UTC 24 |
| Finished | Aug 25 07:42:36 AM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907561900 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_toke n_mux.3907561900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3897657608 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 340453561 ps |
| CPU time | 14.48 seconds |
| Started | Aug 25 07:42:11 AM UTC 24 |
| Finished | Aug 25 07:42:27 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897657608 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3897657608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2621063678 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 23337303 ps |
| CPU time | 1.97 seconds |
| Started | Aug 25 07:42:07 AM UTC 24 |
| Finished | Aug 25 07:42:10 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621063678 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2621063678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1732277295 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 416452386 ps |
| CPU time | 39.52 seconds |
| Started | Aug 25 07:42:09 AM UTC 24 |
| Finished | Aug 25 07:42:50 AM UTC 24 |
| Peak memory | 260720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732277295 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1732277295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.2747570887 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 323372081 ps |
| CPU time | 12.99 seconds |
| Started | Aug 25 07:42:09 AM UTC 24 |
| Finished | Aug 25 07:42:24 AM UTC 24 |
| Peak memory | 263096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747570887 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2747570887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.3956224932 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 9236971043 ps |
| CPU time | 146.05 seconds |
| Started | Aug 25 07:42:36 AM UTC 24 |
| Finished | Aug 25 07:45:05 AM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3956224932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.lc_ctrl_stress_all.3956224932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2245446677 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1033536779 ps |
| CPU time | 48.15 seconds |
| Started | Aug 25 07:42:36 AM UTC 24 |
| Finished | Aug 25 07:43:26 AM UTC 24 |
| Peak memory | 262888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245446677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2245446677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2533412350 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 21831384 ps |
| CPU time | 1.46 seconds |
| Started | Aug 25 07:42:08 AM UTC 24 |
| Finished | Aug 25 07:42:10 AM UTC 24 |
| Peak memory | 220664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533412350 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_volatile_unlock_smoke.2533412350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3951108276 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 88470680 ps |
| CPU time | 2 seconds |
| Started | Aug 25 07:42:43 AM UTC 24 |
| Finished | Aug 25 07:42:46 AM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951108276 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3951108276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.1859507098 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 37706476 ps |
| CPU time | 1.26 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:42 AM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859507098 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1859507098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2132740131 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 232530493 ps |
| CPU time | 17.87 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:58 AM UTC 24 |
| Peak memory | 237860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132740131 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2132740131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.7955062 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 964132755 ps |
| CPU time | 32.27 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:43:14 AM UTC 24 |
| Peak memory | 230012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7955062 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.7955062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.778417391 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1820313089 ps |
| CPU time | 47.38 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:43:29 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778417391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j tag_errors.778417391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1765842182 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 717510820 ps |
| CPU time | 5.92 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:47 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765842182 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_pri ority.1765842182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.3728630615 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 402528254 ps |
| CPU time | 10.58 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:51 AM UTC 24 |
| Peak memory | 236192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728630615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct rl_jtag_prog_failure.3728630615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.282071528 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1063082908 ps |
| CPU time | 31.57 seconds |
| Started | Aug 25 07:42:40 AM UTC 24 |
| Finished | Aug 25 07:43:13 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282071528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc _ctrl_jtag_regwen_during_op.282071528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3451789655 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 846788997 ps |
| CPU time | 11.1 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:52 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451789655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _smoke.3451789655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.3833636210 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5083903181 ps |
| CPU time | 73 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:43:54 AM UTC 24 |
| Peak memory | 281324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833636210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_c trl_jtag_state_failure.3833636210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1398285722 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 690799423 ps |
| CPU time | 31.94 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:43:13 AM UTC 24 |
| Peak memory | 262724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398285722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.l c_ctrl_jtag_state_post_trans.1398285722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1226567089 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 71848984 ps |
| CPU time | 3.3 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:44 AM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226567089 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1226567089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2080833569 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 315575082 ps |
| CPU time | 11.87 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:52 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080833569 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2080833569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.4275990482 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2334115885 ps |
| CPU time | 22.13 seconds |
| Started | Aug 25 07:42:40 AM UTC 24 |
| Finished | Aug 25 07:43:03 AM UTC 24 |
| Peak memory | 237984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275990482 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.4275990482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3144085008 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 895234430 ps |
| CPU time | 12.91 seconds |
| Started | Aug 25 07:42:41 AM UTC 24 |
| Finished | Aug 25 07:42:55 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144085008 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_t oken_digest.3144085008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1841751940 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 579316444 ps |
| CPU time | 14.93 seconds |
| Started | Aug 25 07:42:41 AM UTC 24 |
| Finished | Aug 25 07:42:57 AM UTC 24 |
| Peak memory | 237844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841751940 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_toke n_mux.1841751940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.4165241143 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 748766644 ps |
| CPU time | 8.41 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:49 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165241143 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4165241143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1449342596 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2264066295 ps |
| CPU time | 6.77 seconds |
| Started | Aug 25 07:42:36 AM UTC 24 |
| Finished | Aug 25 07:42:44 AM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449342596 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1449342596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.1307286593 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 872691270 ps |
| CPU time | 61.85 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:43:43 AM UTC 24 |
| Peak memory | 260716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307286593 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1307286593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3064184315 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 208201439 ps |
| CPU time | 12.57 seconds |
| Started | Aug 25 07:42:39 AM UTC 24 |
| Finished | Aug 25 07:42:53 AM UTC 24 |
| Peak memory | 262596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064184315 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3064184315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.441561847 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 6085709090 ps |
| CPU time | 79.42 seconds |
| Started | Aug 25 07:42:41 AM UTC 24 |
| Finished | Aug 25 07:44:02 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=441561847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.lc_ctrl_stress_all.441561847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2469734186 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6096706794 ps |
| CPU time | 118.81 seconds |
| Started | Aug 25 07:42:43 AM UTC 24 |
| Finished | Aug 25 07:44:44 AM UTC 24 |
| Peak memory | 285480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469734186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.2469734186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3908657982 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 49352536 ps |
| CPU time | 1.38 seconds |
| Started | Aug 25 07:42:36 AM UTC 24 |
| Finished | Aug 25 07:42:39 AM UTC 24 |
| Peak memory | 228836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908657982 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_volatile_unlock_smoke.3908657982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest |
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