Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	702967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

890776

1

T1

7

T2

1

T3

43

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1300592	1			T1	14		T2	2		T3	42
values[0x0]	146059	1			T1	5		T3	15		T4	12
values[0x1]	147092	1			T1	3		T2	1		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	555142	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1038601

1

T1

10

T2

1

T3

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5796	1			T14	3		T7	5		T30	2
valid_sources[0x01]	5075	1			T1	1		T19	1		T7	2
valid_sources[0x02]	5207	1			T12	7		T14	10		T30	2
valid_sources[0x03]	4961	1			T4	1		T7	1		T30	1
valid_sources[0x04]	5042	1			T14	4		T15	2		T7	1
valid_sources[0x05]	5037	1			T15	1		T30	1		T23	3
valid_sources[0x06]	4887	1			T4	1		T19	3		T7	1
valid_sources[0x07]	5055	1			T4	1		T15	3		T30	3
valid_sources[0x08]	7627	1			T4	2		T7	2		T30	7
valid_sources[0x09]	5140	1			T4	2		T15	1		T7	5
valid_sources[0x0a]	4922	1			T15	1		T7	2		T21	13
valid_sources[0x0b]	8879	1			T1	1		T14	8		T15	2
valid_sources[0x0c]	5200	1			T4	2		T14	2		T7	1
valid_sources[0x0d]	5642	1			T4	1		T14	10		T15	2
valid_sources[0x0e]	5376	1			T14	4		T15	1		T7	1
valid_sources[0x0f]	4898	1			T4	1		T15	1		T7	4
valid_sources[0x10]	4813	1			T15	1		T19	1		T7	4
valid_sources[0x11]	7032	1			T14	2		T15	1		T7	1
valid_sources[0x12]	4833	1			T14	5		T15	1		T7	2
valid_sources[0x13]	6966	1			T4	3		T19	1		T7	1
valid_sources[0x14]	5086	1			T14	7		T15	3		T22	3
valid_sources[0x15]	6610	1			T12	1		T14	9		T15	2
valid_sources[0x16]	7977	1			T14	7		T15	1		T19	1
valid_sources[0x17]	4840	1			T4	1		T15	2		T19	2
valid_sources[0x18]	5161	1			T15	1		T21	4		T22	2
valid_sources[0x19]	4904	1			T1	1		T14	1		T15	2
valid_sources[0x1a]	4663	1			T14	3		T15	1		T7	3
valid_sources[0x1b]	5496	1			T14	4		T15	1		T7	5
valid_sources[0x1c]	10465	1			T15	1		T7	1		T30	2
valid_sources[0x1d]	6447	1			T12	4		T15	1		T19	2
valid_sources[0x1e]	6473	1			T15	2		T30	1		T21	1
valid_sources[0x1f]	10647	1			T15	1		T7	5		T30	3
valid_sources[0x20]	4998	1			T12	2		T14	14		T15	1
valid_sources[0x21]	5626	1			T14	4		T15	1		T30	1
valid_sources[0x22]	5261	1			T15	1		T7	1		T21	2
valid_sources[0x23]	5014	1			T15	1		T21	1		T22	7
valid_sources[0x24]	5248	1			T19	1		T7	1		T30	1
valid_sources[0x25]	6545	1			T1	1		T15	2		T19	1
valid_sources[0x26]	5359	1			T14	3		T7	1		T30	1
valid_sources[0x27]	5281	1			T4	1		T15	3		T30	4
valid_sources[0x28]	4953	1			T15	1		T30	2		T22	8
valid_sources[0x29]	10801	1			T15	2		T7	2		T30	1
valid_sources[0x2a]	5279	1			T14	6		T15	2		T7	3
valid_sources[0x2b]	4729	1			T14	7		T15	1		T30	2
valid_sources[0x2c]	4786	1			T30	1		T22	6		T23	10
valid_sources[0x2d]	5871	1			T14	2		T15	1		T19	1
valid_sources[0x2e]	39770	1			T14	6		T15	2		T21	3
valid_sources[0x2f]	20321	1			T14	7		T15	1		T19	1
valid_sources[0x30]	5021	1			T15	1		T30	1		T21	7
valid_sources[0x31]	5240	1			T4	1		T15	3		T7	1
valid_sources[0x32]	6871	1			T14	1		T15	3		T7	1
valid_sources[0x33]	5840	1			T12	1		T14	1		T15	3
valid_sources[0x34]	8577	1			T4	1		T14	4		T15	2
valid_sources[0x35]	4829	1			T15	1		T7	1		T30	1
valid_sources[0x36]	5145	1			T15	3		T7	2		T21	13
valid_sources[0x37]	4915	1			T4	2		T14	1		T7	1
valid_sources[0x38]	5143	1			T14	5		T15	1		T7	3
valid_sources[0x39]	5417	1			T14	10		T7	3		T30	2
valid_sources[0x3a]	5268	1			T4	1		T14	6		T7	2
valid_sources[0x3b]	4776	1			T4	1		T14	2		T7	2
valid_sources[0x3c]	5688	1			T14	3		T7	6		T30	1
valid_sources[0x3d]	5067	1			T15	1		T7	1		T21	9
valid_sources[0x3e]	6771	1			T14	1		T15	1		T19	2
valid_sources[0x3f]	5180	1			T15	1		T7	1		T30	1
valid_sources[0x40]	4958	1			T14	3		T15	1		T7	1
valid_sources[0x41]	4701	1			T4	1		T14	4		T15	1
valid_sources[0x42]	5131	1			T15	1		T7	2		T30	2
valid_sources[0x43]	5235	1			T15	1		T7	1		T30	2
valid_sources[0x44]	5147	1			T1	2		T7	2		T30	2
valid_sources[0x45]	5027	1			T15	1		T7	3		T30	2
valid_sources[0x46]	9506	1			T4	1		T12	2		T15	1
valid_sources[0x47]	4880	1			T15	2		T7	3		T30	1
valid_sources[0x48]	4710	1			T14	2		T15	1		T7	1
valid_sources[0x49]	4772	1			T1	1		T15	2		T22	4
valid_sources[0x4a]	5026	1			T15	1		T19	1		T7	2
valid_sources[0x4b]	5228	1			T15	1		T19	2		T7	3
valid_sources[0x4c]	5307	1			T1	1		T14	4		T15	1
valid_sources[0x4d]	6060	1			T14	1		T7	4		T30	1
valid_sources[0x4e]	4677	1			T15	1		T7	2		T30	1
valid_sources[0x4f]	5838	1			T14	7		T19	1		T21	14
valid_sources[0x50]	5079	1			T15	1		T7	1		T30	2
valid_sources[0x51]	4897	1			T15	1		T7	4		T30	2
valid_sources[0x52]	4785	1			T4	2		T14	3		T15	3
valid_sources[0x53]	5170	1			T14	1		T19	1		T7	2
valid_sources[0x54]	5002	1			T15	3		T22	9		T27	7
valid_sources[0x55]	4740	1			T7	1		T22	5		T23	3
valid_sources[0x56]	10961	1			T4	1		T15	1		T7	2
valid_sources[0x57]	5012	1			T7	4		T21	8		T22	5
valid_sources[0x58]	4961	1			T15	1		T7	2		T30	2
valid_sources[0x59]	5888	1			T4	2		T15	1		T19	3
valid_sources[0x5a]	6760	1			T14	5		T15	1		T19	1
valid_sources[0x5b]	4994	1			T1	1		T14	2		T15	3
valid_sources[0x5c]	4796	1			T12	4		T30	1		T22	4
valid_sources[0x5d]	9131	1			T7	3		T21	11		T22	7
valid_sources[0x5e]	6670	1			T14	7		T7	1		T22	9
valid_sources[0x5f]	5046	1			T15	1		T22	6		T23	6
valid_sources[0x60]	4936	1			T14	11		T15	1		T19	1
valid_sources[0x61]	12783	1			T14	4		T30	2		T21	4
valid_sources[0x62]	5185	1			T14	19		T15	3		T7	1
valid_sources[0x63]	5394	1			T14	14		T19	1		T7	1
valid_sources[0x64]	4833	1			T14	6		T19	1		T7	2
valid_sources[0x65]	5119	1			T4	1		T15	1		T7	1
valid_sources[0x66]	5318	1			T14	4		T15	2		T7	1
valid_sources[0x67]	6397	1			T4	1		T14	3		T19	4
valid_sources[0x68]	7148	1			T14	2		T7	1		T30	2
valid_sources[0x69]	5661	1			T14	11		T15	1		T19	4
valid_sources[0x6a]	12109	1			T15	1		T19	1		T30	2
valid_sources[0x6b]	4828	1			T14	1		T30	3		T21	1
valid_sources[0x6c]	5008	1			T15	2		T7	1		T21	3
valid_sources[0x6d]	6630	1			T14	3		T15	3		T7	3
valid_sources[0x6e]	5009	1			T14	4		T15	2		T7	2
valid_sources[0x6f]	5036	1			T14	2		T15	1		T30	2
valid_sources[0x70]	4951	1			T4	1		T14	6		T7	3
valid_sources[0x71]	6702	1			T14	5		T7	1		T22	5
valid_sources[0x72]	5314	1			T15	1		T7	1		T30	1
valid_sources[0x73]	6812	1			T4	3		T14	5		T15	2
valid_sources[0x74]	7404	1			T14	1		T15	1		T7	1
valid_sources[0x75]	5284	1			T14	15		T7	1		T30	5
valid_sources[0x76]	5083	1			T13	7		T15	1		T7	1
valid_sources[0x77]	5018	1			T15	1		T7	1		T22	4
valid_sources[0x78]	7264	1			T4	1		T15	3		T7	1
valid_sources[0x79]	5164	1			T2	3		T14	1		T7	2
valid_sources[0x7a]	6337	1			T4	1		T14	12		T15	3
valid_sources[0x7b]	6434	1			T14	4		T15	3		T19	1
valid_sources[0x7c]	5809	1			T4	1		T14	8		T30	3
valid_sources[0x7d]	5673	1			T14	2		T15	1		T7	2
valid_sources[0x7e]	4799	1			T1	2		T14	4		T15	1
valid_sources[0x7f]	6794	1			T7	1		T30	1		T22	9
valid_sources[0x80]	5877	1			T14	14		T15	1		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

638584

1

T2

1

T3

22

T4

31

values[0x0]

all_enables

biggest_size

126353

1

T1

5

T3

13

T4

11

values[0x1]

all_enables

biggest_size

125839

1

T1

2

T3

8

T4

24