Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59264237	12612	0	0
claim_transition_if_regwen_rd_A	59264237	1118	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59264237	12612	0	0
T10	46165	0	0	0
T62	11452	0	0	0
T67	0	7	0	0
T71	3817	0	0	0
T93	168209	6	0	0
T94	218556	0	0	0
T98	0	4	0	0
T99	0	11	0	0
T111	0	11	0	0
T162	0	3	0	0
T163	0	6	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	8	0	0
T167	84532	0	0	0
T168	143955	0	0	0
T169	739	0	0	0
T170	177185	0	0	0
T171	21115	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59264237	1118	0	0
T109	0	14	0	0
T124	986108	0	0	0
T132	0	9	0	0
T172	238473	11	0	0
T173	0	9	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	204	0	0
T177	0	5	0	0
T178	0	7	0	0
T179	0	6	0	0
T180	6263	0	0	0
T181	3783	0	0	0
T182	19961	0	0	0
T183	91393	0	0	0
T184	27760	0	0	0
T185	22240	0	0	0
T186	8605	0	0	0
T187	21746	0	0	0