| T590 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.2914577397 |
|
|
Sep 04 06:17:19 AM UTC 24 |
Sep 04 06:17:23 AM UTC 24 |
55079644 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.1445991371 |
|
|
Sep 04 06:17:02 AM UTC 24 |
Sep 04 06:17:24 AM UTC 24 |
162451724 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.300011052 |
|
|
Sep 04 06:17:50 AM UTC 24 |
Sep 04 06:18:02 AM UTC 24 |
251225769 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2461373135 |
|
|
Sep 04 06:17:21 AM UTC 24 |
Sep 04 06:17:25 AM UTC 24 |
203830743 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.367199557 |
|
|
Sep 04 06:17:04 AM UTC 24 |
Sep 04 06:17:25 AM UTC 24 |
1445507191 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.3179343728 |
|
|
Sep 04 06:17:11 AM UTC 24 |
Sep 04 06:17:25 AM UTC 24 |
447869212 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.2622803313 |
|
|
Sep 04 06:17:24 AM UTC 24 |
Sep 04 06:17:26 AM UTC 24 |
11445758 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.2043185577 |
|
|
Sep 04 06:17:24 AM UTC 24 |
Sep 04 06:17:26 AM UTC 24 |
43022560 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.3320707028 |
|
|
Sep 04 06:17:11 AM UTC 24 |
Sep 04 06:17:27 AM UTC 24 |
318591786 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.2634199021 |
|
|
Sep 04 06:17:18 AM UTC 24 |
Sep 04 06:17:27 AM UTC 24 |
410681007 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3620038991 |
|
|
Sep 04 06:17:25 AM UTC 24 |
Sep 04 06:17:28 AM UTC 24 |
61396387 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2691929620 |
|
|
Sep 04 06:17:10 AM UTC 24 |
Sep 04 06:17:28 AM UTC 24 |
636177820 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1610315771 |
|
|
Sep 04 06:17:19 AM UTC 24 |
Sep 04 06:17:30 AM UTC 24 |
889763317 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3943306321 |
|
|
Sep 04 06:15:38 AM UTC 24 |
Sep 04 06:17:30 AM UTC 24 |
34751111361 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.2789047076 |
|
|
Sep 04 06:17:27 AM UTC 24 |
Sep 04 06:17:30 AM UTC 24 |
228228346 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2862825384 |
|
|
Sep 04 06:17:26 AM UTC 24 |
Sep 04 06:17:31 AM UTC 24 |
95358553 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.1210596862 |
|
|
Sep 04 06:17:25 AM UTC 24 |
Sep 04 06:17:31 AM UTC 24 |
111207758 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.331527245 |
|
|
Sep 04 06:17:19 AM UTC 24 |
Sep 04 06:17:33 AM UTC 24 |
217985711 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3560919351 |
|
|
Sep 04 06:17:32 AM UTC 24 |
Sep 04 06:17:34 AM UTC 24 |
32319251 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1574199838 |
|
|
Sep 04 06:17:32 AM UTC 24 |
Sep 04 06:17:34 AM UTC 24 |
12412032 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2255150899 |
|
|
Sep 04 06:17:09 AM UTC 24 |
Sep 04 06:17:35 AM UTC 24 |
3047890366 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.1985561982 |
|
|
Sep 04 06:17:32 AM UTC 24 |
Sep 04 06:17:36 AM UTC 24 |
33883740 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.2484527437 |
|
|
Sep 04 06:17:21 AM UTC 24 |
Sep 04 06:17:37 AM UTC 24 |
824323766 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3589792805 |
|
|
Sep 04 06:17:27 AM UTC 24 |
Sep 04 06:17:37 AM UTC 24 |
1593594974 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1638778273 |
|
|
Sep 04 06:17:35 AM UTC 24 |
Sep 04 06:17:39 AM UTC 24 |
118101455 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3023491376 |
|
|
Sep 04 06:17:18 AM UTC 24 |
Sep 04 06:17:40 AM UTC 24 |
210420475 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.2578333630 |
|
|
Sep 04 06:17:22 AM UTC 24 |
Sep 04 06:17:40 AM UTC 24 |
342209257 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3909396812 |
|
|
Sep 04 06:17:27 AM UTC 24 |
Sep 04 06:17:41 AM UTC 24 |
386899295 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2035280428 |
|
|
Sep 04 06:17:22 AM UTC 24 |
Sep 04 06:17:42 AM UTC 24 |
759516044 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.3931540097 |
|
|
Sep 04 06:17:28 AM UTC 24 |
Sep 04 06:17:44 AM UTC 24 |
1028238396 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.434474363 |
|
|
Sep 04 06:16:04 AM UTC 24 |
Sep 04 06:17:45 AM UTC 24 |
3672478895 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2242805053 |
|
|
Sep 04 06:17:43 AM UTC 24 |
Sep 04 06:17:45 AM UTC 24 |
16696809 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.4131296490 |
|
|
Sep 04 06:17:34 AM UTC 24 |
Sep 04 06:17:46 AM UTC 24 |
552597513 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.374720821 |
|
|
Sep 04 06:15:52 AM UTC 24 |
Sep 04 06:17:47 AM UTC 24 |
3435122945 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.505861698 |
|
|
Sep 04 06:17:43 AM UTC 24 |
Sep 04 06:17:47 AM UTC 24 |
48982677 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.741645448 |
|
|
Sep 04 06:17:45 AM UTC 24 |
Sep 04 06:17:47 AM UTC 24 |
12145675 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.1248931939 |
|
|
Sep 04 06:17:35 AM UTC 24 |
Sep 04 06:17:48 AM UTC 24 |
232268290 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3200384014 |
|
|
Sep 04 06:17:29 AM UTC 24 |
Sep 04 06:17:48 AM UTC 24 |
1074903146 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.1171336400 |
|
|
Sep 04 06:17:40 AM UTC 24 |
Sep 04 06:17:49 AM UTC 24 |
486692230 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1576837160 |
|
|
Sep 04 06:17:38 AM UTC 24 |
Sep 04 06:17:50 AM UTC 24 |
2793100893 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.3203445595 |
|
|
Sep 04 06:17:47 AM UTC 24 |
Sep 04 06:17:51 AM UTC 24 |
324100818 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2597040326 |
|
|
Sep 04 06:17:36 AM UTC 24 |
Sep 04 06:17:53 AM UTC 24 |
2776483390 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.2881568059 |
|
|
Sep 04 06:16:16 AM UTC 24 |
Sep 04 06:17:53 AM UTC 24 |
18569445359 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.1767204847 |
|
|
Sep 04 06:17:36 AM UTC 24 |
Sep 04 06:17:54 AM UTC 24 |
527712911 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1935047009 |
|
|
Sep 04 06:17:32 AM UTC 24 |
Sep 04 06:17:54 AM UTC 24 |
211929277 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.390838070 |
|
|
Sep 04 06:17:54 AM UTC 24 |
Sep 04 06:17:56 AM UTC 24 |
89588546 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.718157486 |
|
|
Sep 04 06:17:54 AM UTC 24 |
Sep 04 06:17:56 AM UTC 24 |
102631682 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.2222895707 |
|
|
Sep 04 06:17:38 AM UTC 24 |
Sep 04 06:17:57 AM UTC 24 |
357489317 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4000257268 |
|
|
Sep 04 06:17:55 AM UTC 24 |
Sep 04 06:17:57 AM UTC 24 |
12631969 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.163719961 |
|
|
Sep 04 06:17:28 AM UTC 24 |
Sep 04 06:17:58 AM UTC 24 |
1696492720 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.456631377 |
|
|
Sep 04 06:17:47 AM UTC 24 |
Sep 04 06:17:58 AM UTC 24 |
2743146702 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.4128312052 |
|
|
Sep 04 06:17:47 AM UTC 24 |
Sep 04 06:17:58 AM UTC 24 |
191609485 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1618703682 |
|
|
Sep 04 06:17:25 AM UTC 24 |
Sep 04 06:17:58 AM UTC 24 |
908552753 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3164387815 |
|
|
Sep 04 06:17:46 AM UTC 24 |
Sep 04 06:17:59 AM UTC 24 |
254293957 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.863655933 |
|
|
Sep 04 06:16:51 AM UTC 24 |
Sep 04 06:18:00 AM UTC 24 |
4986966346 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1672117326 |
|
|
Sep 04 06:18:40 AM UTC 24 |
Sep 04 06:18:43 AM UTC 24 |
40735411 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.453027428 |
|
|
Sep 04 06:17:58 AM UTC 24 |
Sep 04 06:18:02 AM UTC 24 |
62946678 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.468744066 |
|
|
Sep 04 06:17:59 AM UTC 24 |
Sep 04 06:18:02 AM UTC 24 |
130828347 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.1135380761 |
|
|
Sep 04 06:18:01 AM UTC 24 |
Sep 04 06:18:03 AM UTC 24 |
61877399 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.1070986244 |
|
|
Sep 04 06:17:50 AM UTC 24 |
Sep 04 06:18:04 AM UTC 24 |
338694651 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.3212203570 |
|
|
Sep 04 06:17:47 AM UTC 24 |
Sep 04 06:18:05 AM UTC 24 |
3771794483 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1075550954 |
|
|
Sep 04 06:18:03 AM UTC 24 |
Sep 04 06:18:05 AM UTC 24 |
31572560 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.775641314 |
|
|
Sep 04 06:17:32 AM UTC 24 |
Sep 04 06:18:43 AM UTC 24 |
3977675287 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.282229554 |
|
|
Sep 04 06:16:59 AM UTC 24 |
Sep 04 06:18:06 AM UTC 24 |
2676349187 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.936257900 |
|
|
Sep 04 06:17:12 AM UTC 24 |
Sep 04 06:18:06 AM UTC 24 |
3066972829 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3604734232 |
|
|
Sep 04 06:18:03 AM UTC 24 |
Sep 04 06:18:07 AM UTC 24 |
165594037 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.595053450 |
|
|
Sep 04 06:17:50 AM UTC 24 |
Sep 04 06:18:07 AM UTC 24 |
387494887 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.3908129469 |
|
|
Sep 04 06:17:56 AM UTC 24 |
Sep 04 06:18:08 AM UTC 24 |
122474427 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.6063587 |
|
|
Sep 04 06:17:58 AM UTC 24 |
Sep 04 06:18:08 AM UTC 24 |
824695024 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.1351624619 |
|
|
Sep 04 06:18:31 AM UTC 24 |
Sep 04 06:18:44 AM UTC 24 |
460183786 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.1774925135 |
|
|
Sep 04 06:18:05 AM UTC 24 |
Sep 04 06:18:08 AM UTC 24 |
49506630 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.4008778240 |
|
|
Sep 04 06:18:08 AM UTC 24 |
Sep 04 06:18:11 AM UTC 24 |
218664531 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3991305913 |
|
|
Sep 04 06:17:59 AM UTC 24 |
Sep 04 06:18:11 AM UTC 24 |
1247067133 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.1875583173 |
|
|
Sep 04 06:15:24 AM UTC 24 |
Sep 04 06:18:12 AM UTC 24 |
74020274404 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.659135422 |
|
|
Sep 04 06:18:10 AM UTC 24 |
Sep 04 06:18:12 AM UTC 24 |
40701906 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.2551539527 |
|
|
Sep 04 06:18:10 AM UTC 24 |
Sep 04 06:18:13 AM UTC 24 |
33042012 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.1532775985 |
|
|
Sep 04 06:17:59 AM UTC 24 |
Sep 04 06:18:13 AM UTC 24 |
385133795 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2530855767 |
|
|
Sep 04 06:18:04 AM UTC 24 |
Sep 04 06:18:14 AM UTC 24 |
167500469 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.4027011214 |
|
|
Sep 04 06:18:06 AM UTC 24 |
Sep 04 06:18:15 AM UTC 24 |
1291824177 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.2313586105 |
|
|
Sep 04 06:18:42 AM UTC 24 |
Sep 04 06:18:47 AM UTC 24 |
66985745 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3845211544 |
|
|
Sep 04 06:18:12 AM UTC 24 |
Sep 04 06:18:15 AM UTC 24 |
23661195 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.246472490 |
|
|
Sep 04 06:17:58 AM UTC 24 |
Sep 04 06:18:16 AM UTC 24 |
1271117624 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.4026803665 |
|
|
Sep 04 06:17:59 AM UTC 24 |
Sep 04 06:18:16 AM UTC 24 |
812904536 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2156703266 |
|
|
Sep 04 06:16:59 AM UTC 24 |
Sep 04 06:18:17 AM UTC 24 |
3661667180 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.1929523973 |
|
|
Sep 04 06:18:08 AM UTC 24 |
Sep 04 06:18:18 AM UTC 24 |
1527457489 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.3266113827 |
|
|
Sep 04 06:18:08 AM UTC 24 |
Sep 04 06:18:19 AM UTC 24 |
478530299 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.16802227 |
|
|
Sep 04 06:17:46 AM UTC 24 |
Sep 04 06:18:19 AM UTC 24 |
276042976 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.268089157 |
|
|
Sep 04 06:17:55 AM UTC 24 |
Sep 04 06:18:20 AM UTC 24 |
230971048 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.3824243451 |
|
|
Sep 04 06:18:18 AM UTC 24 |
Sep 04 06:18:20 AM UTC 24 |
37924294 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3124679456 |
|
|
Sep 04 06:18:19 AM UTC 24 |
Sep 04 06:18:21 AM UTC 24 |
40065268 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.2392805814 |
|
|
Sep 04 06:18:14 AM UTC 24 |
Sep 04 06:18:21 AM UTC 24 |
882045801 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.49692462 |
|
|
Sep 04 06:18:06 AM UTC 24 |
Sep 04 06:18:21 AM UTC 24 |
962241416 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3948805031 |
|
|
Sep 04 06:13:59 AM UTC 24 |
Sep 04 06:18:23 AM UTC 24 |
76567684959 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.3223320719 |
|
|
Sep 04 06:18:08 AM UTC 24 |
Sep 04 06:18:23 AM UTC 24 |
3213723517 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.3666353162 |
|
|
Sep 04 06:18:18 AM UTC 24 |
Sep 04 06:18:24 AM UTC 24 |
61978861 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.1458068542 |
|
|
Sep 04 06:18:12 AM UTC 24 |
Sep 04 06:18:25 AM UTC 24 |
189640190 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2380260118 |
|
|
Sep 04 06:18:08 AM UTC 24 |
Sep 04 06:18:25 AM UTC 24 |
517771195 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.3506722945 |
|
|
Sep 04 06:18:21 AM UTC 24 |
Sep 04 06:18:26 AM UTC 24 |
37367054 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2425358862 |
|
|
Sep 04 06:18:06 AM UTC 24 |
Sep 04 06:18:27 AM UTC 24 |
645080165 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3961804473 |
|
|
Sep 04 06:18:14 AM UTC 24 |
Sep 04 06:18:27 AM UTC 24 |
1260242363 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2406332140 |
|
|
Sep 04 06:17:23 AM UTC 24 |
Sep 04 06:18:28 AM UTC 24 |
3447399321 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1185319648 |
|
|
Sep 04 06:18:26 AM UTC 24 |
Sep 04 06:18:28 AM UTC 24 |
18327953 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.2281436249 |
|
|
Sep 04 06:18:30 AM UTC 24 |
Sep 04 06:18:45 AM UTC 24 |
999017517 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.1930721023 |
|
|
Sep 04 06:16:33 AM UTC 24 |
Sep 04 06:18:28 AM UTC 24 |
19590760930 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3136777665 |
|
|
Sep 04 06:18:27 AM UTC 24 |
Sep 04 06:18:29 AM UTC 24 |
23027614 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.704398665 |
|
|
Sep 04 06:18:14 AM UTC 24 |
Sep 04 06:18:29 AM UTC 24 |
1203116731 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.3012460404 |
|
|
Sep 04 06:18:15 AM UTC 24 |
Sep 04 06:18:29 AM UTC 24 |
1881783129 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.592730300 |
|
|
Sep 04 06:18:15 AM UTC 24 |
Sep 04 06:18:29 AM UTC 24 |
1642483945 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3064575208 |
|
|
Sep 04 06:18:28 AM UTC 24 |
Sep 04 06:18:30 AM UTC 24 |
37463664 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.3167645921 |
|
|
Sep 04 06:17:41 AM UTC 24 |
Sep 04 06:18:31 AM UTC 24 |
4113517157 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.2778914502 |
|
|
Sep 04 06:18:22 AM UTC 24 |
Sep 04 06:18:31 AM UTC 24 |
272164631 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.216292012 |
|
|
Sep 04 06:18:24 AM UTC 24 |
Sep 04 06:18:32 AM UTC 24 |
641572428 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.3398864922 |
|
|
Sep 04 06:18:20 AM UTC 24 |
Sep 04 06:18:32 AM UTC 24 |
64690773 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.819508810 |
|
|
Sep 04 06:18:03 AM UTC 24 |
Sep 04 06:18:33 AM UTC 24 |
661735963 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.3181617296 |
|
|
Sep 04 06:18:22 AM UTC 24 |
Sep 04 06:18:34 AM UTC 24 |
1308652030 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.983602856 |
|
|
Sep 04 06:18:30 AM UTC 24 |
Sep 04 06:18:34 AM UTC 24 |
187593680 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.4280234544 |
|
|
Sep 04 06:18:22 AM UTC 24 |
Sep 04 06:18:35 AM UTC 24 |
885864381 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1579822364 |
|
|
Sep 04 06:18:32 AM UTC 24 |
Sep 04 06:18:35 AM UTC 24 |
17845331 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.284150820 |
|
|
Sep 04 06:18:16 AM UTC 24 |
Sep 04 06:18:36 AM UTC 24 |
869800749 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.2492075138 |
|
|
Sep 04 06:18:10 AM UTC 24 |
Sep 04 06:18:36 AM UTC 24 |
771172585 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.160798838 |
|
|
Sep 04 06:18:34 AM UTC 24 |
Sep 04 06:18:36 AM UTC 24 |
20142009 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2701682593 |
|
|
Sep 04 06:17:06 AM UTC 24 |
Sep 04 06:18:37 AM UTC 24 |
18423245457 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.3812825959 |
|
|
Sep 04 06:18:33 AM UTC 24 |
Sep 04 06:18:38 AM UTC 24 |
225104386 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.432861308 |
|
|
Sep 04 06:18:24 AM UTC 24 |
Sep 04 06:18:38 AM UTC 24 |
1706641107 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.89845400 |
|
|
Sep 04 06:18:30 AM UTC 24 |
Sep 04 06:18:39 AM UTC 24 |
1898520505 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.3286247180 |
|
|
Sep 04 06:18:24 AM UTC 24 |
Sep 04 06:18:39 AM UTC 24 |
1661364065 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.2839657405 |
|
|
Sep 04 06:18:22 AM UTC 24 |
Sep 04 06:18:40 AM UTC 24 |
1618375708 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.1726197002 |
|
|
Sep 04 06:18:30 AM UTC 24 |
Sep 04 06:18:40 AM UTC 24 |
2686009755 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.1432024649 |
|
|
Sep 04 06:18:35 AM UTC 24 |
Sep 04 06:18:40 AM UTC 24 |
50097876 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3515982253 |
|
|
Sep 04 06:18:35 AM UTC 24 |
Sep 04 06:18:41 AM UTC 24 |
261011403 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.3767895330 |
|
|
Sep 04 06:18:36 AM UTC 24 |
Sep 04 06:18:41 AM UTC 24 |
73221229 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.3109678941 |
|
|
Sep 04 06:18:29 AM UTC 24 |
Sep 04 06:18:41 AM UTC 24 |
228103180 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.1097377500 |
|
|
Sep 04 06:18:40 AM UTC 24 |
Sep 04 06:18:43 AM UTC 24 |
22853070 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.1319396690 |
|
|
Sep 04 06:18:31 AM UTC 24 |
Sep 04 06:18:43 AM UTC 24 |
1077859435 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.3881559211 |
|
|
Sep 04 06:18:20 AM UTC 24 |
Sep 04 06:18:47 AM UTC 24 |
4544128037 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.249539921 |
|
|
Sep 04 06:18:42 AM UTC 24 |
Sep 04 06:18:47 AM UTC 24 |
351274848 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.716444517 |
|
|
Sep 04 06:18:30 AM UTC 24 |
Sep 04 06:18:48 AM UTC 24 |
301438554 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.3538942919 |
|
|
Sep 04 06:18:40 AM UTC 24 |
Sep 04 06:18:50 AM UTC 24 |
258712532 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.963097040 |
|
|
Sep 04 06:18:48 AM UTC 24 |
Sep 04 06:18:51 AM UTC 24 |
25878828 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2679734096 |
|
|
Sep 04 06:18:48 AM UTC 24 |
Sep 04 06:18:51 AM UTC 24 |
12779045 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2999597107 |
|
|
Sep 04 06:18:38 AM UTC 24 |
Sep 04 06:18:51 AM UTC 24 |
1052728897 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.2260431584 |
|
|
Sep 04 06:18:36 AM UTC 24 |
Sep 04 06:18:52 AM UTC 24 |
372982411 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3693963596 |
|
|
Sep 04 06:18:44 AM UTC 24 |
Sep 04 06:18:52 AM UTC 24 |
364816755 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2838505396 |
|
|
Sep 04 06:18:43 AM UTC 24 |
Sep 04 06:18:52 AM UTC 24 |
215849569 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3875544461 |
|
|
Sep 04 06:18:48 AM UTC 24 |
Sep 04 06:18:53 AM UTC 24 |
144088129 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.34969925 |
|
|
Sep 04 06:18:36 AM UTC 24 |
Sep 04 06:18:54 AM UTC 24 |
1543015462 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.3023197915 |
|
|
Sep 04 06:18:38 AM UTC 24 |
Sep 04 06:18:56 AM UTC 24 |
7759815609 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.2477832192 |
|
|
Sep 04 06:18:52 AM UTC 24 |
Sep 04 06:18:56 AM UTC 24 |
85095561 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.2390337602 |
|
|
Sep 04 06:18:42 AM UTC 24 |
Sep 04 06:18:57 AM UTC 24 |
236925174 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2793157024 |
|
|
Sep 04 06:18:44 AM UTC 24 |
Sep 04 06:18:58 AM UTC 24 |
1536509742 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.4230082313 |
|
|
Sep 04 06:18:44 AM UTC 24 |
Sep 04 06:18:59 AM UTC 24 |
439571958 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1662879824 |
|
|
Sep 04 06:19:29 AM UTC 24 |
Sep 04 06:19:31 AM UTC 24 |
16720161 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.4272629497 |
|
|
Sep 04 06:18:53 AM UTC 24 |
Sep 04 06:18:59 AM UTC 24 |
106687395 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.4193914096 |
|
|
Sep 04 06:18:57 AM UTC 24 |
Sep 04 06:18:59 AM UTC 24 |
56429851 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.1885416 |
|
|
Sep 04 06:18:50 AM UTC 24 |
Sep 04 06:18:59 AM UTC 24 |
66531309 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.597743380 |
|
|
Sep 04 06:18:38 AM UTC 24 |
Sep 04 06:19:00 AM UTC 24 |
509988453 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1984127757 |
|
|
Sep 04 06:18:58 AM UTC 24 |
Sep 04 06:19:00 AM UTC 24 |
114864194 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.288725698 |
|
|
Sep 04 06:18:59 AM UTC 24 |
Sep 04 06:19:01 AM UTC 24 |
20124324 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.3482938026 |
|
|
Sep 04 06:19:29 AM UTC 24 |
Sep 04 06:19:31 AM UTC 24 |
23583115 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3962033997 |
|
|
Sep 04 06:18:45 AM UTC 24 |
Sep 04 06:19:02 AM UTC 24 |
653049505 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3728410412 |
|
|
Sep 04 06:18:34 AM UTC 24 |
Sep 04 06:19:02 AM UTC 24 |
895359753 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.3939106363 |
|
|
Sep 04 06:18:28 AM UTC 24 |
Sep 04 06:19:03 AM UTC 24 |
540103947 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2319823515 |
|
|
Sep 04 06:18:52 AM UTC 24 |
Sep 04 06:19:03 AM UTC 24 |
493282823 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.382674774 |
|
|
Sep 04 06:19:00 AM UTC 24 |
Sep 04 06:19:05 AM UTC 24 |
102399995 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1503552517 |
|
|
Sep 04 06:18:52 AM UTC 24 |
Sep 04 06:19:06 AM UTC 24 |
591686763 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2245219005 |
|
|
Sep 04 06:18:42 AM UTC 24 |
Sep 04 06:19:06 AM UTC 24 |
679080337 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.447282823 |
|
|
Sep 04 06:18:53 AM UTC 24 |
Sep 04 06:19:06 AM UTC 24 |
619253041 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1005180095 |
|
|
Sep 04 06:18:53 AM UTC 24 |
Sep 04 06:19:06 AM UTC 24 |
292637705 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.3447352080 |
|
|
Sep 04 06:19:04 AM UTC 24 |
Sep 04 06:19:07 AM UTC 24 |
63138192 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.3713156112 |
|
|
Sep 04 06:19:00 AM UTC 24 |
Sep 04 06:19:08 AM UTC 24 |
961547805 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2539873335 |
|
|
Sep 04 06:19:04 AM UTC 24 |
Sep 04 06:19:08 AM UTC 24 |
54768125 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.373284066 |
|
|
Sep 04 06:19:00 AM UTC 24 |
Sep 04 06:19:08 AM UTC 24 |
214801352 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2477997183 |
|
|
Sep 04 06:19:07 AM UTC 24 |
Sep 04 06:19:09 AM UTC 24 |
22348278 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2517428674 |
|
|
Sep 04 06:18:54 AM UTC 24 |
Sep 04 06:19:09 AM UTC 24 |
259743914 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.3855563145 |
|
|
Sep 04 06:19:01 AM UTC 24 |
Sep 04 06:19:11 AM UTC 24 |
409030458 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.2909728803 |
|
|
Sep 04 06:19:30 AM UTC 24 |
Sep 04 06:19:34 AM UTC 24 |
922846539 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1805240457 |
|
|
Sep 04 06:19:07 AM UTC 24 |
Sep 04 06:19:11 AM UTC 24 |
212399133 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.477815050 |
|
|
Sep 04 06:16:49 AM UTC 24 |
Sep 04 06:19:12 AM UTC 24 |
19409328979 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.523488468 |
|
|
Sep 04 06:19:00 AM UTC 24 |
Sep 04 06:19:12 AM UTC 24 |
228976070 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.3525654869 |
|
|
Sep 04 06:19:09 AM UTC 24 |
Sep 04 06:19:13 AM UTC 24 |
94643407 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1053193079 |
|
|
Sep 04 06:19:12 AM UTC 24 |
Sep 04 06:19:14 AM UTC 24 |
41657846 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.574603147 |
|
|
Sep 04 06:19:12 AM UTC 24 |
Sep 04 06:19:15 AM UTC 24 |
90437635 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.4017880542 |
|
|
Sep 04 06:19:03 AM UTC 24 |
Sep 04 06:19:15 AM UTC 24 |
643700469 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.76157796 |
|
|
Sep 04 06:19:30 AM UTC 24 |
Sep 04 06:19:35 AM UTC 24 |
198404438 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.1888922299 |
|
|
Sep 04 06:19:01 AM UTC 24 |
Sep 04 06:19:17 AM UTC 24 |
1125924732 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.394542522 |
|
|
Sep 04 06:19:07 AM UTC 24 |
Sep 04 06:19:18 AM UTC 24 |
61560439 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1318669929 |
|
|
Sep 04 06:19:12 AM UTC 24 |
Sep 04 06:19:18 AM UTC 24 |
50703618 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.3670746863 |
|
|
Sep 04 06:18:49 AM UTC 24 |
Sep 04 06:19:18 AM UTC 24 |
1771309515 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.2586923608 |
|
|
Sep 04 06:19:13 AM UTC 24 |
Sep 04 06:19:19 AM UTC 24 |
525923850 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2318407928 |
|
|
Sep 04 06:18:45 AM UTC 24 |
Sep 04 06:19:19 AM UTC 24 |
1203265332 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.3920050680 |
|
|
Sep 04 06:19:17 AM UTC 24 |
Sep 04 06:19:20 AM UTC 24 |
83763292 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.3087180505 |
|
|
Sep 04 06:19:03 AM UTC 24 |
Sep 04 06:19:21 AM UTC 24 |
723842127 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3875125423 |
|
|
Sep 04 06:19:07 AM UTC 24 |
Sep 04 06:19:21 AM UTC 24 |
1224288374 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.1245670172 |
|
|
Sep 04 06:19:08 AM UTC 24 |
Sep 04 06:19:21 AM UTC 24 |
1298535043 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.3251946384 |
|
|
Sep 04 06:19:13 AM UTC 24 |
Sep 04 06:19:35 AM UTC 24 |
260587301 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.213994875 |
|
|
Sep 04 06:19:09 AM UTC 24 |
Sep 04 06:19:21 AM UTC 24 |
1145434806 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.2482206610 |
|
|
Sep 04 06:19:20 AM UTC 24 |
Sep 04 06:19:22 AM UTC 24 |
19860130 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3160710358 |
|
|
Sep 04 06:18:31 AM UTC 24 |
Sep 04 06:19:22 AM UTC 24 |
3182686024 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1395635883 |
|
|
Sep 04 06:19:20 AM UTC 24 |
Sep 04 06:19:23 AM UTC 24 |
154152040 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3672473675 |
|
|
Sep 04 06:19:21 AM UTC 24 |
Sep 04 06:19:23 AM UTC 24 |
10907387 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.507999019 |
|
|
Sep 04 06:19:22 AM UTC 24 |
Sep 04 06:19:36 AM UTC 24 |
1197946485 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.4173041214 |
|
|
Sep 04 06:19:13 AM UTC 24 |
Sep 04 06:19:24 AM UTC 24 |
151324409 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.2554941248 |
|
|
Sep 04 06:19:15 AM UTC 24 |
Sep 04 06:19:24 AM UTC 24 |
410980372 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.4054913094 |
|
|
Sep 04 06:19:09 AM UTC 24 |
Sep 04 06:19:25 AM UTC 24 |
6212541304 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.2222605999 |
|
|
Sep 04 06:19:24 AM UTC 24 |
Sep 04 06:19:36 AM UTC 24 |
570900180 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.3959680135 |
|
|
Sep 04 06:19:22 AM UTC 24 |
Sep 04 06:19:26 AM UTC 24 |
73878464 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.393022593 |
|
|
Sep 04 06:19:15 AM UTC 24 |
Sep 04 06:19:27 AM UTC 24 |
374318360 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.3570566183 |
|
|
Sep 04 06:16:42 AM UTC 24 |
Sep 04 06:19:27 AM UTC 24 |
5569201501 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.2459504105 |
|
|
Sep 04 06:19:18 AM UTC 24 |
Sep 04 06:19:28 AM UTC 24 |
179839966 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.2457084078 |
|
|
Sep 04 06:19:18 AM UTC 24 |
Sep 04 06:19:28 AM UTC 24 |
622017690 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2098180875 |
|
|
Sep 04 06:19:26 AM UTC 24 |
Sep 04 06:19:29 AM UTC 24 |
68770189 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.1763602310 |
|
|
Sep 04 06:19:00 AM UTC 24 |
Sep 04 06:19:29 AM UTC 24 |
969871327 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2489644297 |
|
|
Sep 04 06:19:09 AM UTC 24 |
Sep 04 06:19:29 AM UTC 24 |
2690528537 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2571266272 |
|
|
Sep 04 06:19:22 AM UTC 24 |
Sep 04 06:19:30 AM UTC 24 |
340325833 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1750529771 |
|
|
Sep 04 06:19:18 AM UTC 24 |
Sep 04 06:19:31 AM UTC 24 |
266365909 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.3085858873 |
|
|
Sep 04 06:20:03 AM UTC 24 |
Sep 04 06:20:27 AM UTC 24 |
2455860178 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.3014761174 |
|
|
Sep 04 06:19:23 AM UTC 24 |
Sep 04 06:19:36 AM UTC 24 |
1824755181 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.1813550711 |
|
|
Sep 04 06:17:59 AM UTC 24 |
Sep 04 06:19:38 AM UTC 24 |
28008444343 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.227062079 |
|
|
Sep 04 06:19:36 AM UTC 24 |
Sep 04 06:19:38 AM UTC 24 |
30391547 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3185017636 |
|
|
Sep 04 06:19:37 AM UTC 24 |
Sep 04 06:19:40 AM UTC 24 |
46059792 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2983514911 |
|
|
Sep 04 06:20:02 AM UTC 24 |
Sep 04 06:20:23 AM UTC 24 |
914131882 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2535761232 |
|
|
Sep 04 06:19:07 AM UTC 24 |
Sep 04 06:19:40 AM UTC 24 |
3102875559 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.2237663061 |
|
|
Sep 04 06:19:33 AM UTC 24 |
Sep 04 06:19:40 AM UTC 24 |
206003781 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.2827073646 |
|
|
Sep 04 06:19:29 AM UTC 24 |
Sep 04 06:19:41 AM UTC 24 |
373271868 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2992937887 |
|
|
Sep 04 06:20:11 AM UTC 24 |
Sep 04 06:20:24 AM UTC 24 |
215899281 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3728028934 |
|
|
Sep 04 06:19:22 AM UTC 24 |
Sep 04 06:19:41 AM UTC 24 |
1034539263 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.788436030 |
|
|
Sep 04 06:19:24 AM UTC 24 |
Sep 04 06:19:41 AM UTC 24 |
347511632 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1976417970 |
|
|
Sep 04 06:19:24 AM UTC 24 |
Sep 04 06:19:42 AM UTC 24 |
408126121 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.2075305369 |
|
|
Sep 04 06:19:39 AM UTC 24 |
Sep 04 06:19:42 AM UTC 24 |
40789501 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3276558601 |
|
|
Sep 04 06:19:25 AM UTC 24 |
Sep 04 06:19:42 AM UTC 24 |
1306936600 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1514814737 |
|
|
Sep 04 06:19:37 AM UTC 24 |
Sep 04 06:19:43 AM UTC 24 |
219350314 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2151284094 |
|
|
Sep 04 06:19:43 AM UTC 24 |
Sep 04 06:19:45 AM UTC 24 |
15316938 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2800671964 |
|
|
Sep 04 06:19:43 AM UTC 24 |
Sep 04 06:19:45 AM UTC 24 |
35086325 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2531304952 |
|
|
Sep 04 06:18:32 AM UTC 24 |
Sep 04 06:19:46 AM UTC 24 |
15759823914 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2967639987 |
|
|
Sep 04 06:19:30 AM UTC 24 |
Sep 04 06:19:48 AM UTC 24 |
780087471 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.641690760 |
|
|
Sep 04 06:19:33 AM UTC 24 |
Sep 04 06:19:48 AM UTC 24 |
1253429132 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.2260044258 |
|
|
Sep 04 06:19:43 AM UTC 24 |
Sep 04 06:19:48 AM UTC 24 |
60991286 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.1099837163 |
|
|
Sep 04 06:19:39 AM UTC 24 |
Sep 04 06:19:48 AM UTC 24 |
138217000 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2188038822 |
|
|
Sep 04 06:19:25 AM UTC 24 |
Sep 04 06:20:24 AM UTC 24 |
3391069402 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.2713787326 |
|
|
Sep 04 06:19:46 AM UTC 24 |
Sep 04 06:19:49 AM UTC 24 |
107472940 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.1858553523 |
|
|
Sep 04 06:19:30 AM UTC 24 |
Sep 04 06:19:50 AM UTC 24 |
1676777982 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1040908584 |
|
|
Sep 04 06:19:29 AM UTC 24 |
Sep 04 06:19:51 AM UTC 24 |
677552243 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.685415570 |
|
|
Sep 04 06:19:41 AM UTC 24 |
Sep 04 06:19:51 AM UTC 24 |
1531622805 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.2277355024 |
|
|
Sep 04 06:19:41 AM UTC 24 |
Sep 04 06:19:52 AM UTC 24 |
3261878209 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1110371964 |
|
|
Sep 04 06:17:51 AM UTC 24 |
Sep 04 06:20:25 AM UTC 24 |
8646485712 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.856994791 |
|
|
Sep 04 06:19:41 AM UTC 24 |
Sep 04 06:19:53 AM UTC 24 |
385664857 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2351105521 |
|
|
Sep 04 06:19:33 AM UTC 24 |
Sep 04 06:19:54 AM UTC 24 |
1479537737 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.375537291 |
|
|
Sep 04 06:18:39 AM UTC 24 |
Sep 04 06:19:54 AM UTC 24 |
1499660212 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.1097497582 |
|
|
Sep 04 06:19:46 AM UTC 24 |
Sep 04 06:19:54 AM UTC 24 |
104748151 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.137294936 |
|
|
Sep 04 06:19:52 AM UTC 24 |
Sep 04 06:19:55 AM UTC 24 |
73950451 ps |