| T815 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.967988095 |
|
|
Sep 04 06:19:53 AM UTC 24 |
Sep 04 06:19:56 AM UTC 24 |
134805103 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3758941379 |
|
|
Sep 04 06:19:52 AM UTC 24 |
Sep 04 06:19:56 AM UTC 24 |
45556141 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.2849802586 |
|
|
Sep 04 06:15:11 AM UTC 24 |
Sep 04 06:19:57 AM UTC 24 |
9480845933 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.310995893 |
|
|
Sep 04 06:19:50 AM UTC 24 |
Sep 04 06:19:58 AM UTC 24 |
1105745312 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.2753719754 |
|
|
Sep 04 06:14:10 AM UTC 24 |
Sep 04 06:19:58 AM UTC 24 |
37089564546 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.3688066825 |
|
|
Sep 04 06:19:41 AM UTC 24 |
Sep 04 06:19:58 AM UTC 24 |
5201124417 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.3559212405 |
|
|
Sep 04 06:20:11 AM UTC 24 |
Sep 04 06:20:22 AM UTC 24 |
391432899 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.948433694 |
|
|
Sep 04 06:20:02 AM UTC 24 |
Sep 04 06:20:26 AM UTC 24 |
8592173871 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.127537536 |
|
|
Sep 04 06:19:50 AM UTC 24 |
Sep 04 06:19:59 AM UTC 24 |
1361934060 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.871227600 |
|
|
Sep 04 06:19:48 AM UTC 24 |
Sep 04 06:20:00 AM UTC 24 |
252844620 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.4045634261 |
|
|
Sep 04 06:19:37 AM UTC 24 |
Sep 04 06:20:00 AM UTC 24 |
149378954 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2487097004 |
|
|
Sep 04 06:19:46 AM UTC 24 |
Sep 04 06:20:01 AM UTC 24 |
3114398026 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3698287884 |
|
|
Sep 04 06:19:56 AM UTC 24 |
Sep 04 06:20:01 AM UTC 24 |
558849331 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.1053758856 |
|
|
Sep 04 06:19:55 AM UTC 24 |
Sep 04 06:20:01 AM UTC 24 |
360789287 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2105781030 |
|
|
Sep 04 06:19:41 AM UTC 24 |
Sep 04 06:20:01 AM UTC 24 |
2502245441 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.3317972021 |
|
|
Sep 04 06:19:48 AM UTC 24 |
Sep 04 06:20:02 AM UTC 24 |
657222665 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3141452473 |
|
|
Sep 04 06:20:00 AM UTC 24 |
Sep 04 06:20:02 AM UTC 24 |
53440196 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3265526073 |
|
|
Sep 04 06:20:00 AM UTC 24 |
Sep 04 06:20:03 AM UTC 24 |
21988201 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.3783100291 |
|
|
Sep 04 06:20:00 AM UTC 24 |
Sep 04 06:20:03 AM UTC 24 |
168689305 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3044927808 |
|
|
Sep 04 06:19:55 AM UTC 24 |
Sep 04 06:20:04 AM UTC 24 |
829120098 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.3143215367 |
|
|
Sep 04 06:19:43 AM UTC 24 |
Sep 04 06:20:06 AM UTC 24 |
830325811 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.901545798 |
|
|
Sep 04 06:19:55 AM UTC 24 |
Sep 04 06:20:07 AM UTC 24 |
287128824 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.227524917 |
|
|
Sep 04 06:20:03 AM UTC 24 |
Sep 04 06:20:07 AM UTC 24 |
54500016 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.348168031 |
|
|
Sep 04 06:20:02 AM UTC 24 |
Sep 04 06:20:08 AM UTC 24 |
169881512 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3145746219 |
|
|
Sep 04 06:18:18 AM UTC 24 |
Sep 04 06:20:08 AM UTC 24 |
6228881703 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.788755837 |
|
|
Sep 04 06:19:57 AM UTC 24 |
Sep 04 06:20:09 AM UTC 24 |
243277257 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.4197774319 |
|
|
Sep 04 06:20:12 AM UTC 24 |
Sep 04 06:20:27 AM UTC 24 |
483876390 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.235490788 |
|
|
Sep 04 06:20:07 AM UTC 24 |
Sep 04 06:20:09 AM UTC 24 |
21693495 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.3564365301 |
|
|
Sep 04 06:19:49 AM UTC 24 |
Sep 04 06:20:09 AM UTC 24 |
7160753162 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.3099701938 |
|
|
Sep 04 06:19:55 AM UTC 24 |
Sep 04 06:20:10 AM UTC 24 |
3165959805 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.986988572 |
|
|
Sep 04 06:19:57 AM UTC 24 |
Sep 04 06:20:11 AM UTC 24 |
978879271 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3359828447 |
|
|
Sep 04 06:20:08 AM UTC 24 |
Sep 04 06:20:11 AM UTC 24 |
42508437 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.579866587 |
|
|
Sep 04 06:20:08 AM UTC 24 |
Sep 04 06:20:11 AM UTC 24 |
31339689 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1959004441 |
|
|
Sep 04 06:20:03 AM UTC 24 |
Sep 04 06:20:12 AM UTC 24 |
439026015 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.3328799691 |
|
|
Sep 04 06:19:44 AM UTC 24 |
Sep 04 06:20:13 AM UTC 24 |
708796275 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.21385696 |
|
|
Sep 04 06:20:10 AM UTC 24 |
Sep 04 06:20:14 AM UTC 24 |
62790744 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.3036339545 |
|
|
Sep 04 06:20:02 AM UTC 24 |
Sep 04 06:20:14 AM UTC 24 |
432795658 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.1343966903 |
|
|
Sep 04 06:20:10 AM UTC 24 |
Sep 04 06:20:14 AM UTC 24 |
54457393 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3918649637 |
|
|
Sep 04 06:19:58 AM UTC 24 |
Sep 04 06:20:15 AM UTC 24 |
1683815118 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.1154489760 |
|
|
Sep 04 06:20:15 AM UTC 24 |
Sep 04 06:20:17 AM UTC 24 |
15645864 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.281692893 |
|
|
Sep 04 06:20:03 AM UTC 24 |
Sep 04 06:20:18 AM UTC 24 |
258783730 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1289313482 |
|
|
Sep 04 06:20:02 AM UTC 24 |
Sep 04 06:20:19 AM UTC 24 |
311926571 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1551262375 |
|
|
Sep 04 06:19:53 AM UTC 24 |
Sep 04 06:20:21 AM UTC 24 |
390618538 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.3681286039 |
|
|
Sep 04 06:20:11 AM UTC 24 |
Sep 04 06:20:22 AM UTC 24 |
902978618 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.3554052224 |
|
|
Sep 04 06:20:10 AM UTC 24 |
Sep 04 06:20:27 AM UTC 24 |
2810909694 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2859303586 |
|
|
Sep 04 06:20:11 AM UTC 24 |
Sep 04 06:20:27 AM UTC 24 |
2861209670 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.1767961872 |
|
|
Sep 04 06:18:08 AM UTC 24 |
Sep 04 06:20:28 AM UTC 24 |
7844721354 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.2275594169 |
|
|
Sep 04 06:20:09 AM UTC 24 |
Sep 04 06:20:35 AM UTC 24 |
404016843 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1156918474 |
|
|
Sep 04 06:18:16 AM UTC 24 |
Sep 04 06:20:42 AM UTC 24 |
26290241320 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.308288009 |
|
|
Sep 04 06:19:03 AM UTC 24 |
Sep 04 06:20:44 AM UTC 24 |
18894683866 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.2965679020 |
|
|
Sep 04 06:19:36 AM UTC 24 |
Sep 04 06:20:54 AM UTC 24 |
4408508189 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2638997187 |
|
|
Sep 04 06:20:00 AM UTC 24 |
Sep 04 06:21:01 AM UTC 24 |
6801109945 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.1989575819 |
|
|
Sep 04 06:20:00 AM UTC 24 |
Sep 04 06:21:08 AM UTC 24 |
1311374093 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3912346035 |
|
|
Sep 04 06:19:26 AM UTC 24 |
Sep 04 06:21:11 AM UTC 24 |
3626112731 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.4110213210 |
|
|
Sep 04 06:19:20 AM UTC 24 |
Sep 04 06:21:23 AM UTC 24 |
71859072169 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3286826723 |
|
|
Sep 04 06:17:29 AM UTC 24 |
Sep 04 06:21:34 AM UTC 24 |
13205335229 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.988514601 |
|
|
Sep 04 06:19:51 AM UTC 24 |
Sep 04 06:21:44 AM UTC 24 |
10697902909 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2791642534 |
|
|
Sep 04 06:19:10 AM UTC 24 |
Sep 04 06:22:14 AM UTC 24 |
29272672123 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3185068407 |
|
|
Sep 04 06:19:43 AM UTC 24 |
Sep 04 06:22:30 AM UTC 24 |
13137109464 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.358456704 |
|
|
Sep 04 06:20:06 AM UTC 24 |
Sep 04 06:22:33 AM UTC 24 |
17046587570 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.136068450 |
|
|
Sep 04 06:18:54 AM UTC 24 |
Sep 04 06:23:24 AM UTC 24 |
18002767227 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.4185569114 |
|
|
Sep 04 06:17:06 AM UTC 24 |
Sep 04 06:25:57 AM UTC 24 |
16838640833 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3168907624 |
|
|
Sep 04 06:20:04 AM UTC 24 |
Sep 04 06:26:12 AM UTC 24 |
88941393387 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.3922765735 |
|
|
Sep 04 06:20:12 AM UTC 24 |
Sep 04 06:29:36 AM UTC 24 |
78150297787 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.791093441 |
|
|
Sep 04 06:19:50 AM UTC 24 |
Sep 04 06:31:03 AM UTC 24 |
79558740170 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.2624038395 |
|
|
Sep 04 06:16:22 AM UTC 24 |
Sep 04 06:33:08 AM UTC 24 |
131966169940 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.775643839 |
|
|
Sep 04 06:20:15 AM UTC 24 |
Sep 04 06:20:17 AM UTC 24 |
34598042 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2375673399 |
|
|
Sep 04 06:20:15 AM UTC 24 |
Sep 04 06:20:20 AM UTC 24 |
388115343 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.62755648 |
|
|
Sep 04 06:20:18 AM UTC 24 |
Sep 04 06:20:21 AM UTC 24 |
56773712 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1008231831 |
|
|
Sep 04 06:20:19 AM UTC 24 |
Sep 04 06:20:22 AM UTC 24 |
123902860 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1547105954 |
|
|
Sep 04 06:20:22 AM UTC 24 |
Sep 04 06:20:24 AM UTC 24 |
16214346 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1779272248 |
|
|
Sep 04 06:20:22 AM UTC 24 |
Sep 04 06:20:25 AM UTC 24 |
81235687 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.78277753 |
|
|
Sep 04 06:20:23 AM UTC 24 |
Sep 04 06:20:26 AM UTC 24 |
21732022 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.295952808 |
|
|
Sep 04 06:20:23 AM UTC 24 |
Sep 04 06:20:26 AM UTC 24 |
48692889 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.891657632 |
|
|
Sep 04 06:20:21 AM UTC 24 |
Sep 04 06:20:27 AM UTC 24 |
468464731 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3069271195 |
|
|
Sep 04 06:20:23 AM UTC 24 |
Sep 04 06:20:27 AM UTC 24 |
47835660 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1137276399 |
|
|
Sep 04 06:20:24 AM UTC 24 |
Sep 04 06:20:27 AM UTC 24 |
27443027 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3725295086 |
|
|
Sep 04 06:20:21 AM UTC 24 |
Sep 04 06:20:28 AM UTC 24 |
231344419 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3140341155 |
|
|
Sep 04 06:20:18 AM UTC 24 |
Sep 04 06:20:28 AM UTC 24 |
5839286814 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1811715868 |
|
|
Sep 04 06:20:24 AM UTC 24 |
Sep 04 06:20:28 AM UTC 24 |
384923300 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2561458848 |
|
|
Sep 04 06:20:26 AM UTC 24 |
Sep 04 06:20:28 AM UTC 24 |
35242272 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1933833701 |
|
|
Sep 04 06:20:16 AM UTC 24 |
Sep 04 06:20:30 AM UTC 24 |
962998763 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2231741164 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:31 AM UTC 24 |
22865831 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3816920779 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:31 AM UTC 24 |
14426330 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2184650042 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:31 AM UTC 24 |
69617306 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2784667234 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:31 AM UTC 24 |
53865386 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.757105601 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:31 AM UTC 24 |
27111825 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2450238919 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:31 AM UTC 24 |
33241816 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.393531814 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:32 AM UTC 24 |
224888557 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3988510682 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:32 AM UTC 24 |
60529983 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1847142920 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:33 AM UTC 24 |
125454508 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2042511797 |
|
|
Sep 04 06:20:30 AM UTC 24 |
Sep 04 06:20:33 AM UTC 24 |
148732557 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1999642844 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:33 AM UTC 24 |
214906292 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.485586757 |
|
|
Sep 04 06:20:26 AM UTC 24 |
Sep 04 06:20:33 AM UTC 24 |
1044028728 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2814710249 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:34 AM UTC 24 |
180989779 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.982085950 |
|
|
Sep 04 06:20:30 AM UTC 24 |
Sep 04 06:20:34 AM UTC 24 |
68756865 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3461976288 |
|
|
Sep 04 06:20:32 AM UTC 24 |
Sep 04 06:20:34 AM UTC 24 |
13180580 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.63788918 |
|
|
Sep 04 06:20:32 AM UTC 24 |
Sep 04 06:20:35 AM UTC 24 |
18641057 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4195950698 |
|
|
Sep 04 06:20:41 AM UTC 24 |
Sep 04 06:20:43 AM UTC 24 |
21115556 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4282937947 |
|
|
Sep 04 06:20:32 AM UTC 24 |
Sep 04 06:20:35 AM UTC 24 |
46465463 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1844659459 |
|
|
Sep 04 06:20:32 AM UTC 24 |
Sep 04 06:20:35 AM UTC 24 |
256227022 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.179845692 |
|
|
Sep 04 06:20:16 AM UTC 24 |
Sep 04 06:20:35 AM UTC 24 |
4306623805 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3871263243 |
|
|
Sep 04 06:20:32 AM UTC 24 |
Sep 04 06:20:35 AM UTC 24 |
42508739 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1415572697 |
|
|
Sep 04 06:20:34 AM UTC 24 |
Sep 04 06:20:36 AM UTC 24 |
90546275 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.197283797 |
|
|
Sep 04 06:20:33 AM UTC 24 |
Sep 04 06:20:36 AM UTC 24 |
17182278 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2489484679 |
|
|
Sep 04 06:20:33 AM UTC 24 |
Sep 04 06:20:36 AM UTC 24 |
198107396 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1856164018 |
|
|
Sep 04 06:20:33 AM UTC 24 |
Sep 04 06:20:37 AM UTC 24 |
42657924 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1615831887 |
|
|
Sep 04 06:20:32 AM UTC 24 |
Sep 04 06:20:37 AM UTC 24 |
195325838 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3568172698 |
|
|
Sep 04 06:20:28 AM UTC 24 |
Sep 04 06:20:37 AM UTC 24 |
170522195 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.571399524 |
|
|
Sep 04 06:20:35 AM UTC 24 |
Sep 04 06:20:37 AM UTC 24 |
254512061 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3094239310 |
|
|
Sep 04 06:20:35 AM UTC 24 |
Sep 04 06:20:38 AM UTC 24 |
40541735 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4095400935 |
|
|
Sep 04 06:20:36 AM UTC 24 |
Sep 04 06:20:38 AM UTC 24 |
79118742 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2940017279 |
|
|
Sep 04 06:20:36 AM UTC 24 |
Sep 04 06:20:39 AM UTC 24 |
14033479 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1751265170 |
|
|
Sep 04 06:20:31 AM UTC 24 |
Sep 04 06:20:39 AM UTC 24 |
1690933546 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3949198249 |
|
|
Sep 04 06:20:36 AM UTC 24 |
Sep 04 06:20:39 AM UTC 24 |
25901427 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2877572115 |
|
|
Sep 04 06:20:36 AM UTC 24 |
Sep 04 06:20:39 AM UTC 24 |
264540644 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3374383990 |
|
|
Sep 04 06:20:36 AM UTC 24 |
Sep 04 06:20:39 AM UTC 24 |
249174532 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2278950217 |
|
|
Sep 04 06:20:36 AM UTC 24 |
Sep 04 06:20:39 AM UTC 24 |
55264245 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2570977157 |
|
|
Sep 04 06:20:30 AM UTC 24 |
Sep 04 06:20:40 AM UTC 24 |
1320880634 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.72788676 |
|
|
Sep 04 06:20:36 AM UTC 24 |
Sep 04 06:20:40 AM UTC 24 |
343554167 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.777360082 |
|
|
Sep 04 06:20:38 AM UTC 24 |
Sep 04 06:20:40 AM UTC 24 |
23944909 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1713914099 |
|
|
Sep 04 06:20:38 AM UTC 24 |
Sep 04 06:20:40 AM UTC 24 |
39377570 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2919809439 |
|
|
Sep 04 06:20:38 AM UTC 24 |
Sep 04 06:20:40 AM UTC 24 |
24997493 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4129622669 |
|
|
Sep 04 06:20:38 AM UTC 24 |
Sep 04 06:20:41 AM UTC 24 |
113254516 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3997331515 |
|
|
Sep 04 06:20:38 AM UTC 24 |
Sep 04 06:20:41 AM UTC 24 |
189395119 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2309817772 |
|
|
Sep 04 06:20:39 AM UTC 24 |
Sep 04 06:20:41 AM UTC 24 |
47166385 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1192897306 |
|
|
Sep 04 06:20:39 AM UTC 24 |
Sep 04 06:20:42 AM UTC 24 |
107444760 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1913659524 |
|
|
Sep 04 06:20:35 AM UTC 24 |
Sep 04 06:20:42 AM UTC 24 |
479602211 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1262513501 |
|
|
Sep 04 06:20:40 AM UTC 24 |
Sep 04 06:20:43 AM UTC 24 |
40350450 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1494750718 |
|
|
Sep 04 06:20:40 AM UTC 24 |
Sep 04 06:20:43 AM UTC 24 |
34191186 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3737626300 |
|
|
Sep 04 06:20:40 AM UTC 24 |
Sep 04 06:20:43 AM UTC 24 |
116621899 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.199314454 |
|
|
Sep 04 06:20:41 AM UTC 24 |
Sep 04 06:20:44 AM UTC 24 |
295549048 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2994365960 |
|
|
Sep 04 06:20:40 AM UTC 24 |
Sep 04 06:20:44 AM UTC 24 |
284018248 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.670406042 |
|
|
Sep 04 06:20:42 AM UTC 24 |
Sep 04 06:20:44 AM UTC 24 |
236745171 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.48867649 |
|
|
Sep 04 06:20:40 AM UTC 24 |
Sep 04 06:20:45 AM UTC 24 |
66609042 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1426562265 |
|
|
Sep 04 06:20:40 AM UTC 24 |
Sep 04 06:20:45 AM UTC 24 |
105625035 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3952251475 |
|
|
Sep 04 06:20:42 AM UTC 24 |
Sep 04 06:20:45 AM UTC 24 |
157473075 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4114012872 |
|
|
Sep 04 06:20:40 AM UTC 24 |
Sep 04 06:20:46 AM UTC 24 |
120259057 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2658421135 |
|
|
Sep 04 06:20:44 AM UTC 24 |
Sep 04 06:20:46 AM UTC 24 |
20727583 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2264467351 |
|
|
Sep 04 06:20:39 AM UTC 24 |
Sep 04 06:20:46 AM UTC 24 |
1617976194 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.503403711 |
|
|
Sep 04 06:20:44 AM UTC 24 |
Sep 04 06:20:46 AM UTC 24 |
32232643 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2555437278 |
|
|
Sep 04 06:20:44 AM UTC 24 |
Sep 04 06:20:47 AM UTC 24 |
341702783 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3502882009 |
|
|
Sep 04 06:20:44 AM UTC 24 |
Sep 04 06:20:47 AM UTC 24 |
67297442 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4057016487 |
|
|
Sep 04 06:20:41 AM UTC 24 |
Sep 04 06:20:47 AM UTC 24 |
175191967 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.394507576 |
|
|
Sep 04 06:20:42 AM UTC 24 |
Sep 04 06:20:48 AM UTC 24 |
133276217 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1687393779 |
|
|
Sep 04 06:20:44 AM UTC 24 |
Sep 04 06:20:48 AM UTC 24 |
154968719 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4118328531 |
|
|
Sep 04 06:20:44 AM UTC 24 |
Sep 04 06:20:48 AM UTC 24 |
81827909 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3731966468 |
|
|
Sep 04 06:20:42 AM UTC 24 |
Sep 04 06:20:48 AM UTC 24 |
378136745 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.94876337 |
|
|
Sep 04 06:20:26 AM UTC 24 |
Sep 04 06:20:48 AM UTC 24 |
2909717760 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.893105567 |
|
|
Sep 04 06:20:46 AM UTC 24 |
Sep 04 06:20:48 AM UTC 24 |
24016109 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2578733237 |
|
|
Sep 04 06:20:46 AM UTC 24 |
Sep 04 06:20:48 AM UTC 24 |
169441117 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2207093990 |
|
|
Sep 04 06:20:45 AM UTC 24 |
Sep 04 06:20:49 AM UTC 24 |
390278305 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.61614784 |
|
|
Sep 04 06:20:47 AM UTC 24 |
Sep 04 06:20:49 AM UTC 24 |
66098495 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2945914878 |
|
|
Sep 04 06:20:47 AM UTC 24 |
Sep 04 06:20:49 AM UTC 24 |
41976354 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3375055736 |
|
|
Sep 04 06:20:47 AM UTC 24 |
Sep 04 06:20:49 AM UTC 24 |
321796383 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4113964618 |
|
|
Sep 04 06:20:44 AM UTC 24 |
Sep 04 06:20:50 AM UTC 24 |
205688901 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3998136594 |
|
|
Sep 04 06:20:46 AM UTC 24 |
Sep 04 06:20:50 AM UTC 24 |
623578443 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2473444683 |
|
|
Sep 04 06:20:48 AM UTC 24 |
Sep 04 06:20:51 AM UTC 24 |
15954822 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2607781712 |
|
|
Sep 04 06:20:47 AM UTC 24 |
Sep 04 06:20:51 AM UTC 24 |
45231168 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.393536620 |
|
|
Sep 04 06:20:48 AM UTC 24 |
Sep 04 06:20:51 AM UTC 24 |
54927105 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.566203258 |
|
|
Sep 04 06:20:50 AM UTC 24 |
Sep 04 06:20:52 AM UTC 24 |
40758222 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1759544759 |
|
|
Sep 04 06:20:30 AM UTC 24 |
Sep 04 06:20:52 AM UTC 24 |
4144745359 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1148835232 |
|
|
Sep 04 06:20:50 AM UTC 24 |
Sep 04 06:20:53 AM UTC 24 |
22987898 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.736222669 |
|
|
Sep 04 06:20:46 AM UTC 24 |
Sep 04 06:20:53 AM UTC 24 |
1961524545 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3383994622 |
|
|
Sep 04 06:20:50 AM UTC 24 |
Sep 04 06:20:53 AM UTC 24 |
890659353 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1342149244 |
|
|
Sep 04 06:20:50 AM UTC 24 |
Sep 04 06:20:53 AM UTC 24 |
49231065 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4193147370 |
|
|
Sep 04 06:20:51 AM UTC 24 |
Sep 04 06:20:54 AM UTC 24 |
248446428 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.256265491 |
|
|
Sep 04 06:20:50 AM UTC 24 |
Sep 04 06:20:55 AM UTC 24 |
45381799 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3676198363 |
|
|
Sep 04 06:20:50 AM UTC 24 |
Sep 04 06:20:55 AM UTC 24 |
301054699 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3264061358 |
|
|
Sep 04 06:20:48 AM UTC 24 |
Sep 04 06:20:55 AM UTC 24 |
679402290 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1298850952 |
|
|
Sep 04 06:20:52 AM UTC 24 |
Sep 04 06:20:55 AM UTC 24 |
71233900 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.329626696 |
|
|
Sep 04 06:20:52 AM UTC 24 |
Sep 04 06:20:56 AM UTC 24 |
69212199 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3245571871 |
|
|
Sep 04 06:20:52 AM UTC 24 |
Sep 04 06:20:56 AM UTC 24 |
371086099 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1606900392 |
|
|
Sep 04 06:20:52 AM UTC 24 |
Sep 04 06:20:56 AM UTC 24 |
150085720 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1742716470 |
|
|
Sep 04 06:20:54 AM UTC 24 |
Sep 04 06:20:56 AM UTC 24 |
17403628 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2350776275 |
|
|
Sep 04 06:20:51 AM UTC 24 |
Sep 04 06:20:56 AM UTC 24 |
93535425 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.256218376 |
|
|
Sep 04 06:20:54 AM UTC 24 |
Sep 04 06:20:56 AM UTC 24 |
65791535 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3890324088 |
|
|
Sep 04 06:20:48 AM UTC 24 |
Sep 04 06:20:56 AM UTC 24 |
187602182 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2837838690 |
|
|
Sep 04 06:20:48 AM UTC 24 |
Sep 04 06:20:56 AM UTC 24 |
411632211 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1463903449 |
|
|
Sep 04 06:20:54 AM UTC 24 |
Sep 04 06:20:57 AM UTC 24 |
421266387 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4124621011 |
|
|
Sep 04 06:20:35 AM UTC 24 |
Sep 04 06:20:57 AM UTC 24 |
828443220 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1044989377 |
|
|
Sep 04 06:20:54 AM UTC 24 |
Sep 04 06:20:58 AM UTC 24 |
108015155 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1859734268 |
|
|
Sep 04 06:20:51 AM UTC 24 |
Sep 04 06:20:58 AM UTC 24 |
1655511218 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.127269144 |
|
|
Sep 04 06:20:54 AM UTC 24 |
Sep 04 06:20:58 AM UTC 24 |
349996071 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2671221341 |
|
|
Sep 04 06:20:55 AM UTC 24 |
Sep 04 06:20:58 AM UTC 24 |
43909981 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.854811213 |
|
|
Sep 04 06:20:42 AM UTC 24 |
Sep 04 06:20:58 AM UTC 24 |
7015520106 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1685095455 |
|
|
Sep 04 06:20:56 AM UTC 24 |
Sep 04 06:20:59 AM UTC 24 |
254955806 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2535555852 |
|
|
Sep 04 06:20:57 AM UTC 24 |
Sep 04 06:20:59 AM UTC 24 |
313998798 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.898653498 |
|
|
Sep 04 06:20:57 AM UTC 24 |
Sep 04 06:20:59 AM UTC 24 |
16186605 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1795350784 |
|
|
Sep 04 06:20:56 AM UTC 24 |
Sep 04 06:21:00 AM UTC 24 |
242702824 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.496583434 |
|
|
Sep 04 06:20:57 AM UTC 24 |
Sep 04 06:21:00 AM UTC 24 |
43439405 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.859105703 |
|
|
Sep 04 06:20:56 AM UTC 24 |
Sep 04 06:21:00 AM UTC 24 |
791831430 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3582083776 |
|
|
Sep 04 06:20:58 AM UTC 24 |
Sep 04 06:21:00 AM UTC 24 |
162775580 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.402564536 |
|
|
Sep 04 06:20:58 AM UTC 24 |
Sep 04 06:21:00 AM UTC 24 |
227086070 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.741668578 |
|
|
Sep 04 06:20:57 AM UTC 24 |
Sep 04 06:21:00 AM UTC 24 |
168142207 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4199850067 |
|
|
Sep 04 06:20:58 AM UTC 24 |
Sep 04 06:21:00 AM UTC 24 |
13848861 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3347064799 |
|
|
Sep 04 06:20:58 AM UTC 24 |
Sep 04 06:21:01 AM UTC 24 |
30826300 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2111071773 |
|
|
Sep 04 06:21:04 AM UTC 24 |
Sep 04 06:21:06 AM UTC 24 |
14504183 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3564413329 |
|
|
Sep 04 06:20:46 AM UTC 24 |
Sep 04 06:21:01 AM UTC 24 |
584975657 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1492084895 |
|
|
Sep 04 06:20:38 AM UTC 24 |
Sep 04 06:21:02 AM UTC 24 |
4565814587 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1673617136 |
|
|
Sep 04 06:20:56 AM UTC 24 |
Sep 04 06:21:02 AM UTC 24 |
207832531 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1014740289 |
|
|
Sep 04 06:21:00 AM UTC 24 |
Sep 04 06:21:02 AM UTC 24 |
44623703 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1018144944 |
|
|
Sep 04 06:21:00 AM UTC 24 |
Sep 04 06:21:02 AM UTC 24 |
23270144 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.194328371 |
|
|
Sep 04 06:21:00 AM UTC 24 |
Sep 04 06:21:02 AM UTC 24 |
70695802 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3414880610 |
|
|
Sep 04 06:20:58 AM UTC 24 |
Sep 04 06:21:02 AM UTC 24 |
228504657 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2788698466 |
|
|
Sep 04 06:21:00 AM UTC 24 |
Sep 04 06:21:02 AM UTC 24 |
27856079 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.818717587 |
|
|
Sep 04 06:21:00 AM UTC 24 |
Sep 04 06:21:03 AM UTC 24 |
77167242 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3775996727 |
|
|
Sep 04 06:21:00 AM UTC 24 |
Sep 04 06:21:03 AM UTC 24 |
401010097 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1825538294 |
|
|
Sep 04 06:21:01 AM UTC 24 |
Sep 04 06:21:04 AM UTC 24 |
18039011 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3544215502 |
|
|
Sep 04 06:21:02 AM UTC 24 |
Sep 04 06:21:04 AM UTC 24 |
13503337 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2324445831 |
|
|
Sep 04 06:21:02 AM UTC 24 |
Sep 04 06:21:04 AM UTC 24 |
21872924 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1487138337 |
|
|
Sep 04 06:21:01 AM UTC 24 |
Sep 04 06:21:04 AM UTC 24 |
25119137 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.939033024 |
|
|
Sep 04 06:21:02 AM UTC 24 |
Sep 04 06:21:04 AM UTC 24 |
22070023 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4043582577 |
|
|
Sep 04 06:21:00 AM UTC 24 |
Sep 04 06:21:05 AM UTC 24 |
232611260 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4095574641 |
|
|
Sep 04 06:21:02 AM UTC 24 |
Sep 04 06:21:05 AM UTC 24 |
42537252 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1759634111 |
|
|
Sep 04 06:21:02 AM UTC 24 |
Sep 04 06:21:05 AM UTC 24 |
44311045 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.407096205 |
|
|
Sep 04 06:21:00 AM UTC 24 |
Sep 04 06:21:05 AM UTC 24 |
225963815 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2076794974 |
|
|
Sep 04 06:21:04 AM UTC 24 |
Sep 04 06:21:06 AM UTC 24 |
31353847 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2774040802 |
|
|
Sep 04 06:21:02 AM UTC 24 |
Sep 04 06:21:06 AM UTC 24 |
115732229 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.150372180 |
|
|
Sep 04 06:20:51 AM UTC 24 |
Sep 04 06:21:06 AM UTC 24 |
5132144560 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3678350076 |
|
|
Sep 04 06:21:04 AM UTC 24 |
Sep 04 06:21:06 AM UTC 24 |
16205405 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1065964283 |
|
|
Sep 04 06:21:04 AM UTC 24 |
Sep 04 06:21:06 AM UTC 24 |
53177588 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1030133767 |
|
|
Sep 04 06:21:04 AM UTC 24 |
Sep 04 06:21:06 AM UTC 24 |
29844012 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3803113296 |
|
|
Sep 04 06:21:04 AM UTC 24 |
Sep 04 06:21:06 AM UTC 24 |
33246188 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2990193565 |
|
|
Sep 04 06:21:03 AM UTC 24 |
Sep 04 06:21:07 AM UTC 24 |
202772120 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1766704891 |
|
|
Sep 04 06:20:45 AM UTC 24 |
Sep 04 06:21:07 AM UTC 24 |
3025146830 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.883642249 |
|
|
Sep 04 06:20:56 AM UTC 24 |
Sep 04 06:21:07 AM UTC 24 |
372867701 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4203293499 |
|
|
Sep 04 06:21:06 AM UTC 24 |
Sep 04 06:21:08 AM UTC 24 |
93139620 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1239536564 |
|
|
Sep 04 06:21:06 AM UTC 24 |
Sep 04 06:21:08 AM UTC 24 |
30898058 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.438476452 |
|
|
Sep 04 06:21:04 AM UTC 24 |
Sep 04 06:21:08 AM UTC 24 |
232255522 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1438939929 |
|
|
Sep 04 06:21:06 AM UTC 24 |
Sep 04 06:21:08 AM UTC 24 |
64848987 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.782705785 |
|
|
Sep 04 06:21:05 AM UTC 24 |
Sep 04 06:21:09 AM UTC 24 |
125672922 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4115632317 |
|
|
Sep 04 06:21:06 AM UTC 24 |
Sep 04 06:21:09 AM UTC 24 |
94622508 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1919645178 |
|
|
Sep 04 06:21:06 AM UTC 24 |
Sep 04 06:21:09 AM UTC 24 |
27327191 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1725450767 |
|
|
Sep 04 06:21:04 AM UTC 24 |
Sep 04 06:21:09 AM UTC 24 |
132983402 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3006119681 |
|
|
Sep 04 06:21:06 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
56292219 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3434927532 |
|
|
Sep 04 06:21:08 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
34793063 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3368709925 |
|
|
Sep 04 06:21:08 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
43934587 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2140508126 |
|
|
Sep 04 06:21:08 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
22075673 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1705123414 |
|
|
Sep 04 06:21:08 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
16776824 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3337254498 |
|
|
Sep 04 06:20:55 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
968775446 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1943631913 |
|
|
Sep 04 06:21:07 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
121317790 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2184016491 |
|
|
Sep 04 06:21:06 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
383397048 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.161993889 |
|
|
Sep 04 06:21:07 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
34715223 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1974498642 |
|
|
Sep 04 06:21:08 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
40204028 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.394672087 |
|
|
Sep 04 06:20:48 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
2879073893 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1330597696 |
|
|
Sep 04 06:21:08 AM UTC 24 |
Sep 04 06:21:10 AM UTC 24 |
27034891 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.51538231 |
|
|
Sep 04 06:21:08 AM UTC 24 |
Sep 04 06:21:11 AM UTC 24 |
120205344 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1883732177 |
|
|
Sep 04 06:21:07 AM UTC 24 |
Sep 04 06:21:12 AM UTC 24 |
585013872 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2239757302 |
|
|
Sep 04 06:21:08 AM UTC 24 |
Sep 04 06:21:12 AM UTC 24 |
202256200 ps |