| T574 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.3282897353 |
|
|
Sep 09 11:25:18 AM UTC 24 |
Sep 09 11:25:33 AM UTC 24 |
764754241 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.4147163852 |
|
|
Sep 09 11:25:30 AM UTC 24 |
Sep 09 11:25:33 AM UTC 24 |
89164650 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.3964161394 |
|
|
Sep 09 11:25:30 AM UTC 24 |
Sep 09 11:25:33 AM UTC 24 |
60024017 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.1584443622 |
|
|
Sep 09 11:25:38 AM UTC 24 |
Sep 09 11:25:55 AM UTC 24 |
761410486 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.4267061620 |
|
|
Sep 09 11:25:16 AM UTC 24 |
Sep 09 11:25:33 AM UTC 24 |
1278652050 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1627827128 |
|
|
Sep 09 11:25:31 AM UTC 24 |
Sep 09 11:25:34 AM UTC 24 |
13183430 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2163789302 |
|
|
Sep 09 11:25:24 AM UTC 24 |
Sep 09 11:25:34 AM UTC 24 |
1334716499 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1117449117 |
|
|
Sep 09 11:25:53 AM UTC 24 |
Sep 09 11:25:55 AM UTC 24 |
47424402 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.631248422 |
|
|
Sep 09 11:25:24 AM UTC 24 |
Sep 09 11:25:35 AM UTC 24 |
1617475624 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.3742573005 |
|
|
Sep 09 11:25:27 AM UTC 24 |
Sep 09 11:25:35 AM UTC 24 |
45690092 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.408263476 |
|
|
Sep 09 11:24:33 AM UTC 24 |
Sep 09 11:25:36 AM UTC 24 |
3724061078 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1323072962 |
|
|
Sep 09 11:25:24 AM UTC 24 |
Sep 09 11:25:36 AM UTC 24 |
928607120 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.4253426260 |
|
|
Sep 09 11:25:27 AM UTC 24 |
Sep 09 11:25:36 AM UTC 24 |
365968439 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.1973669875 |
|
|
Sep 09 11:25:24 AM UTC 24 |
Sep 09 11:25:36 AM UTC 24 |
401042198 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2365663265 |
|
|
Sep 09 11:25:33 AM UTC 24 |
Sep 09 11:25:37 AM UTC 24 |
212501760 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3968281272 |
|
|
Sep 09 11:25:34 AM UTC 24 |
Sep 09 11:25:37 AM UTC 24 |
44091618 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2834607486 |
|
|
Sep 09 11:25:34 AM UTC 24 |
Sep 09 11:25:37 AM UTC 24 |
20966674 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.3702264483 |
|
|
Sep 09 11:25:24 AM UTC 24 |
Sep 09 11:25:37 AM UTC 24 |
281226508 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2506549957 |
|
|
Sep 09 11:24:45 AM UTC 24 |
Sep 09 11:25:38 AM UTC 24 |
1511104088 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3506553532 |
|
|
Sep 09 11:25:36 AM UTC 24 |
Sep 09 11:25:38 AM UTC 24 |
36276057 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3607714667 |
|
|
Sep 09 11:25:29 AM UTC 24 |
Sep 09 11:25:38 AM UTC 24 |
5271792352 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.3153562476 |
|
|
Sep 09 11:25:36 AM UTC 24 |
Sep 09 11:25:39 AM UTC 24 |
29732880 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3183644663 |
|
|
Sep 09 11:24:09 AM UTC 24 |
Sep 09 11:25:41 AM UTC 24 |
5548294751 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.772251814 |
|
|
Sep 09 11:25:33 AM UTC 24 |
Sep 09 11:25:41 AM UTC 24 |
73786610 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.1738162385 |
|
|
Sep 09 11:25:38 AM UTC 24 |
Sep 09 11:25:42 AM UTC 24 |
105088352 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2500938964 |
|
|
Sep 09 11:25:40 AM UTC 24 |
Sep 09 11:25:42 AM UTC 24 |
20157708 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.3272085678 |
|
|
Sep 09 11:25:37 AM UTC 24 |
Sep 09 11:25:42 AM UTC 24 |
96645765 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.683833484 |
|
|
Sep 09 11:25:29 AM UTC 24 |
Sep 09 11:25:42 AM UTC 24 |
2788410089 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.634681868 |
|
|
Sep 09 11:25:33 AM UTC 24 |
Sep 09 11:25:43 AM UTC 24 |
209439380 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.1490938061 |
|
|
Sep 09 11:25:37 AM UTC 24 |
Sep 09 11:25:43 AM UTC 24 |
119620507 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3030803807 |
|
|
Sep 09 11:25:33 AM UTC 24 |
Sep 09 11:25:44 AM UTC 24 |
219770412 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3292092965 |
|
|
Sep 09 11:25:42 AM UTC 24 |
Sep 09 11:25:45 AM UTC 24 |
32268735 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2060730146 |
|
|
Sep 09 11:25:29 AM UTC 24 |
Sep 09 11:25:45 AM UTC 24 |
989243012 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2993145596 |
|
|
Sep 09 11:25:40 AM UTC 24 |
Sep 09 11:25:45 AM UTC 24 |
69134641 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.793319087 |
|
|
Sep 09 11:25:21 AM UTC 24 |
Sep 09 11:25:47 AM UTC 24 |
478300204 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.1727155452 |
|
|
Sep 09 11:25:34 AM UTC 24 |
Sep 09 11:25:48 AM UTC 24 |
2779139137 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3033039552 |
|
|
Sep 09 11:25:34 AM UTC 24 |
Sep 09 11:25:48 AM UTC 24 |
2938094803 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.3127924849 |
|
|
Sep 09 11:25:29 AM UTC 24 |
Sep 09 11:25:48 AM UTC 24 |
533597091 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.1489955363 |
|
|
Sep 09 11:25:27 AM UTC 24 |
Sep 09 11:25:48 AM UTC 24 |
2013947240 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1463395159 |
|
|
Sep 09 11:25:38 AM UTC 24 |
Sep 09 11:25:49 AM UTC 24 |
255659200 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.1221882237 |
|
|
Sep 09 11:24:13 AM UTC 24 |
Sep 09 11:25:49 AM UTC 24 |
8324844334 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.878942661 |
|
|
Sep 09 11:25:44 AM UTC 24 |
Sep 09 11:25:49 AM UTC 24 |
665155478 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3291224562 |
|
|
Sep 09 11:25:44 AM UTC 24 |
Sep 09 11:25:49 AM UTC 24 |
94441149 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.2637232298 |
|
|
Sep 09 11:25:27 AM UTC 24 |
Sep 09 11:25:50 AM UTC 24 |
470329001 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.861195163 |
|
|
Sep 09 11:25:44 AM UTC 24 |
Sep 09 11:25:55 AM UTC 24 |
482646955 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.677680803 |
|
|
Sep 09 11:25:37 AM UTC 24 |
Sep 09 11:25:50 AM UTC 24 |
304754304 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1111567596 |
|
|
Sep 09 11:25:49 AM UTC 24 |
Sep 09 11:25:51 AM UTC 24 |
19808104 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.3003598263 |
|
|
Sep 09 11:25:49 AM UTC 24 |
Sep 09 11:25:51 AM UTC 24 |
19509934 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.379155366 |
|
|
Sep 09 11:25:49 AM UTC 24 |
Sep 09 11:25:52 AM UTC 24 |
161601108 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.3263670066 |
|
|
Sep 09 11:25:31 AM UTC 24 |
Sep 09 11:25:55 AM UTC 24 |
1046582029 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.1672262546 |
|
|
Sep 09 11:25:44 AM UTC 24 |
Sep 09 11:25:53 AM UTC 24 |
187907987 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.44369690 |
|
|
Sep 09 11:25:44 AM UTC 24 |
Sep 09 11:25:53 AM UTC 24 |
1530664098 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.2141485971 |
|
|
Sep 09 11:25:37 AM UTC 24 |
Sep 09 11:25:53 AM UTC 24 |
473948090 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.614581711 |
|
|
Sep 09 11:25:50 AM UTC 24 |
Sep 09 11:25:54 AM UTC 24 |
71282733 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.511307903 |
|
|
Sep 09 11:25:50 AM UTC 24 |
Sep 09 11:25:54 AM UTC 24 |
151768623 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.1255862238 |
|
|
Sep 09 11:25:50 AM UTC 24 |
Sep 09 11:25:55 AM UTC 24 |
285372346 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.1434863645 |
|
|
Sep 09 11:25:53 AM UTC 24 |
Sep 09 11:25:55 AM UTC 24 |
23157731 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.3915948698 |
|
|
Sep 09 11:25:06 AM UTC 24 |
Sep 09 11:25:56 AM UTC 24 |
2657332928 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.1224841220 |
|
|
Sep 09 11:25:45 AM UTC 24 |
Sep 09 11:25:57 AM UTC 24 |
1297474881 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.4239318560 |
|
|
Sep 09 11:25:45 AM UTC 24 |
Sep 09 11:25:58 AM UTC 24 |
376514456 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3785552200 |
|
|
Sep 09 11:25:53 AM UTC 24 |
Sep 09 11:25:58 AM UTC 24 |
141834428 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.2738626666 |
|
|
Sep 09 11:25:18 AM UTC 24 |
Sep 09 11:25:58 AM UTC 24 |
11221438506 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.141660786 |
|
|
Sep 09 11:25:44 AM UTC 24 |
Sep 09 11:25:59 AM UTC 24 |
419961882 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.2506547440 |
|
|
Sep 09 11:25:42 AM UTC 24 |
Sep 09 11:25:59 AM UTC 24 |
197782272 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.3409152131 |
|
|
Sep 09 11:25:57 AM UTC 24 |
Sep 09 11:25:59 AM UTC 24 |
14878819 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.1257523252 |
|
|
Sep 09 11:22:01 AM UTC 24 |
Sep 09 11:26:00 AM UTC 24 |
64069644578 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1924182566 |
|
|
Sep 09 11:25:55 AM UTC 24 |
Sep 09 11:26:00 AM UTC 24 |
77590662 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3944305452 |
|
|
Sep 09 11:25:58 AM UTC 24 |
Sep 09 11:26:00 AM UTC 24 |
11619003 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.2583085762 |
|
|
Sep 09 11:25:34 AM UTC 24 |
Sep 09 11:26:01 AM UTC 24 |
1421141489 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2187847291 |
|
|
Sep 09 11:25:56 AM UTC 24 |
Sep 09 11:26:01 AM UTC 24 |
275359526 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2324119839 |
|
|
Sep 09 11:26:25 AM UTC 24 |
Sep 09 11:26:28 AM UTC 24 |
37016669 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.3183609665 |
|
|
Sep 09 11:25:55 AM UTC 24 |
Sep 09 11:26:01 AM UTC 24 |
161537063 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.4024114845 |
|
|
Sep 09 11:25:50 AM UTC 24 |
Sep 09 11:26:02 AM UTC 24 |
1741923473 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.1729991933 |
|
|
Sep 09 11:25:58 AM UTC 24 |
Sep 09 11:26:02 AM UTC 24 |
33440353 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2192653111 |
|
|
Sep 09 11:25:29 AM UTC 24 |
Sep 09 11:26:03 AM UTC 24 |
7908684448 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2306445411 |
|
|
Sep 09 11:25:56 AM UTC 24 |
Sep 09 11:26:05 AM UTC 24 |
1386215102 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.783774131 |
|
|
Sep 09 11:25:50 AM UTC 24 |
Sep 09 11:26:05 AM UTC 24 |
303980107 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.564194433 |
|
|
Sep 09 11:26:03 AM UTC 24 |
Sep 09 11:26:05 AM UTC 24 |
13579511 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.1887620616 |
|
|
Sep 09 11:26:03 AM UTC 24 |
Sep 09 11:26:05 AM UTC 24 |
100483617 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.241564053 |
|
|
Sep 09 11:25:55 AM UTC 24 |
Sep 09 11:26:05 AM UTC 24 |
652106663 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.273409926 |
|
|
Sep 09 11:25:52 AM UTC 24 |
Sep 09 11:26:05 AM UTC 24 |
2891226451 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.3292149972 |
|
|
Sep 09 11:23:30 AM UTC 24 |
Sep 09 11:26:06 AM UTC 24 |
21896017121 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1894785957 |
|
|
Sep 09 11:25:36 AM UTC 24 |
Sep 09 11:26:06 AM UTC 24 |
936702325 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3856322607 |
|
|
Sep 09 11:26:00 AM UTC 24 |
Sep 09 11:26:06 AM UTC 24 |
168422695 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.1967008987 |
|
|
Sep 09 11:25:50 AM UTC 24 |
Sep 09 11:26:07 AM UTC 24 |
1528422780 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.3066279505 |
|
|
Sep 09 11:26:03 AM UTC 24 |
Sep 09 11:26:07 AM UTC 24 |
34300969 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.844908390 |
|
|
Sep 09 11:25:55 AM UTC 24 |
Sep 09 11:26:07 AM UTC 24 |
1000146281 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2348906225 |
|
|
Sep 09 11:25:56 AM UTC 24 |
Sep 09 11:26:09 AM UTC 24 |
1022497732 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.631714873 |
|
|
Sep 09 11:26:00 AM UTC 24 |
Sep 09 11:26:09 AM UTC 24 |
160590233 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3459100612 |
|
|
Sep 09 11:26:08 AM UTC 24 |
Sep 09 11:26:10 AM UTC 24 |
76519472 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.1530997752 |
|
|
Sep 09 11:25:52 AM UTC 24 |
Sep 09 11:26:10 AM UTC 24 |
4980740134 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.3458158891 |
|
|
Sep 09 11:26:08 AM UTC 24 |
Sep 09 11:26:10 AM UTC 24 |
15158319 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.2400965006 |
|
|
Sep 09 11:26:05 AM UTC 24 |
Sep 09 11:26:10 AM UTC 24 |
336132535 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.2419850029 |
|
|
Sep 09 11:26:00 AM UTC 24 |
Sep 09 11:26:12 AM UTC 24 |
290590747 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.3865663917 |
|
|
Sep 09 11:25:49 AM UTC 24 |
Sep 09 11:26:12 AM UTC 24 |
844256181 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3839862282 |
|
|
Sep 09 11:26:08 AM UTC 24 |
Sep 09 11:26:12 AM UTC 24 |
272067148 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.604189836 |
|
|
Sep 09 11:26:00 AM UTC 24 |
Sep 09 11:26:12 AM UTC 24 |
1095256529 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2495699648 |
|
|
Sep 09 11:26:01 AM UTC 24 |
Sep 09 11:26:13 AM UTC 24 |
272525725 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2647708020 |
|
|
Sep 09 11:26:04 AM UTC 24 |
Sep 09 11:26:13 AM UTC 24 |
161786303 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.2951933498 |
|
|
Sep 09 11:25:56 AM UTC 24 |
Sep 09 11:26:14 AM UTC 24 |
345383108 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.371003404 |
|
|
Sep 09 11:26:10 AM UTC 24 |
Sep 09 11:26:15 AM UTC 24 |
342432518 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2644373446 |
|
|
Sep 09 11:26:01 AM UTC 24 |
Sep 09 11:26:15 AM UTC 24 |
4483420535 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.3812552585 |
|
|
Sep 09 11:25:39 AM UTC 24 |
Sep 09 11:26:16 AM UTC 24 |
880141726 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.4230280557 |
|
|
Sep 09 11:26:00 AM UTC 24 |
Sep 09 11:26:16 AM UTC 24 |
446466051 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2267624604 |
|
|
Sep 09 11:26:14 AM UTC 24 |
Sep 09 11:26:17 AM UTC 24 |
39224355 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.3283150350 |
|
|
Sep 09 11:26:07 AM UTC 24 |
Sep 09 11:26:17 AM UTC 24 |
1408603425 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3185404619 |
|
|
Sep 09 11:23:58 AM UTC 24 |
Sep 09 11:26:17 AM UTC 24 |
5509396201 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.861223821 |
|
|
Sep 09 11:26:15 AM UTC 24 |
Sep 09 11:26:18 AM UTC 24 |
11926412 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.1383315481 |
|
|
Sep 09 11:24:53 AM UTC 24 |
Sep 09 11:26:18 AM UTC 24 |
1876675125 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2511250542 |
|
|
Sep 09 11:26:23 AM UTC 24 |
Sep 09 11:26:28 AM UTC 24 |
457887076 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.254889706 |
|
|
Sep 09 11:26:01 AM UTC 24 |
Sep 09 11:26:19 AM UTC 24 |
2079204720 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.164858750 |
|
|
Sep 09 11:26:07 AM UTC 24 |
Sep 09 11:26:19 AM UTC 24 |
379142684 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.2837704065 |
|
|
Sep 09 11:26:09 AM UTC 24 |
Sep 09 11:26:19 AM UTC 24 |
171301733 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.1482141624 |
|
|
Sep 09 11:26:14 AM UTC 24 |
Sep 09 11:26:21 AM UTC 24 |
61036715 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.3042403690 |
|
|
Sep 09 11:25:25 AM UTC 24 |
Sep 09 11:26:21 AM UTC 24 |
9367478026 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.361098372 |
|
|
Sep 09 11:26:17 AM UTC 24 |
Sep 09 11:26:22 AM UTC 24 |
119878893 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2829316518 |
|
|
Sep 09 11:26:07 AM UTC 24 |
Sep 09 11:26:22 AM UTC 24 |
1036336334 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.1319436348 |
|
|
Sep 09 11:26:07 AM UTC 24 |
Sep 09 11:26:22 AM UTC 24 |
1816634050 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.3066024597 |
|
|
Sep 09 11:26:12 AM UTC 24 |
Sep 09 11:26:22 AM UTC 24 |
2952317627 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.4052501216 |
|
|
Sep 09 11:26:20 AM UTC 24 |
Sep 09 11:26:23 AM UTC 24 |
18850189 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.778094842 |
|
|
Sep 09 11:26:19 AM UTC 24 |
Sep 09 11:26:29 AM UTC 24 |
1058051482 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3077760781 |
|
|
Sep 09 11:26:10 AM UTC 24 |
Sep 09 11:26:23 AM UTC 24 |
441424319 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.3227534754 |
|
|
Sep 09 11:26:03 AM UTC 24 |
Sep 09 11:26:24 AM UTC 24 |
1756635628 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.3537535108 |
|
|
Sep 09 11:25:58 AM UTC 24 |
Sep 09 11:26:24 AM UTC 24 |
234650431 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.227895198 |
|
|
Sep 09 11:26:13 AM UTC 24 |
Sep 09 11:26:24 AM UTC 24 |
432467062 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2971417495 |
|
|
Sep 09 11:25:52 AM UTC 24 |
Sep 09 11:26:24 AM UTC 24 |
1099901253 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1985533983 |
|
|
Sep 09 11:26:22 AM UTC 24 |
Sep 09 11:26:24 AM UTC 24 |
18614253 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.1627096246 |
|
|
Sep 09 11:26:08 AM UTC 24 |
Sep 09 11:26:25 AM UTC 24 |
377313731 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.3376310972 |
|
|
Sep 09 11:26:20 AM UTC 24 |
Sep 09 11:26:25 AM UTC 24 |
300244705 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.372819807 |
|
|
Sep 09 11:25:53 AM UTC 24 |
Sep 09 11:26:26 AM UTC 24 |
450730977 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.2925087737 |
|
|
Sep 09 11:26:13 AM UTC 24 |
Sep 09 11:26:26 AM UTC 24 |
293983202 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3312047642 |
|
|
Sep 09 11:26:23 AM UTC 24 |
Sep 09 11:26:27 AM UTC 24 |
140497134 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3043199145 |
|
|
Sep 09 11:25:14 AM UTC 24 |
Sep 09 11:26:27 AM UTC 24 |
8295148025 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.371911285 |
|
|
Sep 09 11:26:25 AM UTC 24 |
Sep 09 11:26:28 AM UTC 24 |
185335499 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3595575959 |
|
|
Sep 09 11:26:17 AM UTC 24 |
Sep 09 11:26:28 AM UTC 24 |
1206548856 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3555024212 |
|
|
Sep 09 11:26:08 AM UTC 24 |
Sep 09 11:26:29 AM UTC 24 |
3210129664 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1780943974 |
|
|
Sep 09 11:26:27 AM UTC 24 |
Sep 09 11:26:29 AM UTC 24 |
10984641 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1853918177 |
|
|
Sep 09 11:26:08 AM UTC 24 |
Sep 09 11:26:29 AM UTC 24 |
663758310 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.3218397732 |
|
|
Sep 09 11:26:19 AM UTC 24 |
Sep 09 11:26:30 AM UTC 24 |
969356426 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.1379360968 |
|
|
Sep 09 11:26:17 AM UTC 24 |
Sep 09 11:26:30 AM UTC 24 |
461036257 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.353350960 |
|
|
Sep 09 11:26:09 AM UTC 24 |
Sep 09 11:26:31 AM UTC 24 |
382506750 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.1539733451 |
|
|
Sep 09 11:26:19 AM UTC 24 |
Sep 09 11:26:31 AM UTC 24 |
747133458 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.2692152088 |
|
|
Sep 09 11:26:17 AM UTC 24 |
Sep 09 11:26:31 AM UTC 24 |
3132528579 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.2095215548 |
|
|
Sep 09 11:23:38 AM UTC 24 |
Sep 09 11:26:31 AM UTC 24 |
12088801534 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.2483436348 |
|
|
Sep 09 11:26:27 AM UTC 24 |
Sep 09 11:26:32 AM UTC 24 |
276867490 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.2680786281 |
|
|
Sep 09 11:26:20 AM UTC 24 |
Sep 09 11:26:32 AM UTC 24 |
1171354581 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.640097303 |
|
|
Sep 09 11:26:30 AM UTC 24 |
Sep 09 11:26:32 AM UTC 24 |
14668494 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.2937678304 |
|
|
Sep 09 11:26:12 AM UTC 24 |
Sep 09 11:26:33 AM UTC 24 |
6863854200 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4037346810 |
|
|
Sep 09 11:26:31 AM UTC 24 |
Sep 09 11:26:34 AM UTC 24 |
16353270 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.2052851028 |
|
|
Sep 09 11:26:25 AM UTC 24 |
Sep 09 11:26:36 AM UTC 24 |
1045319969 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2978002918 |
|
|
Sep 09 11:26:23 AM UTC 24 |
Sep 09 11:26:36 AM UTC 24 |
255811105 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.2993816742 |
|
|
Sep 09 11:26:12 AM UTC 24 |
Sep 09 11:26:36 AM UTC 24 |
5933593782 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.3896675202 |
|
|
Sep 09 11:26:28 AM UTC 24 |
Sep 09 11:26:36 AM UTC 24 |
1646347842 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.1457746337 |
|
|
Sep 09 11:26:27 AM UTC 24 |
Sep 09 11:26:36 AM UTC 24 |
464923751 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.852483074 |
|
|
Sep 09 11:24:58 AM UTC 24 |
Sep 09 11:26:37 AM UTC 24 |
4635838295 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.1914712587 |
|
|
Sep 09 11:26:33 AM UTC 24 |
Sep 09 11:26:37 AM UTC 24 |
51913183 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3029273401 |
|
|
Sep 09 11:26:23 AM UTC 24 |
Sep 09 11:26:38 AM UTC 24 |
251907959 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.244568783 |
|
|
Sep 09 11:26:25 AM UTC 24 |
Sep 09 11:26:38 AM UTC 24 |
725592391 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1114136877 |
|
|
Sep 09 11:26:28 AM UTC 24 |
Sep 09 11:26:38 AM UTC 24 |
208844404 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.333471538 |
|
|
Sep 09 11:26:28 AM UTC 24 |
Sep 09 11:26:39 AM UTC 24 |
3352834300 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.122548933 |
|
|
Sep 09 11:24:58 AM UTC 24 |
Sep 09 11:26:39 AM UTC 24 |
10323901337 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1525884450 |
|
|
Sep 09 11:26:37 AM UTC 24 |
Sep 09 11:26:39 AM UTC 24 |
35143693 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.3821031377 |
|
|
Sep 09 11:26:37 AM UTC 24 |
Sep 09 11:26:39 AM UTC 24 |
32295767 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.2327947785 |
|
|
Sep 09 11:26:28 AM UTC 24 |
Sep 09 11:26:40 AM UTC 24 |
1142155781 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3632694713 |
|
|
Sep 09 11:25:26 AM UTC 24 |
Sep 09 11:26:41 AM UTC 24 |
5648031437 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.14994000 |
|
|
Sep 09 11:26:37 AM UTC 24 |
Sep 09 11:26:41 AM UTC 24 |
35004584 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1766782864 |
|
|
Sep 09 11:26:31 AM UTC 24 |
Sep 09 11:26:41 AM UTC 24 |
98089171 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.880230868 |
|
|
Sep 09 11:26:22 AM UTC 24 |
Sep 09 11:26:41 AM UTC 24 |
868516715 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.947603167 |
|
|
Sep 09 11:26:31 AM UTC 24 |
Sep 09 11:26:41 AM UTC 24 |
57571054 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.4216261336 |
|
|
Sep 09 11:26:30 AM UTC 24 |
Sep 09 11:26:41 AM UTC 24 |
368167715 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.567167723 |
|
|
Sep 09 11:26:33 AM UTC 24 |
Sep 09 11:26:42 AM UTC 24 |
2053579184 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3361242498 |
|
|
Sep 09 11:24:06 AM UTC 24 |
Sep 09 11:26:42 AM UTC 24 |
30966557746 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.929731137 |
|
|
Sep 09 11:26:33 AM UTC 24 |
Sep 09 11:26:42 AM UTC 24 |
1402539955 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.3897066434 |
|
|
Sep 09 11:26:25 AM UTC 24 |
Sep 09 11:26:42 AM UTC 24 |
1625973324 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.3082575519 |
|
|
Sep 09 11:26:38 AM UTC 24 |
Sep 09 11:26:43 AM UTC 24 |
132774558 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1659449328 |
|
|
Sep 09 11:26:33 AM UTC 24 |
Sep 09 11:26:43 AM UTC 24 |
1102418229 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.3245164075 |
|
|
Sep 09 11:26:38 AM UTC 24 |
Sep 09 11:26:43 AM UTC 24 |
55156506 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.477589360 |
|
|
Sep 09 11:26:33 AM UTC 24 |
Sep 09 11:26:43 AM UTC 24 |
287740255 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.2362947294 |
|
|
Sep 09 11:26:23 AM UTC 24 |
Sep 09 11:26:44 AM UTC 24 |
1103206772 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1980542901 |
|
|
Sep 09 11:26:28 AM UTC 24 |
Sep 09 11:26:44 AM UTC 24 |
301404149 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3878410361 |
|
|
Sep 09 11:26:34 AM UTC 24 |
Sep 09 11:26:45 AM UTC 24 |
1056324263 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.371053463 |
|
|
Sep 09 11:26:48 AM UTC 24 |
Sep 09 11:26:56 AM UTC 24 |
2547739834 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.2415586618 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:45 AM UTC 24 |
31584314 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2644418512 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:45 AM UTC 24 |
56722458 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.654551065 |
|
|
Sep 09 11:26:33 AM UTC 24 |
Sep 09 11:26:46 AM UTC 24 |
1523239230 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.4247621652 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:46 AM UTC 24 |
115514962 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.440196758 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:46 AM UTC 24 |
17350166 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.185045204 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:47 AM UTC 24 |
83480032 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2401773066 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:48 AM UTC 24 |
69165603 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.211738442 |
|
|
Sep 09 11:26:45 AM UTC 24 |
Sep 09 11:26:48 AM UTC 24 |
42775719 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.1011108420 |
|
|
Sep 09 11:26:40 AM UTC 24 |
Sep 09 11:26:48 AM UTC 24 |
389681239 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3552070659 |
|
|
Sep 09 11:26:17 AM UTC 24 |
Sep 09 11:26:49 AM UTC 24 |
1158777759 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1328983888 |
|
|
Sep 09 11:26:46 AM UTC 24 |
Sep 09 11:26:49 AM UTC 24 |
100139831 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.937078443 |
|
|
Sep 09 11:26:40 AM UTC 24 |
Sep 09 11:26:49 AM UTC 24 |
4858404217 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.67457639 |
|
|
Sep 09 11:26:27 AM UTC 24 |
Sep 09 11:26:49 AM UTC 24 |
4185252896 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.4176699919 |
|
|
Sep 09 11:26:08 AM UTC 24 |
Sep 09 11:26:50 AM UTC 24 |
3798415758 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.489416960 |
|
|
Sep 09 11:26:38 AM UTC 24 |
Sep 09 11:26:50 AM UTC 24 |
235422285 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.667118912 |
|
|
Sep 09 11:25:40 AM UTC 24 |
Sep 09 11:26:51 AM UTC 24 |
1866909339 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.492879116 |
|
|
Sep 09 11:26:46 AM UTC 24 |
Sep 09 11:26:51 AM UTC 24 |
138511570 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.3277155223 |
|
|
Sep 09 11:26:40 AM UTC 24 |
Sep 09 11:26:51 AM UTC 24 |
295406923 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.2795493660 |
|
|
Sep 09 11:25:07 AM UTC 24 |
Sep 09 11:26:52 AM UTC 24 |
3601336366 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.858893501 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:52 AM UTC 24 |
267645786 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2512192318 |
|
|
Sep 09 11:26:50 AM UTC 24 |
Sep 09 11:26:53 AM UTC 24 |
14806535 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1788292033 |
|
|
Sep 09 11:26:25 AM UTC 24 |
Sep 09 11:26:53 AM UTC 24 |
756350527 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.38508418 |
|
|
Sep 09 11:26:31 AM UTC 24 |
Sep 09 11:26:53 AM UTC 24 |
919286535 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.1129192478 |
|
|
Sep 09 11:26:48 AM UTC 24 |
Sep 09 11:26:54 AM UTC 24 |
178133101 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.3682074239 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:54 AM UTC 24 |
1877818355 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.3825540077 |
|
|
Sep 09 11:26:40 AM UTC 24 |
Sep 09 11:26:54 AM UTC 24 |
2870023965 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1334832377 |
|
|
Sep 09 11:26:52 AM UTC 24 |
Sep 09 11:26:54 AM UTC 24 |
22298293 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3333269619 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:55 AM UTC 24 |
777908814 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.1578343921 |
|
|
Sep 09 11:26:46 AM UTC 24 |
Sep 09 11:26:55 AM UTC 24 |
99501624 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1673532537 |
|
|
Sep 09 11:26:52 AM UTC 24 |
Sep 09 11:26:55 AM UTC 24 |
155928231 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.1632406507 |
|
|
Sep 09 11:26:50 AM UTC 24 |
Sep 09 11:26:56 AM UTC 24 |
141094516 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.2738560765 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:26:56 AM UTC 24 |
271069569 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.451841541 |
|
|
Sep 09 11:26:40 AM UTC 24 |
Sep 09 11:26:57 AM UTC 24 |
300738388 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.2550173762 |
|
|
Sep 09 11:26:52 AM UTC 24 |
Sep 09 11:26:57 AM UTC 24 |
81778042 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1130818692 |
|
|
Sep 09 11:26:56 AM UTC 24 |
Sep 09 11:26:58 AM UTC 24 |
85517019 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2551817519 |
|
|
Sep 09 11:26:56 AM UTC 24 |
Sep 09 11:26:58 AM UTC 24 |
21703463 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.128455062 |
|
|
Sep 09 11:26:45 AM UTC 24 |
Sep 09 11:26:59 AM UTC 24 |
1456863494 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1484707741 |
|
|
Sep 09 11:26:56 AM UTC 24 |
Sep 09 11:27:00 AM UTC 24 |
35862780 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.2471540239 |
|
|
Sep 09 11:26:54 AM UTC 24 |
Sep 09 11:27:02 AM UTC 24 |
436429427 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.4181891407 |
|
|
Sep 09 11:26:56 AM UTC 24 |
Sep 09 11:27:02 AM UTC 24 |
872754021 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1676815264 |
|
|
Sep 09 11:26:48 AM UTC 24 |
Sep 09 11:27:02 AM UTC 24 |
690762897 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.4175614823 |
|
|
Sep 09 11:26:49 AM UTC 24 |
Sep 09 11:27:03 AM UTC 24 |
268893740 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.106416937 |
|
|
Sep 09 11:27:01 AM UTC 24 |
Sep 09 11:27:04 AM UTC 24 |
28727827 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.326276372 |
|
|
Sep 09 11:26:54 AM UTC 24 |
Sep 09 11:27:04 AM UTC 24 |
710436755 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1470478040 |
|
|
Sep 09 11:27:02 AM UTC 24 |
Sep 09 11:27:05 AM UTC 24 |
23081552 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2370920198 |
|
|
Sep 09 11:26:48 AM UTC 24 |
Sep 09 11:27:05 AM UTC 24 |
1130629101 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.772413143 |
|
|
Sep 09 11:26:49 AM UTC 24 |
Sep 09 11:27:05 AM UTC 24 |
355813009 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1447726851 |
|
|
Sep 09 11:26:54 AM UTC 24 |
Sep 09 11:27:05 AM UTC 24 |
1129990038 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2028062596 |
|
|
Sep 09 11:26:37 AM UTC 24 |
Sep 09 11:27:06 AM UTC 24 |
244608699 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1649680924 |
|
|
Sep 09 11:26:58 AM UTC 24 |
Sep 09 11:27:06 AM UTC 24 |
865538360 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.4041835945 |
|
|
Sep 09 11:27:02 AM UTC 24 |
Sep 09 11:27:07 AM UTC 24 |
37485754 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2781264245 |
|
|
Sep 09 11:26:58 AM UTC 24 |
Sep 09 11:27:07 AM UTC 24 |
269901616 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.3264039667 |
|
|
Sep 09 11:26:49 AM UTC 24 |
Sep 09 11:27:08 AM UTC 24 |
673015367 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.1101507821 |
|
|
Sep 09 11:27:05 AM UTC 24 |
Sep 09 11:27:09 AM UTC 24 |
149266073 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.1595418775 |
|
|
Sep 09 11:26:54 AM UTC 24 |
Sep 09 11:27:09 AM UTC 24 |
1785828790 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.2023574146 |
|
|
Sep 09 11:26:56 AM UTC 24 |
Sep 09 11:27:10 AM UTC 24 |
312737327 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.133658375 |
|
|
Sep 09 11:27:08 AM UTC 24 |
Sep 09 11:27:10 AM UTC 24 |
32689123 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.3797818545 |
|
|
Sep 09 11:26:54 AM UTC 24 |
Sep 09 11:27:10 AM UTC 24 |
4707776847 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.2172271197 |
|
|
Sep 09 11:26:59 AM UTC 24 |
Sep 09 11:27:12 AM UTC 24 |
324009356 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2497533400 |
|
|
Sep 09 11:27:10 AM UTC 24 |
Sep 09 11:27:13 AM UTC 24 |
27410977 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.732265313 |
|
|
Sep 09 11:26:58 AM UTC 24 |
Sep 09 11:27:13 AM UTC 24 |
306712881 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.56601789 |
|
|
Sep 09 11:27:09 AM UTC 24 |
Sep 09 11:27:13 AM UTC 24 |
35637972 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3452518259 |
|
|
Sep 09 11:26:46 AM UTC 24 |
Sep 09 11:27:14 AM UTC 24 |
1551515562 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3410853127 |
|
|
Sep 09 11:26:52 AM UTC 24 |
Sep 09 11:27:14 AM UTC 24 |
729286999 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1562631519 |
|
|
Sep 09 11:26:59 AM UTC 24 |
Sep 09 11:27:14 AM UTC 24 |
1087460231 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.758586602 |
|
|
Sep 09 11:27:05 AM UTC 24 |
Sep 09 11:27:15 AM UTC 24 |
64655388 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1792188507 |
|
|
Sep 09 11:27:07 AM UTC 24 |
Sep 09 11:27:15 AM UTC 24 |
328604557 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.1098424966 |
|
|
Sep 09 11:26:58 AM UTC 24 |
Sep 09 11:27:15 AM UTC 24 |
4784103265 ps |