| T814 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.2057224775 |
|
|
Sep 09 11:27:25 AM UTC 24 |
Sep 09 11:27:36 AM UTC 24 |
292992605 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.4092093191 |
|
|
Sep 09 11:27:05 AM UTC 24 |
Sep 09 11:27:16 AM UTC 24 |
649429972 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.4232030828 |
|
|
Sep 09 11:27:06 AM UTC 24 |
Sep 09 11:27:18 AM UTC 24 |
2862439398 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.3622341920 |
|
|
Sep 09 11:27:12 AM UTC 24 |
Sep 09 11:27:18 AM UTC 24 |
374600310 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3959813682 |
|
|
Sep 09 11:27:16 AM UTC 24 |
Sep 09 11:27:18 AM UTC 24 |
20796579 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1164635446 |
|
|
Sep 09 11:27:06 AM UTC 24 |
Sep 09 11:27:18 AM UTC 24 |
3001868984 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3751898466 |
|
|
Sep 09 11:27:16 AM UTC 24 |
Sep 09 11:27:18 AM UTC 24 |
14996076 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3493990979 |
|
|
Sep 09 11:26:56 AM UTC 24 |
Sep 09 11:27:18 AM UTC 24 |
1900698808 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2519520103 |
|
|
Sep 09 11:26:20 AM UTC 24 |
Sep 09 11:27:19 AM UTC 24 |
1057678521 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1844429152 |
|
|
Sep 09 11:26:52 AM UTC 24 |
Sep 09 11:27:19 AM UTC 24 |
212491786 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.2385428801 |
|
|
Sep 09 11:27:16 AM UTC 24 |
Sep 09 11:27:19 AM UTC 24 |
60346588 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.3961029993 |
|
|
Sep 09 11:27:07 AM UTC 24 |
Sep 09 11:27:20 AM UTC 24 |
533380858 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.2798599725 |
|
|
Sep 09 11:26:43 AM UTC 24 |
Sep 09 11:27:20 AM UTC 24 |
589116407 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1833185233 |
|
|
Sep 09 11:26:56 AM UTC 24 |
Sep 09 11:27:20 AM UTC 24 |
852962915 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2979998495 |
|
|
Sep 09 11:27:25 AM UTC 24 |
Sep 09 11:27:36 AM UTC 24 |
1133339578 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.1121524785 |
|
|
Sep 09 11:27:14 AM UTC 24 |
Sep 09 11:27:21 AM UTC 24 |
1724368758 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.923648428 |
|
|
Sep 09 11:27:10 AM UTC 24 |
Sep 09 11:27:36 AM UTC 24 |
836199418 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.2559590467 |
|
|
Sep 09 11:27:07 AM UTC 24 |
Sep 09 11:27:22 AM UTC 24 |
408245600 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.3886214617 |
|
|
Sep 09 11:27:19 AM UTC 24 |
Sep 09 11:27:23 AM UTC 24 |
108973205 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.3703216328 |
|
|
Sep 09 11:26:40 AM UTC 24 |
Sep 09 11:27:23 AM UTC 24 |
4343028590 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4200306880 |
|
|
Sep 09 11:27:21 AM UTC 24 |
Sep 09 11:27:24 AM UTC 24 |
15027030 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.3587091842 |
|
|
Sep 09 11:27:21 AM UTC 24 |
Sep 09 11:27:24 AM UTC 24 |
89732585 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.1499165680 |
|
|
Sep 09 11:27:11 AM UTC 24 |
Sep 09 11:27:24 AM UTC 24 |
136267968 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.1533482191 |
|
|
Sep 09 11:27:21 AM UTC 24 |
Sep 09 11:27:24 AM UTC 24 |
131860544 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2474853700 |
|
|
Sep 09 11:27:13 AM UTC 24 |
Sep 09 11:27:25 AM UTC 24 |
990279147 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1202948503 |
|
|
Sep 09 11:27:22 AM UTC 24 |
Sep 09 11:27:26 AM UTC 24 |
103847099 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.2148830734 |
|
|
Sep 09 11:27:12 AM UTC 24 |
Sep 09 11:27:26 AM UTC 24 |
1188783551 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.3219003931 |
|
|
Sep 09 11:27:18 AM UTC 24 |
Sep 09 11:27:27 AM UTC 24 |
224350670 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.155929574 |
|
|
Sep 09 11:26:20 AM UTC 24 |
Sep 09 11:27:27 AM UTC 24 |
2019792290 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1849852159 |
|
|
Sep 09 11:27:14 AM UTC 24 |
Sep 09 11:27:27 AM UTC 24 |
423889684 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.122760871 |
|
|
Sep 09 11:27:19 AM UTC 24 |
Sep 09 11:27:27 AM UTC 24 |
3719724391 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.870464751 |
|
|
Sep 09 11:27:26 AM UTC 24 |
Sep 09 11:27:29 AM UTC 24 |
90411012 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1293885263 |
|
|
Sep 09 11:27:21 AM UTC 24 |
Sep 09 11:27:29 AM UTC 24 |
2412799423 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3965610180 |
|
|
Sep 09 11:27:14 AM UTC 24 |
Sep 09 11:27:29 AM UTC 24 |
1059398204 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2496986212 |
|
|
Sep 09 11:27:22 AM UTC 24 |
Sep 09 11:27:30 AM UTC 24 |
987614486 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.474511654 |
|
|
Sep 09 11:24:39 AM UTC 24 |
Sep 09 11:27:31 AM UTC 24 |
3727172302 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1259775899 |
|
|
Sep 09 11:27:14 AM UTC 24 |
Sep 09 11:27:31 AM UTC 24 |
365223566 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.1942048854 |
|
|
Sep 09 11:27:19 AM UTC 24 |
Sep 09 11:27:31 AM UTC 24 |
411231647 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1499142474 |
|
|
Sep 09 11:27:19 AM UTC 24 |
Sep 09 11:27:33 AM UTC 24 |
398538101 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.1852849305 |
|
|
Sep 09 11:27:04 AM UTC 24 |
Sep 09 11:27:33 AM UTC 24 |
359141231 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.529068189 |
|
|
Sep 09 11:27:19 AM UTC 24 |
Sep 09 11:27:34 AM UTC 24 |
2522045398 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.644901352 |
|
|
Sep 09 11:23:03 AM UTC 24 |
Sep 09 11:27:34 AM UTC 24 |
47626657467 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.270826784 |
|
|
Sep 09 11:27:19 AM UTC 24 |
Sep 09 11:27:35 AM UTC 24 |
790037485 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.3000643871 |
|
|
Sep 09 11:27:24 AM UTC 24 |
Sep 09 11:27:37 AM UTC 24 |
2174506435 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1362081094 |
|
|
Sep 09 11:27:24 AM UTC 24 |
Sep 09 11:27:37 AM UTC 24 |
577490334 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.317739873 |
|
|
Sep 09 11:26:30 AM UTC 24 |
Sep 09 11:27:38 AM UTC 24 |
8855168157 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1979393391 |
|
|
Sep 09 11:27:25 AM UTC 24 |
Sep 09 11:27:41 AM UTC 24 |
1800661227 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2293113078 |
|
|
Sep 09 11:27:25 AM UTC 24 |
Sep 09 11:27:42 AM UTC 24 |
2274915847 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1527761557 |
|
|
Sep 09 11:26:50 AM UTC 24 |
Sep 09 11:27:45 AM UTC 24 |
6318433061 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3714179854 |
|
|
Sep 09 11:26:45 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
13811819925 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2027579084 |
|
|
Sep 09 11:27:18 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
259549800 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.1831414154 |
|
|
Sep 09 11:27:22 AM UTC 24 |
Sep 09 11:27:53 AM UTC 24 |
314331061 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.18154720 |
|
|
Sep 09 11:27:26 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
4578469845 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.2820606632 |
|
|
Sep 09 11:27:08 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
1457438886 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2061574535 |
|
|
Sep 09 11:23:23 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
25164517853 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2528059726 |
|
|
Sep 09 11:26:59 AM UTC 24 |
Sep 09 11:28:13 AM UTC 24 |
9436049221 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.2629161412 |
|
|
Sep 09 11:25:52 AM UTC 24 |
Sep 09 11:28:13 AM UTC 24 |
10030543468 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3456972390 |
|
|
Sep 09 11:25:57 AM UTC 24 |
Sep 09 11:28:17 AM UTC 24 |
28046010612 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.1558485602 |
|
|
Sep 09 11:26:25 AM UTC 24 |
Sep 09 11:28:21 AM UTC 24 |
6839778043 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.2451350349 |
|
|
Sep 09 11:25:57 AM UTC 24 |
Sep 09 11:28:26 AM UTC 24 |
15869920432 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1216933087 |
|
|
Sep 09 11:25:46 AM UTC 24 |
Sep 09 11:28:33 AM UTC 24 |
31107868216 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1460972725 |
|
|
Sep 09 11:26:45 AM UTC 24 |
Sep 09 11:28:40 AM UTC 24 |
7100147008 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1542003833 |
|
|
Sep 09 11:26:30 AM UTC 24 |
Sep 09 11:28:48 AM UTC 24 |
6231563484 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.4006077755 |
|
|
Sep 09 11:26:37 AM UTC 24 |
Sep 09 11:28:54 AM UTC 24 |
13778547742 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2258279918 |
|
|
Sep 09 11:25:34 AM UTC 24 |
Sep 09 11:28:57 AM UTC 24 |
7188494185 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.708859813 |
|
|
Sep 09 11:26:13 AM UTC 24 |
Sep 09 11:29:09 AM UTC 24 |
8885220213 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2174345410 |
|
|
Sep 09 11:25:29 AM UTC 24 |
Sep 09 11:29:10 AM UTC 24 |
5587509826 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.4159968857 |
|
|
Sep 09 11:24:24 AM UTC 24 |
Sep 09 11:29:14 AM UTC 24 |
10345280690 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.3808819812 |
|
|
Sep 09 11:26:01 AM UTC 24 |
Sep 09 11:29:21 AM UTC 24 |
8255648679 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2747004821 |
|
|
Sep 09 11:26:50 AM UTC 24 |
Sep 09 11:29:35 AM UTC 24 |
72710823850 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2283187145 |
|
|
Sep 09 11:27:21 AM UTC 24 |
Sep 09 11:30:25 AM UTC 24 |
43828133873 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2349507814 |
|
|
Sep 09 11:26:34 AM UTC 24 |
Sep 09 11:32:18 AM UTC 24 |
13397913128 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.1295143336 |
|
|
Sep 09 11:27:16 AM UTC 24 |
Sep 09 11:32:43 AM UTC 24 |
14597958059 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.94418944 |
|
|
Sep 09 11:27:25 AM UTC 24 |
Sep 09 11:32:57 AM UTC 24 |
17942191299 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.4003502949 |
|
|
Sep 09 11:26:54 AM UTC 24 |
Sep 09 11:33:07 AM UTC 24 |
45506967008 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3781073219 |
|
|
Sep 09 11:22:40 AM UTC 24 |
Sep 09 11:33:16 AM UTC 24 |
24419865480 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1862137427 |
|
|
Sep 09 11:22:29 AM UTC 24 |
Sep 09 11:35:21 AM UTC 24 |
29340349319 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2883834354 |
|
|
Sep 09 11:27:28 AM UTC 24 |
Sep 09 11:27:31 AM UTC 24 |
56662121 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.825756467 |
|
|
Sep 09 11:27:28 AM UTC 24 |
Sep 09 11:27:31 AM UTC 24 |
117188152 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2310027891 |
|
|
Sep 09 11:27:29 AM UTC 24 |
Sep 09 11:27:32 AM UTC 24 |
440536603 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3603936536 |
|
|
Sep 09 11:27:28 AM UTC 24 |
Sep 09 11:27:33 AM UTC 24 |
122700945 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3212437564 |
|
|
Sep 09 11:27:30 AM UTC 24 |
Sep 09 11:27:33 AM UTC 24 |
25779667 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.809758778 |
|
|
Sep 09 11:27:32 AM UTC 24 |
Sep 09 11:27:35 AM UTC 24 |
12585592 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1594864212 |
|
|
Sep 09 11:27:32 AM UTC 24 |
Sep 09 11:27:35 AM UTC 24 |
233089618 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2070701443 |
|
|
Sep 09 11:27:32 AM UTC 24 |
Sep 09 11:27:35 AM UTC 24 |
15673097 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1524443346 |
|
|
Sep 09 11:27:30 AM UTC 24 |
Sep 09 11:27:35 AM UTC 24 |
139633985 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2036459619 |
|
|
Sep 09 11:27:32 AM UTC 24 |
Sep 09 11:27:35 AM UTC 24 |
15684320 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3754264545 |
|
|
Sep 09 11:27:32 AM UTC 24 |
Sep 09 11:27:35 AM UTC 24 |
24676426 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1966549071 |
|
|
Sep 09 11:27:32 AM UTC 24 |
Sep 09 11:27:36 AM UTC 24 |
73307381 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4085445442 |
|
|
Sep 09 11:27:34 AM UTC 24 |
Sep 09 11:27:37 AM UTC 24 |
41925854 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2720769504 |
|
|
Sep 09 11:27:34 AM UTC 24 |
Sep 09 11:27:37 AM UTC 24 |
332408189 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2510056927 |
|
|
Sep 09 11:27:34 AM UTC 24 |
Sep 09 11:27:37 AM UTC 24 |
105000891 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2207207135 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:38 AM UTC 24 |
46596868 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.202685287 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:39 AM UTC 24 |
12770248 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1335491242 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:39 AM UTC 24 |
37231295 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4096166731 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:39 AM UTC 24 |
83605440 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4225015910 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:39 AM UTC 24 |
26100686 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.967172509 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:39 AM UTC 24 |
858194040 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1596967436 |
|
|
Sep 09 11:27:47 AM UTC 24 |
Sep 09 11:27:50 AM UTC 24 |
13832199 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1727490447 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:40 AM UTC 24 |
82657646 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.628932345 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:41 AM UTC 24 |
31091518 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3980442626 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:41 AM UTC 24 |
381349948 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3045365264 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:41 AM UTC 24 |
73964763 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4184335431 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:41 AM UTC 24 |
67998484 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2023576492 |
|
|
Sep 09 11:27:40 AM UTC 24 |
Sep 09 11:27:42 AM UTC 24 |
70633257 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1992642634 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:42 AM UTC 24 |
1246071470 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1579852052 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:42 AM UTC 24 |
40403964 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1479467336 |
|
|
Sep 09 11:27:40 AM UTC 24 |
Sep 09 11:27:42 AM UTC 24 |
15456955 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1961757603 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:42 AM UTC 24 |
365363311 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2883252529 |
|
|
Sep 09 11:27:39 AM UTC 24 |
Sep 09 11:27:42 AM UTC 24 |
101110765 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3823722599 |
|
|
Sep 09 11:27:40 AM UTC 24 |
Sep 09 11:27:43 AM UTC 24 |
168888554 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3702445919 |
|
|
Sep 09 11:27:40 AM UTC 24 |
Sep 09 11:27:43 AM UTC 24 |
36058935 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3044711269 |
|
|
Sep 09 11:27:36 AM UTC 24 |
Sep 09 11:27:43 AM UTC 24 |
1245014480 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.471229285 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:43 AM UTC 24 |
175679454 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2881880104 |
|
|
Sep 09 11:27:41 AM UTC 24 |
Sep 09 11:27:43 AM UTC 24 |
84584411 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.499506119 |
|
|
Sep 09 11:27:41 AM UTC 24 |
Sep 09 11:27:43 AM UTC 24 |
35648067 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.698516212 |
|
|
Sep 09 11:27:40 AM UTC 24 |
Sep 09 11:27:44 AM UTC 24 |
281856116 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2851738576 |
|
|
Sep 09 11:27:34 AM UTC 24 |
Sep 09 11:27:45 AM UTC 24 |
1466734769 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2739226506 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
17858513 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.831235685 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
35505542 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2238761994 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
44102248 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2417457546 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
17848514 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.600568446 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
20285780 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1667718454 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:27:51 AM UTC 24 |
694769872 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.607390468 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
389858219 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3064885173 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
66661844 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2804882548 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
65904354 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.491798140 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:46 AM UTC 24 |
59260566 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.141838766 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:47 AM UTC 24 |
194681271 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3526163091 |
|
|
Sep 09 11:27:44 AM UTC 24 |
Sep 09 11:27:47 AM UTC 24 |
43217982 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.466171373 |
|
|
Sep 09 11:27:44 AM UTC 24 |
Sep 09 11:27:47 AM UTC 24 |
49618167 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.597529995 |
|
|
Sep 09 11:27:45 AM UTC 24 |
Sep 09 11:27:47 AM UTC 24 |
46136460 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.110645951 |
|
|
Sep 09 11:27:45 AM UTC 24 |
Sep 09 11:27:47 AM UTC 24 |
183257009 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2921858576 |
|
|
Sep 09 11:27:45 AM UTC 24 |
Sep 09 11:27:47 AM UTC 24 |
85495595 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1517438773 |
|
|
Sep 09 11:27:46 AM UTC 24 |
Sep 09 11:27:48 AM UTC 24 |
41766722 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1566045975 |
|
|
Sep 09 11:27:34 AM UTC 24 |
Sep 09 11:27:48 AM UTC 24 |
1238347337 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.517774961 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:48 AM UTC 24 |
8049093624 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2966628455 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:27:50 AM UTC 24 |
15775081 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1002045895 |
|
|
Sep 09 11:27:47 AM UTC 24 |
Sep 09 11:27:49 AM UTC 24 |
14485344 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2349528379 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:49 AM UTC 24 |
237795072 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1633742781 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:27:50 AM UTC 24 |
24279901 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1871024955 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:27:50 AM UTC 24 |
53996033 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3237592132 |
|
|
Sep 09 11:27:46 AM UTC 24 |
Sep 09 11:27:51 AM UTC 24 |
204163024 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2530072700 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:27:51 AM UTC 24 |
49786137 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4195882986 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:27:51 AM UTC 24 |
44837907 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.768052683 |
|
|
Sep 09 11:27:49 AM UTC 24 |
Sep 09 11:27:51 AM UTC 24 |
42881720 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1411999351 |
|
|
Sep 09 11:27:49 AM UTC 24 |
Sep 09 11:27:51 AM UTC 24 |
38696582 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3838913001 |
|
|
Sep 09 11:27:49 AM UTC 24 |
Sep 09 11:27:52 AM UTC 24 |
26750517 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2551117872 |
|
|
Sep 09 11:27:49 AM UTC 24 |
Sep 09 11:27:52 AM UTC 24 |
56850347 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3616990434 |
|
|
Sep 09 11:27:47 AM UTC 24 |
Sep 09 11:27:52 AM UTC 24 |
391102684 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.633823184 |
|
|
Sep 09 11:27:28 AM UTC 24 |
Sep 09 11:27:52 AM UTC 24 |
2328647733 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.101909471 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:27:53 AM UTC 24 |
135426994 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2773600915 |
|
|
Sep 09 11:27:52 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
16992823 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3689248057 |
|
|
Sep 09 11:27:49 AM UTC 24 |
Sep 09 11:27:53 AM UTC 24 |
512648261 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2386334444 |
|
|
Sep 09 11:27:46 AM UTC 24 |
Sep 09 11:27:53 AM UTC 24 |
262751009 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.969491685 |
|
|
Sep 09 11:27:51 AM UTC 24 |
Sep 09 11:27:54 AM UTC 24 |
68131705 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.54248012 |
|
|
Sep 09 11:27:51 AM UTC 24 |
Sep 09 11:27:54 AM UTC 24 |
906769737 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2402741398 |
|
|
Sep 09 11:28:04 AM UTC 24 |
Sep 09 11:28:06 AM UTC 24 |
12369639 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2266492308 |
|
|
Sep 09 11:27:49 AM UTC 24 |
Sep 09 11:27:54 AM UTC 24 |
162896077 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.534564513 |
|
|
Sep 09 11:27:51 AM UTC 24 |
Sep 09 11:27:54 AM UTC 24 |
77467627 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1824128598 |
|
|
Sep 09 11:27:38 AM UTC 24 |
Sep 09 11:27:54 AM UTC 24 |
1376290012 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3629920150 |
|
|
Sep 09 11:27:28 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
9255548902 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1365569655 |
|
|
Sep 09 11:27:51 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
83178173 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1198623481 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
444549255 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1417244230 |
|
|
Sep 09 11:27:52 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
66554241 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1173102069 |
|
|
Sep 09 11:27:51 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
195520851 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.809339953 |
|
|
Sep 09 11:27:52 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
32616996 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2858373687 |
|
|
Sep 09 11:27:52 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
605238821 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.329849134 |
|
|
Sep 09 11:27:49 AM UTC 24 |
Sep 09 11:27:55 AM UTC 24 |
379510820 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1520794969 |
|
|
Sep 09 11:27:52 AM UTC 24 |
Sep 09 11:27:56 AM UTC 24 |
109700143 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1824206257 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:27:56 AM UTC 24 |
8388282911 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3605399333 |
|
|
Sep 09 11:27:54 AM UTC 24 |
Sep 09 11:27:56 AM UTC 24 |
45689089 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1837034453 |
|
|
Sep 09 11:27:43 AM UTC 24 |
Sep 09 11:27:56 AM UTC 24 |
1366958582 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3116554967 |
|
|
Sep 09 11:27:54 AM UTC 24 |
Sep 09 11:27:56 AM UTC 24 |
28916721 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1911130517 |
|
|
Sep 09 11:27:51 AM UTC 24 |
Sep 09 11:27:56 AM UTC 24 |
387669783 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.772826629 |
|
|
Sep 09 11:27:53 AM UTC 24 |
Sep 09 11:27:57 AM UTC 24 |
483320549 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1555567917 |
|
|
Sep 09 11:27:52 AM UTC 24 |
Sep 09 11:27:57 AM UTC 24 |
75927919 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1414328241 |
|
|
Sep 09 11:27:54 AM UTC 24 |
Sep 09 11:27:58 AM UTC 24 |
102872636 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1474281393 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:27:58 AM UTC 24 |
20878723 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3948399359 |
|
|
Sep 09 11:27:54 AM UTC 24 |
Sep 09 11:27:58 AM UTC 24 |
732788196 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3140921063 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:27:58 AM UTC 24 |
23119678 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.653786391 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:27:58 AM UTC 24 |
140878971 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.36259564 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:27:59 AM UTC 24 |
36464853 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.482003575 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:27:59 AM UTC 24 |
35476287 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2780144230 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:27:59 AM UTC 24 |
112582660 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2418360667 |
|
|
Sep 09 11:27:53 AM UTC 24 |
Sep 09 11:27:59 AM UTC 24 |
893419136 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.947458692 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:27:59 AM UTC 24 |
469741619 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.685064728 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:27:59 AM UTC 24 |
28707880 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3901402637 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
118234757 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.335149660 |
|
|
Sep 09 11:27:54 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
191694919 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3641047271 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
164646816 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4061377940 |
|
|
Sep 09 11:27:58 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
123685347 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.355062591 |
|
|
Sep 09 11:27:58 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
42973776 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1928141973 |
|
|
Sep 09 11:27:58 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
30690024 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1236587551 |
|
|
Sep 09 11:27:58 AM UTC 24 |
Sep 09 11:28:00 AM UTC 24 |
153488267 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2892040333 |
|
|
Sep 09 11:27:56 AM UTC 24 |
Sep 09 11:28:01 AM UTC 24 |
273860847 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1991493913 |
|
|
Sep 09 11:27:58 AM UTC 24 |
Sep 09 11:28:01 AM UTC 24 |
52515540 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4106044708 |
|
|
Sep 09 11:27:45 AM UTC 24 |
Sep 09 11:28:01 AM UTC 24 |
4865649267 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2266002619 |
|
|
Sep 09 11:27:53 AM UTC 24 |
Sep 09 11:28:01 AM UTC 24 |
1595778270 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.188762008 |
|
|
Sep 09 11:28:04 AM UTC 24 |
Sep 09 11:28:06 AM UTC 24 |
13744838 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3574481490 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:02 AM UTC 24 |
88593858 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1249534230 |
|
|
Sep 09 11:27:58 AM UTC 24 |
Sep 09 11:28:02 AM UTC 24 |
1066975686 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.164308683 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:02 AM UTC 24 |
16788037 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.440486147 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:02 AM UTC 24 |
22131987 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4039672602 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:02 AM UTC 24 |
43362930 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.536181949 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:03 AM UTC 24 |
130961236 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1925058575 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:03 AM UTC 24 |
128201536 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3542948093 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:03 AM UTC 24 |
80771307 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.612922358 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:04 AM UTC 24 |
234202159 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1050152957 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:04 AM UTC 24 |
227425069 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2771886681 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:04 AM UTC 24 |
36910327 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1666569709 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:04 AM UTC 24 |
74848548 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2453795890 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:04 AM UTC 24 |
159368299 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3826086250 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
125726105 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1321003820 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
12559439 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3049483708 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
27606006 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2640293583 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
121034849 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1848098938 |
|
|
Sep 09 11:27:58 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
207689719 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1142272160 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
41288105 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4081491425 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
110273481 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2295938530 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
119954332 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2428466676 |
|
|
Sep 09 11:28:00 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
454150055 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3773194460 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:07 AM UTC 24 |
148599186 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.951051000 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
61759992 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4010460596 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:05 AM UTC 24 |
38828713 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2306571519 |
|
|
Sep 09 11:27:45 AM UTC 24 |
Sep 09 11:28:06 AM UTC 24 |
833982154 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3374642348 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:06 AM UTC 24 |
42914008 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2531718544 |
|
|
Sep 09 11:27:51 AM UTC 24 |
Sep 09 11:28:06 AM UTC 24 |
628305393 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2434524713 |
|
|
Sep 09 11:28:04 AM UTC 24 |
Sep 09 11:28:07 AM UTC 24 |
196343303 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4019943494 |
|
|
Sep 09 11:27:48 AM UTC 24 |
Sep 09 11:28:07 AM UTC 24 |
810294668 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2430283815 |
|
|
Sep 09 11:28:04 AM UTC 24 |
Sep 09 11:28:07 AM UTC 24 |
29515370 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.914700127 |
|
|
Sep 09 11:28:04 AM UTC 24 |
Sep 09 11:28:07 AM UTC 24 |
1083046865 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1768266671 |
|
|
Sep 09 11:28:05 AM UTC 24 |
Sep 09 11:28:07 AM UTC 24 |
30489697 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.345087305 |
|
|
Sep 09 11:28:04 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
102829580 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2841916995 |
|
|
Sep 09 11:28:05 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
20757374 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.616372332 |
|
|
Sep 09 11:28:05 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
30180761 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1062442218 |
|
|
Sep 09 11:28:05 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
102266935 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4273377474 |
|
|
Sep 09 11:28:04 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
453535804 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3626606713 |
|
|
Sep 09 11:28:05 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
89013938 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.804695982 |
|
|
Sep 09 11:28:02 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
292733932 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1995479263 |
|
|
Sep 09 11:28:05 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
79230427 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1754924515 |
|
|
Sep 09 11:28:05 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
174747528 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.769825961 |
|
|
Sep 09 11:28:04 AM UTC 24 |
Sep 09 11:28:08 AM UTC 24 |
572776140 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3922868742 |
|
|
Sep 09 11:27:58 AM UTC 24 |
Sep 09 11:28:09 AM UTC 24 |
1617228367 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2777800217 |
|
|
Sep 09 11:28:07 AM UTC 24 |
Sep 09 11:28:09 AM UTC 24 |
27093074 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.79270403 |
|
|
Sep 09 11:28:07 AM UTC 24 |
Sep 09 11:28:09 AM UTC 24 |
18848687 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2396836696 |
|
|
Sep 09 11:28:06 AM UTC 24 |
Sep 09 11:28:09 AM UTC 24 |
90156384 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.661748800 |
|
|
Sep 09 11:28:07 AM UTC 24 |
Sep 09 11:28:10 AM UTC 24 |
42306885 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1143168529 |
|
|
Sep 09 11:28:08 AM UTC 24 |
Sep 09 11:28:10 AM UTC 24 |
44448812 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2267788097 |
|
|
Sep 09 11:28:07 AM UTC 24 |
Sep 09 11:28:10 AM UTC 24 |
32175299 ps |