Unified Coverage Report :: Module :: prim_sec_anchor_flop

Module : prim_sec_anchor_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_sec_anchor_0.1/rtl/prim_sec_anchor_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req.gen_flops.u_prim_flop
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en.gen_flops.u_prim_flop

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_raw_test_rma

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_dft_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_nvm_debug_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_hw_debug_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_cpu_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_creator_seed_sw_rw_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_owner_seed_sw_rw_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_iso_part_sw_rd_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_iso_part_sw_wr_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_seed_hw_rd_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_keymgr_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_escalate_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_clk_byp_req

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_flash_rma_req

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en.gen_flops.u_prim_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_lc_sender_check_byp_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_flop	100.00	100.00				100.00