| T583 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.244534373 |
|
|
Sep 24 12:41:50 PM UTC 24 |
Sep 24 12:42:10 PM UTC 24 |
1744057926 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.1810856210 |
|
|
Sep 24 12:41:55 PM UTC 24 |
Sep 24 12:42:10 PM UTC 24 |
516560374 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.3886170146 |
|
|
Sep 24 12:42:10 PM UTC 24 |
Sep 24 12:42:12 PM UTC 24 |
19562701 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1209934592 |
|
|
Sep 24 12:41:49 PM UTC 24 |
Sep 24 12:42:13 PM UTC 24 |
1472827756 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.423435434 |
|
|
Sep 24 12:42:27 PM UTC 24 |
Sep 24 12:42:44 PM UTC 24 |
3337841371 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.452955142 |
|
|
Sep 24 12:42:03 PM UTC 24 |
Sep 24 12:42:13 PM UTC 24 |
134989003 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.449258558 |
|
|
Sep 24 12:41:56 PM UTC 24 |
Sep 24 12:42:13 PM UTC 24 |
4875039731 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.3938975867 |
|
|
Sep 24 12:41:56 PM UTC 24 |
Sep 24 12:42:13 PM UTC 24 |
1825692885 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2443648633 |
|
|
Sep 24 12:42:11 PM UTC 24 |
Sep 24 12:42:13 PM UTC 24 |
16542777 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1721951734 |
|
|
Sep 24 12:40:54 PM UTC 24 |
Sep 24 12:42:13 PM UTC 24 |
11381965000 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.410477359 |
|
|
Sep 24 12:42:11 PM UTC 24 |
Sep 24 12:42:15 PM UTC 24 |
170875651 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.3440056704 |
|
|
Sep 24 12:42:11 PM UTC 24 |
Sep 24 12:42:15 PM UTC 24 |
243621576 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.1491474985 |
|
|
Sep 24 12:42:05 PM UTC 24 |
Sep 24 12:42:16 PM UTC 24 |
398374941 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.3111798810 |
|
|
Sep 24 12:41:52 PM UTC 24 |
Sep 24 12:42:16 PM UTC 24 |
386102662 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.2487417886 |
|
|
Sep 24 12:42:05 PM UTC 24 |
Sep 24 12:42:17 PM UTC 24 |
248980962 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2902184825 |
|
|
Sep 24 12:42:12 PM UTC 24 |
Sep 24 12:42:18 PM UTC 24 |
251884308 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.1472170589 |
|
|
Sep 24 12:40:18 PM UTC 24 |
Sep 24 12:42:19 PM UTC 24 |
8853335241 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2658459456 |
|
|
Sep 24 12:42:17 PM UTC 24 |
Sep 24 12:42:19 PM UTC 24 |
12350124 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.433043229 |
|
|
Sep 24 12:42:16 PM UTC 24 |
Sep 24 12:42:19 PM UTC 24 |
21980332 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3086416009 |
|
|
Sep 24 12:42:06 PM UTC 24 |
Sep 24 12:42:20 PM UTC 24 |
312031385 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.814967320 |
|
|
Sep 24 12:42:09 PM UTC 24 |
Sep 24 12:42:20 PM UTC 24 |
171817891 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.685670686 |
|
|
Sep 24 12:42:14 PM UTC 24 |
Sep 24 12:42:21 PM UTC 24 |
113081644 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.3269408114 |
|
|
Sep 24 12:42:06 PM UTC 24 |
Sep 24 12:42:21 PM UTC 24 |
689768977 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.3737726890 |
|
|
Sep 24 12:42:17 PM UTC 24 |
Sep 24 12:42:21 PM UTC 24 |
278264682 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.1491669706 |
|
|
Sep 24 12:42:22 PM UTC 24 |
Sep 24 12:42:44 PM UTC 24 |
2724516657 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2110097086 |
|
|
Sep 24 12:41:55 PM UTC 24 |
Sep 24 12:42:23 PM UTC 24 |
13926160916 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.14718300 |
|
|
Sep 24 12:42:14 PM UTC 24 |
Sep 24 12:42:24 PM UTC 24 |
785078638 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3758169083 |
|
|
Sep 24 12:42:14 PM UTC 24 |
Sep 24 12:42:24 PM UTC 24 |
295974429 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.3297052651 |
|
|
Sep 24 12:42:20 PM UTC 24 |
Sep 24 12:42:24 PM UTC 24 |
32927196 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.3935324510 |
|
|
Sep 24 12:42:05 PM UTC 24 |
Sep 24 12:42:24 PM UTC 24 |
2328585138 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.4024137651 |
|
|
Sep 24 12:42:14 PM UTC 24 |
Sep 24 12:42:25 PM UTC 24 |
246118592 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.749940373 |
|
|
Sep 24 12:42:24 PM UTC 24 |
Sep 24 12:42:26 PM UTC 24 |
35759604 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.3748653339 |
|
|
Sep 24 12:42:42 PM UTC 24 |
Sep 24 12:42:45 PM UTC 24 |
84905785 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4068956332 |
|
|
Sep 24 12:42:25 PM UTC 24 |
Sep 24 12:42:27 PM UTC 24 |
35880788 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.2791646027 |
|
|
Sep 24 12:42:15 PM UTC 24 |
Sep 24 12:42:28 PM UTC 24 |
1668239271 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.472502610 |
|
|
Sep 24 12:42:14 PM UTC 24 |
Sep 24 12:42:29 PM UTC 24 |
1089273259 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.4005634036 |
|
|
Sep 24 12:42:19 PM UTC 24 |
Sep 24 12:42:29 PM UTC 24 |
386807791 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2537587836 |
|
|
Sep 24 12:42:25 PM UTC 24 |
Sep 24 12:42:29 PM UTC 24 |
42941613 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.3179696655 |
|
|
Sep 24 12:42:26 PM UTC 24 |
Sep 24 12:42:32 PM UTC 24 |
92586680 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2978872565 |
|
|
Sep 24 12:42:11 PM UTC 24 |
Sep 24 12:42:33 PM UTC 24 |
384572975 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3521225442 |
|
|
Sep 24 12:42:02 PM UTC 24 |
Sep 24 12:42:33 PM UTC 24 |
3382966460 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.1390690701 |
|
|
Sep 24 12:40:41 PM UTC 24 |
Sep 24 12:42:35 PM UTC 24 |
23951739779 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.2941751794 |
|
|
Sep 24 12:42:25 PM UTC 24 |
Sep 24 12:42:35 PM UTC 24 |
92388485 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.892941524 |
|
|
Sep 24 12:42:21 PM UTC 24 |
Sep 24 12:42:35 PM UTC 24 |
433132609 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.1063713515 |
|
|
Sep 24 12:42:34 PM UTC 24 |
Sep 24 12:42:37 PM UTC 24 |
18051419 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.879007534 |
|
|
Sep 24 12:42:22 PM UTC 24 |
Sep 24 12:42:37 PM UTC 24 |
615639019 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.4185692917 |
|
|
Sep 24 12:42:34 PM UTC 24 |
Sep 24 12:42:38 PM UTC 24 |
36116663 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.459859718 |
|
|
Sep 24 12:42:36 PM UTC 24 |
Sep 24 12:42:38 PM UTC 24 |
29552446 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3088588959 |
|
|
Sep 24 12:42:22 PM UTC 24 |
Sep 24 12:42:39 PM UTC 24 |
1004371865 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1400181262 |
|
|
Sep 24 12:41:52 PM UTC 24 |
Sep 24 12:42:39 PM UTC 24 |
1083357602 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2855511053 |
|
|
Sep 24 12:41:27 PM UTC 24 |
Sep 24 12:42:39 PM UTC 24 |
1876691851 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.92635140 |
|
|
Sep 24 12:42:21 PM UTC 24 |
Sep 24 12:42:39 PM UTC 24 |
1657919515 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1518618625 |
|
|
Sep 24 12:42:28 PM UTC 24 |
Sep 24 12:42:40 PM UTC 24 |
1484584106 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.3739079234 |
|
|
Sep 24 12:42:38 PM UTC 24 |
Sep 24 12:42:42 PM UTC 24 |
64457117 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.3792330383 |
|
|
Sep 24 12:42:21 PM UTC 24 |
Sep 24 12:42:42 PM UTC 24 |
744333460 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.2804256409 |
|
|
Sep 24 12:42:27 PM UTC 24 |
Sep 24 12:42:42 PM UTC 24 |
629161248 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.1987874686 |
|
|
Sep 24 12:42:40 PM UTC 24 |
Sep 24 12:42:46 PM UTC 24 |
258944065 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.61554183 |
|
|
Sep 24 12:42:30 PM UTC 24 |
Sep 24 12:42:46 PM UTC 24 |
533930347 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1010770607 |
|
|
Sep 24 12:42:44 PM UTC 24 |
Sep 24 12:42:46 PM UTC 24 |
169688368 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2538217867 |
|
|
Sep 24 12:42:43 PM UTC 24 |
Sep 24 12:42:47 PM UTC 24 |
24259938 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.2302796010 |
|
|
Sep 24 12:42:38 PM UTC 24 |
Sep 24 12:42:48 PM UTC 24 |
3305628382 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.143959267 |
|
|
Sep 24 12:42:30 PM UTC 24 |
Sep 24 12:42:49 PM UTC 24 |
355547194 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.174859552 |
|
|
Sep 24 12:42:38 PM UTC 24 |
Sep 24 12:42:49 PM UTC 24 |
537891167 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3019481468 |
|
|
Sep 24 12:42:40 PM UTC 24 |
Sep 24 12:42:50 PM UTC 24 |
383934972 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.3113920661 |
|
|
Sep 24 12:42:19 PM UTC 24 |
Sep 24 12:42:50 PM UTC 24 |
1528752534 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.877326285 |
|
|
Sep 24 12:42:25 PM UTC 24 |
Sep 24 12:42:51 PM UTC 24 |
872420264 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.2042870742 |
|
|
Sep 24 12:42:46 PM UTC 24 |
Sep 24 12:42:52 PM UTC 24 |
182380913 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2877310688 |
|
|
Sep 24 12:42:15 PM UTC 24 |
Sep 24 12:42:53 PM UTC 24 |
2468777422 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.2156085067 |
|
|
Sep 24 12:42:30 PM UTC 24 |
Sep 24 12:42:54 PM UTC 24 |
897309839 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2600080484 |
|
|
Sep 24 12:42:51 PM UTC 24 |
Sep 24 12:42:54 PM UTC 24 |
16537008 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.154304676 |
|
|
Sep 24 12:42:41 PM UTC 24 |
Sep 24 12:42:54 PM UTC 24 |
505616604 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.3638374543 |
|
|
Sep 24 12:43:41 PM UTC 24 |
Sep 24 12:43:43 PM UTC 24 |
18662754 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.799607377 |
|
|
Sep 24 12:42:47 PM UTC 24 |
Sep 24 12:42:54 PM UTC 24 |
1652548083 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.3177389577 |
|
|
Sep 24 12:42:51 PM UTC 24 |
Sep 24 12:42:54 PM UTC 24 |
20463440 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1126648465 |
|
|
Sep 24 12:42:52 PM UTC 24 |
Sep 24 12:42:55 PM UTC 24 |
17813942 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.2389907486 |
|
|
Sep 24 12:43:03 PM UTC 24 |
Sep 24 12:43:41 PM UTC 24 |
1129402270 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.3974056930 |
|
|
Sep 24 12:41:18 PM UTC 24 |
Sep 24 12:42:57 PM UTC 24 |
10583140891 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3775687015 |
|
|
Sep 24 12:42:47 PM UTC 24 |
Sep 24 12:42:58 PM UTC 24 |
466081941 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.3535312909 |
|
|
Sep 24 12:42:45 PM UTC 24 |
Sep 24 12:42:58 PM UTC 24 |
94120342 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.4038352766 |
|
|
Sep 24 12:42:40 PM UTC 24 |
Sep 24 12:42:59 PM UTC 24 |
453725115 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.1583944976 |
|
|
Sep 24 12:42:22 PM UTC 24 |
Sep 24 12:43:41 PM UTC 24 |
4345956412 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.758314534 |
|
|
Sep 24 12:42:59 PM UTC 24 |
Sep 24 12:43:02 PM UTC 24 |
68045290 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3376702655 |
|
|
Sep 24 12:42:55 PM UTC 24 |
Sep 24 12:43:02 PM UTC 24 |
1688856024 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.1900011193 |
|
|
Sep 24 12:42:48 PM UTC 24 |
Sep 24 12:43:02 PM UTC 24 |
776611808 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2107383095 |
|
|
Sep 24 12:42:50 PM UTC 24 |
Sep 24 12:43:04 PM UTC 24 |
678147999 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.1210749379 |
|
|
Sep 24 12:42:46 PM UTC 24 |
Sep 24 12:43:04 PM UTC 24 |
1460531427 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1687821513 |
|
|
Sep 24 12:42:47 PM UTC 24 |
Sep 24 12:43:04 PM UTC 24 |
409802079 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.4034381974 |
|
|
Sep 24 12:43:03 PM UTC 24 |
Sep 24 12:43:05 PM UTC 24 |
15886166 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2870899062 |
|
|
Sep 24 12:43:00 PM UTC 24 |
Sep 24 12:43:05 PM UTC 24 |
206240100 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.1728671471 |
|
|
Sep 24 12:43:25 PM UTC 24 |
Sep 24 12:43:43 PM UTC 24 |
3159205334 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.683713925 |
|
|
Sep 24 12:42:55 PM UTC 24 |
Sep 24 12:43:05 PM UTC 24 |
1862707746 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.3191396258 |
|
|
Sep 24 12:43:03 PM UTC 24 |
Sep 24 12:43:07 PM UTC 24 |
87960529 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2519434378 |
|
|
Sep 24 12:42:56 PM UTC 24 |
Sep 24 12:43:07 PM UTC 24 |
851313461 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.1946881400 |
|
|
Sep 24 12:42:54 PM UTC 24 |
Sep 24 12:43:08 PM UTC 24 |
328293613 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.898071713 |
|
|
Sep 24 12:42:55 PM UTC 24 |
Sep 24 12:43:09 PM UTC 24 |
1565420903 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.507513061 |
|
|
Sep 24 12:43:08 PM UTC 24 |
Sep 24 12:43:11 PM UTC 24 |
22845069 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2370005527 |
|
|
Sep 24 12:43:09 PM UTC 24 |
Sep 24 12:43:11 PM UTC 24 |
40311770 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.4183264423 |
|
|
Sep 24 12:42:55 PM UTC 24 |
Sep 24 12:43:12 PM UTC 24 |
298165199 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.373220285 |
|
|
Sep 24 12:43:09 PM UTC 24 |
Sep 24 12:43:12 PM UTC 24 |
28608709 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.2432227610 |
|
|
Sep 24 12:42:45 PM UTC 24 |
Sep 24 12:43:13 PM UTC 24 |
189338792 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.4124170034 |
|
|
Sep 24 12:42:36 PM UTC 24 |
Sep 24 12:43:13 PM UTC 24 |
277221124 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2089782899 |
|
|
Sep 24 12:43:03 PM UTC 24 |
Sep 24 12:43:13 PM UTC 24 |
387041601 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3710009773 |
|
|
Sep 24 12:41:42 PM UTC 24 |
Sep 24 12:43:15 PM UTC 24 |
30784378923 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.4157490778 |
|
|
Sep 24 12:42:55 PM UTC 24 |
Sep 24 12:43:16 PM UTC 24 |
814977113 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.3909008875 |
|
|
Sep 24 12:42:58 PM UTC 24 |
Sep 24 12:43:17 PM UTC 24 |
682129989 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.1634466196 |
|
|
Sep 24 12:43:15 PM UTC 24 |
Sep 24 12:43:18 PM UTC 24 |
75484672 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.3372857613 |
|
|
Sep 24 12:43:14 PM UTC 24 |
Sep 24 12:43:19 PM UTC 24 |
124640076 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.280073109 |
|
|
Sep 24 12:43:07 PM UTC 24 |
Sep 24 12:43:19 PM UTC 24 |
821314924 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.2536789458 |
|
|
Sep 24 12:43:05 PM UTC 24 |
Sep 24 12:43:19 PM UTC 24 |
196125078 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.3921033177 |
|
|
Sep 24 12:43:14 PM UTC 24 |
Sep 24 12:43:22 PM UTC 24 |
986664625 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.2041798933 |
|
|
Sep 24 12:43:17 PM UTC 24 |
Sep 24 12:43:43 PM UTC 24 |
2225824094 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3489604102 |
|
|
Sep 24 12:43:20 PM UTC 24 |
Sep 24 12:43:23 PM UTC 24 |
49931406 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.2506796499 |
|
|
Sep 24 12:43:12 PM UTC 24 |
Sep 24 12:43:23 PM UTC 24 |
1276275051 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2527022362 |
|
|
Sep 24 12:43:20 PM UTC 24 |
Sep 24 12:43:23 PM UTC 24 |
31285325 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3532952038 |
|
|
Sep 24 12:43:05 PM UTC 24 |
Sep 24 12:43:23 PM UTC 24 |
2366671310 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.1930304163 |
|
|
Sep 24 12:43:20 PM UTC 24 |
Sep 24 12:43:24 PM UTC 24 |
38011297 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.982655073 |
|
|
Sep 24 12:43:05 PM UTC 24 |
Sep 24 12:43:25 PM UTC 24 |
370782283 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2115035314 |
|
|
Sep 24 12:43:07 PM UTC 24 |
Sep 24 12:43:27 PM UTC 24 |
5554257257 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.3601934736 |
|
|
Sep 24 12:39:10 PM UTC 24 |
Sep 24 12:43:28 PM UTC 24 |
70898701346 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.783014453 |
|
|
Sep 24 12:43:14 PM UTC 24 |
Sep 24 12:43:30 PM UTC 24 |
290791397 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.3163120802 |
|
|
Sep 24 12:43:07 PM UTC 24 |
Sep 24 12:43:31 PM UTC 24 |
870966073 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.2034106322 |
|
|
Sep 24 12:43:16 PM UTC 24 |
Sep 24 12:43:32 PM UTC 24 |
794141737 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.44923111 |
|
|
Sep 24 12:43:24 PM UTC 24 |
Sep 24 12:43:32 PM UTC 24 |
143263435 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.2828503455 |
|
|
Sep 24 12:43:24 PM UTC 24 |
Sep 24 12:43:33 PM UTC 24 |
140796175 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.1409294294 |
|
|
Sep 24 12:43:11 PM UTC 24 |
Sep 24 12:43:33 PM UTC 24 |
708835658 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.3601829301 |
|
|
Sep 24 12:43:15 PM UTC 24 |
Sep 24 12:43:34 PM UTC 24 |
860207013 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.2060931002 |
|
|
Sep 24 12:40:06 PM UTC 24 |
Sep 24 12:43:34 PM UTC 24 |
39727749773 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.1638788593 |
|
|
Sep 24 12:43:32 PM UTC 24 |
Sep 24 12:43:35 PM UTC 24 |
55818871 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.1390829319 |
|
|
Sep 24 12:42:53 PM UTC 24 |
Sep 24 12:43:35 PM UTC 24 |
406354190 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3754468824 |
|
|
Sep 24 12:43:33 PM UTC 24 |
Sep 24 12:43:36 PM UTC 24 |
15071196 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.3569539495 |
|
|
Sep 24 12:43:24 PM UTC 24 |
Sep 24 12:43:37 PM UTC 24 |
572269076 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3650027467 |
|
|
Sep 24 12:43:27 PM UTC 24 |
Sep 24 12:43:43 PM UTC 24 |
302743066 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.133061252 |
|
|
Sep 24 12:43:33 PM UTC 24 |
Sep 24 12:43:38 PM UTC 24 |
50533979 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.3342267157 |
|
|
Sep 24 12:43:24 PM UTC 24 |
Sep 24 12:43:38 PM UTC 24 |
1070960741 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.767327149 |
|
|
Sep 24 12:43:35 PM UTC 24 |
Sep 24 12:43:40 PM UTC 24 |
63766485 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.1246374493 |
|
|
Sep 24 12:43:24 PM UTC 24 |
Sep 24 12:43:41 PM UTC 24 |
1473720985 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.657264001 |
|
|
Sep 24 12:43:26 PM UTC 24 |
Sep 24 12:43:41 PM UTC 24 |
556942199 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.2199592836 |
|
|
Sep 24 12:38:24 PM UTC 24 |
Sep 24 12:43:43 PM UTC 24 |
18680592627 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3005862876 |
|
|
Sep 24 12:43:42 PM UTC 24 |
Sep 24 12:43:44 PM UTC 24 |
40198662 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.932138274 |
|
|
Sep 24 12:41:34 PM UTC 24 |
Sep 24 12:43:46 PM UTC 24 |
14243372442 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2890768758 |
|
|
Sep 24 12:43:35 PM UTC 24 |
Sep 24 12:43:46 PM UTC 24 |
60352914 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2108553551 |
|
|
Sep 24 12:43:36 PM UTC 24 |
Sep 24 12:43:46 PM UTC 24 |
932414266 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3652114487 |
|
|
Sep 24 12:43:38 PM UTC 24 |
Sep 24 12:43:47 PM UTC 24 |
1033328976 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.1081120436 |
|
|
Sep 24 12:43:42 PM UTC 24 |
Sep 24 12:43:48 PM UTC 24 |
82927476 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.2901192335 |
|
|
Sep 24 12:43:22 PM UTC 24 |
Sep 24 12:43:48 PM UTC 24 |
617630666 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.1076650689 |
|
|
Sep 24 12:43:07 PM UTC 24 |
Sep 24 12:43:48 PM UTC 24 |
634114581 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2060512119 |
|
|
Sep 24 12:43:42 PM UTC 24 |
Sep 24 12:43:48 PM UTC 24 |
91001819 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.2398281441 |
|
|
Sep 24 12:43:44 PM UTC 24 |
Sep 24 12:43:49 PM UTC 24 |
85423455 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.3395227769 |
|
|
Sep 24 12:43:44 PM UTC 24 |
Sep 24 12:43:49 PM UTC 24 |
89666093 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.3178824453 |
|
|
Sep 24 12:43:36 PM UTC 24 |
Sep 24 12:43:49 PM UTC 24 |
366266537 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2176069384 |
|
|
Sep 24 12:43:47 PM UTC 24 |
Sep 24 12:43:50 PM UTC 24 |
16617445 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3959029832 |
|
|
Sep 24 12:43:48 PM UTC 24 |
Sep 24 12:43:51 PM UTC 24 |
32511420 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1690941294 |
|
|
Sep 24 12:43:47 PM UTC 24 |
Sep 24 12:43:51 PM UTC 24 |
28098500 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2620863692 |
|
|
Sep 24 12:43:50 PM UTC 24 |
Sep 24 12:43:53 PM UTC 24 |
46901491 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.1979153063 |
|
|
Sep 24 12:43:38 PM UTC 24 |
Sep 24 12:43:54 PM UTC 24 |
405747753 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.110169204 |
|
|
Sep 24 12:43:44 PM UTC 24 |
Sep 24 12:43:56 PM UTC 24 |
204496200 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1039455780 |
|
|
Sep 24 12:43:30 PM UTC 24 |
Sep 24 12:44:36 PM UTC 24 |
44252248440 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2205017879 |
|
|
Sep 24 12:42:33 PM UTC 24 |
Sep 24 12:43:57 PM UTC 24 |
29203814708 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.398372046 |
|
|
Sep 24 12:44:35 PM UTC 24 |
Sep 24 12:44:38 PM UTC 24 |
59323780 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.3514245447 |
|
|
Sep 24 12:43:36 PM UTC 24 |
Sep 24 12:43:58 PM UTC 24 |
2735117418 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.4219244574 |
|
|
Sep 24 12:43:45 PM UTC 24 |
Sep 24 12:43:58 PM UTC 24 |
4296014314 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.466032106 |
|
|
Sep 24 12:43:33 PM UTC 24 |
Sep 24 12:43:59 PM UTC 24 |
771838503 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2541033231 |
|
|
Sep 24 12:43:56 PM UTC 24 |
Sep 24 12:43:59 PM UTC 24 |
156157293 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.3893662109 |
|
|
Sep 24 12:43:50 PM UTC 24 |
Sep 24 12:43:59 PM UTC 24 |
348109635 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.289164971 |
|
|
Sep 24 12:43:58 PM UTC 24 |
Sep 24 12:44:01 PM UTC 24 |
44157639 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.3939987984 |
|
|
Sep 24 12:43:42 PM UTC 24 |
Sep 24 12:44:01 PM UTC 24 |
685213178 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.990190283 |
|
|
Sep 24 12:43:50 PM UTC 24 |
Sep 24 12:44:01 PM UTC 24 |
608331371 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.3062074261 |
|
|
Sep 24 12:43:54 PM UTC 24 |
Sep 24 12:44:37 PM UTC 24 |
1241299521 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.3205476374 |
|
|
Sep 24 12:43:37 PM UTC 24 |
Sep 24 12:44:01 PM UTC 24 |
1530259248 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.738711100 |
|
|
Sep 24 12:43:50 PM UTC 24 |
Sep 24 12:44:02 PM UTC 24 |
2472805477 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.3652363492 |
|
|
Sep 24 12:43:44 PM UTC 24 |
Sep 24 12:44:02 PM UTC 24 |
365003192 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.3483515765 |
|
|
Sep 24 12:43:44 PM UTC 24 |
Sep 24 12:44:02 PM UTC 24 |
251640766 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.4161892939 |
|
|
Sep 24 12:43:58 PM UTC 24 |
Sep 24 12:44:03 PM UTC 24 |
71614878 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.3591724786 |
|
|
Sep 24 12:43:59 PM UTC 24 |
Sep 24 12:44:04 PM UTC 24 |
153955340 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2708081266 |
|
|
Sep 24 12:43:46 PM UTC 24 |
Sep 24 12:44:05 PM UTC 24 |
1169359819 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.236370064 |
|
|
Sep 24 12:43:59 PM UTC 24 |
Sep 24 12:44:05 PM UTC 24 |
78438282 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.626594960 |
|
|
Sep 24 12:41:52 PM UTC 24 |
Sep 24 12:45:35 PM UTC 24 |
12980561124 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.519873243 |
|
|
Sep 24 12:41:45 PM UTC 24 |
Sep 24 12:44:05 PM UTC 24 |
5975092086 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.1830547681 |
|
|
Sep 24 12:43:51 PM UTC 24 |
Sep 24 12:44:06 PM UTC 24 |
715790725 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.597342836 |
|
|
Sep 24 12:44:04 PM UTC 24 |
Sep 24 12:44:06 PM UTC 24 |
172125438 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1469113081 |
|
|
Sep 24 12:43:50 PM UTC 24 |
Sep 24 12:44:06 PM UTC 24 |
244385030 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.161157395 |
|
|
Sep 24 12:43:52 PM UTC 24 |
Sep 24 12:44:07 PM UTC 24 |
946699802 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1351696168 |
|
|
Sep 24 12:44:05 PM UTC 24 |
Sep 24 12:44:07 PM UTC 24 |
52404507 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.3006334817 |
|
|
Sep 24 12:43:52 PM UTC 24 |
Sep 24 12:44:09 PM UTC 24 |
760976196 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1673273609 |
|
|
Sep 24 12:44:19 PM UTC 24 |
Sep 24 12:44:37 PM UTC 24 |
1581645552 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.660702383 |
|
|
Sep 24 12:44:07 PM UTC 24 |
Sep 24 12:44:12 PM UTC 24 |
261654508 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.3331109959 |
|
|
Sep 24 12:44:04 PM UTC 24 |
Sep 24 12:44:13 PM UTC 24 |
1115074633 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.586418353 |
|
|
Sep 24 12:44:02 PM UTC 24 |
Sep 24 12:44:15 PM UTC 24 |
1128386340 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.261790369 |
|
|
Sep 24 12:44:00 PM UTC 24 |
Sep 24 12:44:15 PM UTC 24 |
886674741 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.2614096803 |
|
|
Sep 24 12:44:00 PM UTC 24 |
Sep 24 12:44:16 PM UTC 24 |
380398318 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.3362992588 |
|
|
Sep 24 12:43:50 PM UTC 24 |
Sep 24 12:44:16 PM UTC 24 |
806069620 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2037208880 |
|
|
Sep 24 12:44:07 PM UTC 24 |
Sep 24 12:44:17 PM UTC 24 |
576584631 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.1928709747 |
|
|
Sep 24 12:44:15 PM UTC 24 |
Sep 24 12:44:17 PM UTC 24 |
19533260 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3217181202 |
|
|
Sep 24 12:44:02 PM UTC 24 |
Sep 24 12:44:18 PM UTC 24 |
1186668429 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.1208878815 |
|
|
Sep 24 12:44:02 PM UTC 24 |
Sep 24 12:44:18 PM UTC 24 |
5532158389 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.243547146 |
|
|
Sep 24 12:44:16 PM UTC 24 |
Sep 24 12:44:18 PM UTC 24 |
23806692 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.3013070863 |
|
|
Sep 24 12:44:08 PM UTC 24 |
Sep 24 12:44:18 PM UTC 24 |
560133508 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.3498265125 |
|
|
Sep 24 12:44:04 PM UTC 24 |
Sep 24 12:44:19 PM UTC 24 |
435533586 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3285630103 |
|
|
Sep 24 12:44:07 PM UTC 24 |
Sep 24 12:44:20 PM UTC 24 |
1579991125 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1682800493 |
|
|
Sep 24 12:44:16 PM UTC 24 |
Sep 24 12:44:21 PM UTC 24 |
70727584 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.2693064449 |
|
|
Sep 24 12:44:19 PM UTC 24 |
Sep 24 12:44:37 PM UTC 24 |
309967806 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3091177496 |
|
|
Sep 24 12:44:08 PM UTC 24 |
Sep 24 12:44:22 PM UTC 24 |
507461096 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.2087840228 |
|
|
Sep 24 12:44:08 PM UTC 24 |
Sep 24 12:44:23 PM UTC 24 |
274385408 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.80098197 |
|
|
Sep 24 12:44:17 PM UTC 24 |
Sep 24 12:44:23 PM UTC 24 |
49387963 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.491971140 |
|
|
Sep 24 12:44:07 PM UTC 24 |
Sep 24 12:44:24 PM UTC 24 |
647178053 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.406223256 |
|
|
Sep 24 12:44:10 PM UTC 24 |
Sep 24 12:44:24 PM UTC 24 |
430084827 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.1541465434 |
|
|
Sep 24 12:44:19 PM UTC 24 |
Sep 24 12:44:25 PM UTC 24 |
387647824 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.1439699770 |
|
|
Sep 24 12:44:23 PM UTC 24 |
Sep 24 12:44:25 PM UTC 24 |
30896577 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.887910298 |
|
|
Sep 24 12:44:23 PM UTC 24 |
Sep 24 12:44:26 PM UTC 24 |
87136036 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2323234026 |
|
|
Sep 24 12:44:24 PM UTC 24 |
Sep 24 12:44:26 PM UTC 24 |
12912940 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.141371551 |
|
|
Sep 24 12:44:19 PM UTC 24 |
Sep 24 12:44:28 PM UTC 24 |
528244300 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.354282977 |
|
|
Sep 24 12:44:19 PM UTC 24 |
Sep 24 12:44:29 PM UTC 24 |
331438046 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.2163742597 |
|
|
Sep 24 12:44:27 PM UTC 24 |
Sep 24 12:44:30 PM UTC 24 |
62707871 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3237429552 |
|
|
Sep 24 12:44:25 PM UTC 24 |
Sep 24 12:44:32 PM UTC 24 |
115267066 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.1730502450 |
|
|
Sep 24 12:44:20 PM UTC 24 |
Sep 24 12:44:34 PM UTC 24 |
1024962280 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.3602787664 |
|
|
Sep 24 12:44:19 PM UTC 24 |
Sep 24 12:44:35 PM UTC 24 |
378955218 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.3718580097 |
|
|
Sep 24 12:44:25 PM UTC 24 |
Sep 24 12:44:35 PM UTC 24 |
76395542 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.4174119329 |
|
|
Sep 24 12:45:11 PM UTC 24 |
Sep 24 12:45:37 PM UTC 24 |
302328527 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.479115952 |
|
|
Sep 24 12:41:59 PM UTC 24 |
Sep 24 12:44:39 PM UTC 24 |
5381846990 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1383120395 |
|
|
Sep 24 12:44:36 PM UTC 24 |
Sep 24 12:44:39 PM UTC 24 |
13205839 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.2660682822 |
|
|
Sep 24 12:44:30 PM UTC 24 |
Sep 24 12:44:39 PM UTC 24 |
277333546 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.1304320537 |
|
|
Sep 24 12:44:07 PM UTC 24 |
Sep 24 12:44:40 PM UTC 24 |
400984264 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.3860817348 |
|
|
Sep 24 12:43:59 PM UTC 24 |
Sep 24 12:44:40 PM UTC 24 |
654555146 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3006385171 |
|
|
Sep 24 12:44:36 PM UTC 24 |
Sep 24 12:44:41 PM UTC 24 |
365137122 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.3264732738 |
|
|
Sep 24 12:44:38 PM UTC 24 |
Sep 24 12:44:42 PM UTC 24 |
71691505 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.4163977442 |
|
|
Sep 24 12:44:30 PM UTC 24 |
Sep 24 12:44:45 PM UTC 24 |
375037674 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2160868319 |
|
|
Sep 24 12:44:42 PM UTC 24 |
Sep 24 12:44:45 PM UTC 24 |
30071294 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1597086471 |
|
|
Sep 24 12:43:54 PM UTC 24 |
Sep 24 12:44:46 PM UTC 24 |
1672342687 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.2779908892 |
|
|
Sep 24 12:41:34 PM UTC 24 |
Sep 24 12:44:47 PM UTC 24 |
4971595290 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4209941159 |
|
|
Sep 24 12:44:46 PM UTC 24 |
Sep 24 12:44:48 PM UTC 24 |
16434848 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2113666923 |
|
|
Sep 24 12:45:03 PM UTC 24 |
Sep 24 12:45:33 PM UTC 24 |
947701189 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.3133489888 |
|
|
Sep 24 12:44:27 PM UTC 24 |
Sep 24 12:44:49 PM UTC 24 |
738907394 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1973576520 |
|
|
Sep 24 12:44:40 PM UTC 24 |
Sep 24 12:44:49 PM UTC 24 |
404605591 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.1006690141 |
|
|
Sep 24 12:44:26 PM UTC 24 |
Sep 24 12:44:49 PM UTC 24 |
5598648109 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.4004041319 |
|
|
Sep 24 12:44:46 PM UTC 24 |
Sep 24 12:44:49 PM UTC 24 |
86022438 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.2217637089 |
|
|
Sep 24 12:44:38 PM UTC 24 |
Sep 24 12:44:50 PM UTC 24 |
64711661 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.2837065294 |
|
|
Sep 24 12:44:28 PM UTC 24 |
Sep 24 12:44:50 PM UTC 24 |
451055340 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.2201142181 |
|
|
Sep 24 12:43:47 PM UTC 24 |
Sep 24 12:44:51 PM UTC 24 |
5788141881 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.3905815200 |
|
|
Sep 24 12:44:38 PM UTC 24 |
Sep 24 12:44:51 PM UTC 24 |
288740464 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.720084965 |
|
|
Sep 24 12:42:50 PM UTC 24 |
Sep 24 12:44:51 PM UTC 24 |
3373245127 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1601707640 |
|
|
Sep 24 12:45:16 PM UTC 24 |
Sep 24 12:45:33 PM UTC 24 |
482075975 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.865574362 |
|
|
Sep 24 12:44:17 PM UTC 24 |
Sep 24 12:44:51 PM UTC 24 |
877491815 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.179743169 |
|
|
Sep 24 12:44:41 PM UTC 24 |
Sep 24 12:44:52 PM UTC 24 |
904372787 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2258247106 |
|
|
Sep 24 12:40:52 PM UTC 24 |
Sep 24 12:44:53 PM UTC 24 |
45888509265 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.2992363439 |
|
|
Sep 24 12:45:13 PM UTC 24 |
Sep 24 12:45:29 PM UTC 24 |
460738798 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.1377459927 |
|
|
Sep 24 12:44:48 PM UTC 24 |
Sep 24 12:44:53 PM UTC 24 |
323174297 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.3896411626 |
|
|
Sep 24 12:44:38 PM UTC 24 |
Sep 24 12:44:54 PM UTC 24 |
1401136714 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.1033185981 |
|
|
Sep 24 12:44:53 PM UTC 24 |
Sep 24 12:44:55 PM UTC 24 |
38790941 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2836908534 |
|
|
Sep 24 12:44:53 PM UTC 24 |
Sep 24 12:44:56 PM UTC 24 |
15189406 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.2319964453 |
|
|
Sep 24 12:44:49 PM UTC 24 |
Sep 24 12:44:56 PM UTC 24 |
407733008 ps |