| T823 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3847000697 |
|
|
Sep 24 12:44:53 PM UTC 24 |
Sep 24 12:44:57 PM UTC 24 |
69679717 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.2705733975 |
|
|
Sep 24 12:44:24 PM UTC 24 |
Sep 24 12:44:58 PM UTC 24 |
1414811120 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.356884481 |
|
|
Sep 24 12:44:41 PM UTC 24 |
Sep 24 12:44:59 PM UTC 24 |
1674793299 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.1943209112 |
|
|
Sep 24 12:44:40 PM UTC 24 |
Sep 24 12:44:59 PM UTC 24 |
3362826351 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1611304 |
|
|
Sep 24 12:44:51 PM UTC 24 |
Sep 24 12:45:01 PM UTC 24 |
1422936310 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.1325690218 |
|
|
Sep 24 12:44:55 PM UTC 24 |
Sep 24 12:45:01 PM UTC 24 |
139731705 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.618730496 |
|
|
Sep 24 12:44:49 PM UTC 24 |
Sep 24 12:45:02 PM UTC 24 |
461091293 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3614744965 |
|
|
Sep 24 12:45:00 PM UTC 24 |
Sep 24 12:45:03 PM UTC 24 |
69391654 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.2752334794 |
|
|
Sep 24 12:44:50 PM UTC 24 |
Sep 24 12:45:03 PM UTC 24 |
566745189 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2459924303 |
|
|
Sep 24 12:45:03 PM UTC 24 |
Sep 24 12:45:05 PM UTC 24 |
21605362 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3814778717 |
|
|
Sep 24 12:43:47 PM UTC 24 |
Sep 24 12:45:05 PM UTC 24 |
2200156200 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.607656892 |
|
|
Sep 24 12:44:57 PM UTC 24 |
Sep 24 12:45:05 PM UTC 24 |
553510256 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.509519057 |
|
|
Sep 24 12:44:55 PM UTC 24 |
Sep 24 12:45:06 PM UTC 24 |
72173210 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1072303419 |
|
|
Sep 24 12:44:51 PM UTC 24 |
Sep 24 12:45:06 PM UTC 24 |
350689532 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.711589891 |
|
|
Sep 24 12:45:04 PM UTC 24 |
Sep 24 12:45:08 PM UTC 24 |
48111157 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1341844828 |
|
|
Sep 24 12:44:51 PM UTC 24 |
Sep 24 12:45:09 PM UTC 24 |
5475551733 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.988368456 |
|
|
Sep 24 12:45:03 PM UTC 24 |
Sep 24 12:45:09 PM UTC 24 |
139422329 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.4080007173 |
|
|
Sep 24 12:44:49 PM UTC 24 |
Sep 24 12:45:10 PM UTC 24 |
1343711420 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.3563987013 |
|
|
Sep 24 12:45:04 PM UTC 24 |
Sep 24 12:45:10 PM UTC 24 |
214517472 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1664672688 |
|
|
Sep 24 12:44:55 PM UTC 24 |
Sep 24 12:45:10 PM UTC 24 |
1754320971 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.741310895 |
|
|
Sep 24 12:45:15 PM UTC 24 |
Sep 24 12:45:31 PM UTC 24 |
242299612 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2482712708 |
|
|
Sep 24 12:44:58 PM UTC 24 |
Sep 24 12:45:10 PM UTC 24 |
903023545 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.4191313150 |
|
|
Sep 24 12:43:38 PM UTC 24 |
Sep 24 12:45:11 PM UTC 24 |
2584458212 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2292896840 |
|
|
Sep 24 12:44:55 PM UTC 24 |
Sep 24 12:45:11 PM UTC 24 |
353794660 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.3065626783 |
|
|
Sep 24 12:44:57 PM UTC 24 |
Sep 24 12:45:12 PM UTC 24 |
687219643 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.152506555 |
|
|
Sep 24 12:42:41 PM UTC 24 |
Sep 24 12:45:12 PM UTC 24 |
15803846881 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1251206413 |
|
|
Sep 24 12:45:11 PM UTC 24 |
Sep 24 12:45:13 PM UTC 24 |
23255261 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3984537208 |
|
|
Sep 24 12:45:11 PM UTC 24 |
Sep 24 12:45:14 PM UTC 24 |
56386873 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.2151463766 |
|
|
Sep 24 12:44:38 PM UTC 24 |
Sep 24 12:45:15 PM UTC 24 |
349384552 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.2897201661 |
|
|
Sep 24 12:44:57 PM UTC 24 |
Sep 24 12:45:15 PM UTC 24 |
865841303 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3267447328 |
|
|
Sep 24 12:45:06 PM UTC 24 |
Sep 24 12:45:16 PM UTC 24 |
161102465 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.3174048131 |
|
|
Sep 24 12:45:06 PM UTC 24 |
Sep 24 12:45:17 PM UTC 24 |
366339309 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.1650800155 |
|
|
Sep 24 12:44:47 PM UTC 24 |
Sep 24 12:45:17 PM UTC 24 |
271223729 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.212029835 |
|
|
Sep 24 12:45:13 PM UTC 24 |
Sep 24 12:45:18 PM UTC 24 |
188698599 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.2604706824 |
|
|
Sep 24 12:45:15 PM UTC 24 |
Sep 24 12:45:19 PM UTC 24 |
75641359 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.4081801195 |
|
|
Sep 24 12:45:18 PM UTC 24 |
Sep 24 12:45:20 PM UTC 24 |
79384658 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.876355195 |
|
|
Sep 24 12:45:11 PM UTC 24 |
Sep 24 12:45:21 PM UTC 24 |
354453392 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.1948980818 |
|
|
Sep 24 12:41:58 PM UTC 24 |
Sep 24 12:45:21 PM UTC 24 |
36670579007 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.4122235930 |
|
|
Sep 24 12:45:13 PM UTC 24 |
Sep 24 12:45:22 PM UTC 24 |
138153600 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.3031119199 |
|
|
Sep 24 12:42:41 PM UTC 24 |
Sep 24 12:45:23 PM UTC 24 |
4929171961 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.3764254550 |
|
|
Sep 24 12:45:07 PM UTC 24 |
Sep 24 12:45:23 PM UTC 24 |
1025687842 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2596651227 |
|
|
Sep 24 12:45:07 PM UTC 24 |
Sep 24 12:45:23 PM UTC 24 |
755888499 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3232856031 |
|
|
Sep 24 12:44:55 PM UTC 24 |
Sep 24 12:45:29 PM UTC 24 |
260246607 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.1712816596 |
|
|
Sep 24 12:45:06 PM UTC 24 |
Sep 24 12:45:24 PM UTC 24 |
545953495 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.3435780104 |
|
|
Sep 24 12:45:15 PM UTC 24 |
Sep 24 12:45:25 PM UTC 24 |
300375264 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.2870881958 |
|
|
Sep 24 12:45:09 PM UTC 24 |
Sep 24 12:45:27 PM UTC 24 |
516322966 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.3659243915 |
|
|
Sep 24 12:45:16 PM UTC 24 |
Sep 24 12:45:28 PM UTC 24 |
274561616 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.1584760726 |
|
|
Sep 24 12:44:14 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
4233166942 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3357598196 |
|
|
Sep 24 12:43:18 PM UTC 24 |
Sep 24 12:45:54 PM UTC 24 |
4581065795 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.87767821 |
|
|
Sep 24 12:44:33 PM UTC 24 |
Sep 24 12:45:55 PM UTC 24 |
2008848368 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2365220250 |
|
|
Sep 24 12:44:21 PM UTC 24 |
Sep 24 12:45:59 PM UTC 24 |
13433246980 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3363295389 |
|
|
Sep 24 12:45:10 PM UTC 24 |
Sep 24 12:46:12 PM UTC 24 |
3006695563 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2931676403 |
|
|
Sep 24 12:45:00 PM UTC 24 |
Sep 24 12:46:13 PM UTC 24 |
4453322826 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3579145926 |
|
|
Sep 24 12:45:17 PM UTC 24 |
Sep 24 12:46:25 PM UTC 24 |
23618503549 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.312407996 |
|
|
Sep 24 12:44:31 PM UTC 24 |
Sep 24 12:46:26 PM UTC 24 |
4816645948 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.3912852566 |
|
|
Sep 24 12:44:59 PM UTC 24 |
Sep 24 12:46:26 PM UTC 24 |
5944916114 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.441981234 |
|
|
Sep 24 12:42:58 PM UTC 24 |
Sep 24 12:46:52 PM UTC 24 |
54524691727 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.112985905 |
|
|
Sep 24 12:44:04 PM UTC 24 |
Sep 24 12:46:57 PM UTC 24 |
4596867054 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2486386510 |
|
|
Sep 24 12:45:17 PM UTC 24 |
Sep 24 12:47:04 PM UTC 24 |
31355039469 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3451964890 |
|
|
Sep 24 12:44:23 PM UTC 24 |
Sep 24 12:47:05 PM UTC 24 |
4890584228 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.1430957960 |
|
|
Sep 24 12:40:31 PM UTC 24 |
Sep 24 12:47:17 PM UTC 24 |
43306797932 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2988776896 |
|
|
Sep 24 12:44:04 PM UTC 24 |
Sep 24 12:47:25 PM UTC 24 |
22102307782 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1064048645 |
|
|
Sep 24 12:42:30 PM UTC 24 |
Sep 24 12:47:32 PM UTC 24 |
35561629668 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.1122790392 |
|
|
Sep 24 12:41:00 PM UTC 24 |
Sep 24 12:47:32 PM UTC 24 |
63687519125 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.1985711096 |
|
|
Sep 24 12:44:41 PM UTC 24 |
Sep 24 12:47:38 PM UTC 24 |
6581868459 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2983906609 |
|
|
Sep 24 12:42:09 PM UTC 24 |
Sep 24 12:47:42 PM UTC 24 |
9787876282 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3252023178 |
|
|
Sep 24 12:44:41 PM UTC 24 |
Sep 24 12:47:52 PM UTC 24 |
133846594631 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.855661989 |
|
|
Sep 24 12:44:53 PM UTC 24 |
Sep 24 12:48:42 PM UTC 24 |
9241496839 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.4227256105 |
|
|
Sep 24 12:44:13 PM UTC 24 |
Sep 24 12:49:51 PM UTC 24 |
36932548699 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2011850110 |
|
|
Sep 24 12:45:19 PM UTC 24 |
Sep 24 12:45:22 PM UTC 24 |
210415526 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1550680651 |
|
|
Sep 24 12:45:20 PM UTC 24 |
Sep 24 12:45:22 PM UTC 24 |
97320317 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2597263720 |
|
|
Sep 24 12:45:22 PM UTC 24 |
Sep 24 12:45:25 PM UTC 24 |
81140068 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1656189921 |
|
|
Sep 24 12:45:24 PM UTC 24 |
Sep 24 12:45:27 PM UTC 24 |
34953902 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2985839877 |
|
|
Sep 24 12:45:24 PM UTC 24 |
Sep 24 12:45:27 PM UTC 24 |
48125931 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.263201839 |
|
|
Sep 24 12:45:24 PM UTC 24 |
Sep 24 12:45:27 PM UTC 24 |
39845556 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.38579872 |
|
|
Sep 24 12:45:22 PM UTC 24 |
Sep 24 12:45:27 PM UTC 24 |
670715852 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1212969012 |
|
|
Sep 24 12:45:24 PM UTC 24 |
Sep 24 12:45:28 PM UTC 24 |
57153342 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1725627603 |
|
|
Sep 24 12:45:26 PM UTC 24 |
Sep 24 12:45:28 PM UTC 24 |
41612406 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4035887216 |
|
|
Sep 24 12:45:26 PM UTC 24 |
Sep 24 12:45:28 PM UTC 24 |
24071219 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.622630938 |
|
|
Sep 24 12:45:26 PM UTC 24 |
Sep 24 12:45:29 PM UTC 24 |
34133693 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1732742270 |
|
|
Sep 24 12:45:24 PM UTC 24 |
Sep 24 12:45:29 PM UTC 24 |
92840105 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1102062450 |
|
|
Sep 24 12:45:25 PM UTC 24 |
Sep 24 12:45:29 PM UTC 24 |
225412868 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2242971908 |
|
|
Sep 24 12:45:28 PM UTC 24 |
Sep 24 12:45:31 PM UTC 24 |
33766262 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2738374717 |
|
|
Sep 24 12:45:28 PM UTC 24 |
Sep 24 12:45:32 PM UTC 24 |
110854083 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3604650503 |
|
|
Sep 24 12:45:28 PM UTC 24 |
Sep 24 12:45:32 PM UTC 24 |
65833280 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.366261966 |
|
|
Sep 24 12:45:30 PM UTC 24 |
Sep 24 12:45:32 PM UTC 24 |
38118465 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3027313711 |
|
|
Sep 24 12:45:29 PM UTC 24 |
Sep 24 12:45:32 PM UTC 24 |
43096026 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1380237005 |
|
|
Sep 24 12:45:30 PM UTC 24 |
Sep 24 12:45:33 PM UTC 24 |
183488466 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.731916520 |
|
|
Sep 24 12:45:29 PM UTC 24 |
Sep 24 12:45:33 PM UTC 24 |
21492286 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1573054224 |
|
|
Sep 24 12:45:31 PM UTC 24 |
Sep 24 12:45:33 PM UTC 24 |
18891763 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1628097851 |
|
|
Sep 24 12:45:31 PM UTC 24 |
Sep 24 12:45:34 PM UTC 24 |
60624238 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.251816615 |
|
|
Sep 24 12:45:22 PM UTC 24 |
Sep 24 12:45:34 PM UTC 24 |
372563961 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.167007322 |
|
|
Sep 24 12:45:32 PM UTC 24 |
Sep 24 12:45:35 PM UTC 24 |
50483048 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3844306291 |
|
|
Sep 24 12:45:32 PM UTC 24 |
Sep 24 12:45:36 PM UTC 24 |
319132866 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2192189699 |
|
|
Sep 24 12:45:29 PM UTC 24 |
Sep 24 12:45:36 PM UTC 24 |
288576549 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3666778607 |
|
|
Sep 24 12:45:32 PM UTC 24 |
Sep 24 12:45:37 PM UTC 24 |
535729343 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.707141786 |
|
|
Sep 24 12:45:34 PM UTC 24 |
Sep 24 12:45:37 PM UTC 24 |
102348978 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4062112833 |
|
|
Sep 24 12:45:33 PM UTC 24 |
Sep 24 12:45:37 PM UTC 24 |
139623260 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.401838317 |
|
|
Sep 24 12:45:29 PM UTC 24 |
Sep 24 12:45:37 PM UTC 24 |
416134490 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3855240882 |
|
|
Sep 24 12:45:35 PM UTC 24 |
Sep 24 12:45:37 PM UTC 24 |
19749373 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1436901108 |
|
|
Sep 24 12:45:29 PM UTC 24 |
Sep 24 12:45:37 PM UTC 24 |
240010448 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3963889802 |
|
|
Sep 24 12:45:35 PM UTC 24 |
Sep 24 12:45:38 PM UTC 24 |
62019911 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3429242422 |
|
|
Sep 24 12:45:35 PM UTC 24 |
Sep 24 12:45:38 PM UTC 24 |
26788514 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4101243166 |
|
|
Sep 24 12:45:36 PM UTC 24 |
Sep 24 12:45:39 PM UTC 24 |
22469475 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1714623991 |
|
|
Sep 24 12:45:34 PM UTC 24 |
Sep 24 12:45:39 PM UTC 24 |
137666365 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1107955995 |
|
|
Sep 24 12:45:36 PM UTC 24 |
Sep 24 12:45:39 PM UTC 24 |
112197144 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.581228429 |
|
|
Sep 24 12:45:34 PM UTC 24 |
Sep 24 12:45:39 PM UTC 24 |
200872508 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1485449099 |
|
|
Sep 24 12:45:36 PM UTC 24 |
Sep 24 12:45:39 PM UTC 24 |
84580801 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3211402291 |
|
|
Sep 24 12:45:35 PM UTC 24 |
Sep 24 12:45:39 PM UTC 24 |
124794814 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3142121689 |
|
|
Sep 24 12:45:36 PM UTC 24 |
Sep 24 12:45:40 PM UTC 24 |
69305964 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3789978938 |
|
|
Sep 24 12:45:28 PM UTC 24 |
Sep 24 12:45:40 PM UTC 24 |
441028245 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2483501709 |
|
|
Sep 24 12:45:38 PM UTC 24 |
Sep 24 12:45:40 PM UTC 24 |
410718936 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2242818046 |
|
|
Sep 24 12:45:38 PM UTC 24 |
Sep 24 12:45:40 PM UTC 24 |
65188871 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.312306435 |
|
|
Sep 24 12:45:38 PM UTC 24 |
Sep 24 12:45:41 PM UTC 24 |
39758749 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4105048907 |
|
|
Sep 24 12:45:39 PM UTC 24 |
Sep 24 12:45:41 PM UTC 24 |
21043424 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4055897302 |
|
|
Sep 24 12:45:39 PM UTC 24 |
Sep 24 12:45:41 PM UTC 24 |
48664425 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3726577401 |
|
|
Sep 24 12:45:40 PM UTC 24 |
Sep 24 12:45:43 PM UTC 24 |
80121528 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2724311992 |
|
|
Sep 24 12:45:33 PM UTC 24 |
Sep 24 12:45:43 PM UTC 24 |
2692146215 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.618479637 |
|
|
Sep 24 12:45:40 PM UTC 24 |
Sep 24 12:45:43 PM UTC 24 |
96199416 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1949554 |
|
|
Sep 24 12:45:40 PM UTC 24 |
Sep 24 12:45:43 PM UTC 24 |
72323693 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4211586350 |
|
|
Sep 24 12:45:40 PM UTC 24 |
Sep 24 12:45:43 PM UTC 24 |
58744237 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1346061977 |
|
|
Sep 24 12:45:41 PM UTC 24 |
Sep 24 12:45:43 PM UTC 24 |
38749514 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.165246618 |
|
|
Sep 24 12:45:38 PM UTC 24 |
Sep 24 12:45:43 PM UTC 24 |
296176379 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2045261776 |
|
|
Sep 24 12:45:38 PM UTC 24 |
Sep 24 12:45:43 PM UTC 24 |
1205600021 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.610097491 |
|
|
Sep 24 12:45:42 PM UTC 24 |
Sep 24 12:45:44 PM UTC 24 |
30877528 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1756281999 |
|
|
Sep 24 12:45:39 PM UTC 24 |
Sep 24 12:45:45 PM UTC 24 |
559074938 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2510634853 |
|
|
Sep 24 12:45:42 PM UTC 24 |
Sep 24 12:45:45 PM UTC 24 |
138967200 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4123703172 |
|
|
Sep 24 12:45:42 PM UTC 24 |
Sep 24 12:45:45 PM UTC 24 |
49539445 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1629679354 |
|
|
Sep 24 12:45:39 PM UTC 24 |
Sep 24 12:45:46 PM UTC 24 |
281977272 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3247860323 |
|
|
Sep 24 12:45:43 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
233886232 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.314441495 |
|
|
Sep 24 12:45:44 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
36521570 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3583630319 |
|
|
Sep 24 12:45:44 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
15739221 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.284340683 |
|
|
Sep 24 12:45:44 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
21876604 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1671224341 |
|
|
Sep 24 12:45:43 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
120264829 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.502195408 |
|
|
Sep 24 12:45:44 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
40499764 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1105594241 |
|
|
Sep 24 12:45:44 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
27028655 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.732871579 |
|
|
Sep 24 12:45:44 PM UTC 24 |
Sep 24 12:45:47 PM UTC 24 |
134765461 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.24063649 |
|
|
Sep 24 12:45:44 PM UTC 24 |
Sep 24 12:45:48 PM UTC 24 |
112587967 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.928637012 |
|
|
Sep 24 12:45:44 PM UTC 24 |
Sep 24 12:45:48 PM UTC 24 |
747183216 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.754648385 |
|
|
Sep 24 12:45:40 PM UTC 24 |
Sep 24 12:45:49 PM UTC 24 |
4900866387 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3919265696 |
|
|
Sep 24 12:45:46 PM UTC 24 |
Sep 24 12:45:49 PM UTC 24 |
17650088 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3044153858 |
|
|
Sep 24 12:45:21 PM UTC 24 |
Sep 24 12:45:50 PM UTC 24 |
1250141263 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1052705196 |
|
|
Sep 24 12:45:38 PM UTC 24 |
Sep 24 12:45:51 PM UTC 24 |
3054084249 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1076344674 |
|
|
Sep 24 12:45:48 PM UTC 24 |
Sep 24 12:45:51 PM UTC 24 |
23462384 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2976114483 |
|
|
Sep 24 12:45:48 PM UTC 24 |
Sep 24 12:45:51 PM UTC 24 |
17247337 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1681944818 |
|
|
Sep 24 12:45:49 PM UTC 24 |
Sep 24 12:45:51 PM UTC 24 |
76156501 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3435664426 |
|
|
Sep 24 12:45:47 PM UTC 24 |
Sep 24 12:45:52 PM UTC 24 |
288861303 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.490523345 |
|
|
Sep 24 12:46:03 PM UTC 24 |
Sep 24 12:46:08 PM UTC 24 |
310590445 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.235763376 |
|
|
Sep 24 12:45:49 PM UTC 24 |
Sep 24 12:45:52 PM UTC 24 |
82374432 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1364841086 |
|
|
Sep 24 12:45:49 PM UTC 24 |
Sep 24 12:45:52 PM UTC 24 |
73413719 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.329419003 |
|
|
Sep 24 12:45:48 PM UTC 24 |
Sep 24 12:45:53 PM UTC 24 |
400576339 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.423701359 |
|
|
Sep 24 12:45:49 PM UTC 24 |
Sep 24 12:45:53 PM UTC 24 |
133982271 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2567912347 |
|
|
Sep 24 12:45:50 PM UTC 24 |
Sep 24 12:45:53 PM UTC 24 |
38623864 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.100576113 |
|
|
Sep 24 12:45:49 PM UTC 24 |
Sep 24 12:45:54 PM UTC 24 |
102777888 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.276430257 |
|
|
Sep 24 12:45:51 PM UTC 24 |
Sep 24 12:45:54 PM UTC 24 |
40736943 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3444488600 |
|
|
Sep 24 12:45:47 PM UTC 24 |
Sep 24 12:45:54 PM UTC 24 |
181891243 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4280859408 |
|
|
Sep 24 12:45:50 PM UTC 24 |
Sep 24 12:45:55 PM UTC 24 |
88166021 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4130647601 |
|
|
Sep 24 12:45:52 PM UTC 24 |
Sep 24 12:45:55 PM UTC 24 |
35426414 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2829373282 |
|
|
Sep 24 12:46:05 PM UTC 24 |
Sep 24 12:46:08 PM UTC 24 |
611212355 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.489921073 |
|
|
Sep 24 12:45:46 PM UTC 24 |
Sep 24 12:45:55 PM UTC 24 |
1424736895 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1815957976 |
|
|
Sep 24 12:45:52 PM UTC 24 |
Sep 24 12:45:56 PM UTC 24 |
57138823 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.595185275 |
|
|
Sep 24 12:45:54 PM UTC 24 |
Sep 24 12:45:56 PM UTC 24 |
370035584 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3952261959 |
|
|
Sep 24 12:45:54 PM UTC 24 |
Sep 24 12:45:56 PM UTC 24 |
26637497 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3464727492 |
|
|
Sep 24 12:45:28 PM UTC 24 |
Sep 24 12:45:57 PM UTC 24 |
2330362592 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3505418616 |
|
|
Sep 24 12:45:51 PM UTC 24 |
Sep 24 12:45:57 PM UTC 24 |
443088363 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2400153711 |
|
|
Sep 24 12:45:48 PM UTC 24 |
Sep 24 12:45:57 PM UTC 24 |
1003911848 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.313648062 |
|
|
Sep 24 12:45:49 PM UTC 24 |
Sep 24 12:45:57 PM UTC 24 |
590993021 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3558212300 |
|
|
Sep 24 12:45:41 PM UTC 24 |
Sep 24 12:45:57 PM UTC 24 |
2182261190 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2002447441 |
|
|
Sep 24 12:45:56 PM UTC 24 |
Sep 24 12:45:58 PM UTC 24 |
34357283 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2153380820 |
|
|
Sep 24 12:45:55 PM UTC 24 |
Sep 24 12:45:58 PM UTC 24 |
220365690 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1290947420 |
|
|
Sep 24 12:45:56 PM UTC 24 |
Sep 24 12:45:58 PM UTC 24 |
80896671 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2266310260 |
|
|
Sep 24 12:45:56 PM UTC 24 |
Sep 24 12:45:58 PM UTC 24 |
40475321 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3513677109 |
|
|
Sep 24 12:45:52 PM UTC 24 |
Sep 24 12:45:58 PM UTC 24 |
890082768 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2809411982 |
|
|
Sep 24 12:45:56 PM UTC 24 |
Sep 24 12:45:59 PM UTC 24 |
59267602 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2848641560 |
|
|
Sep 24 12:45:55 PM UTC 24 |
Sep 24 12:45:59 PM UTC 24 |
238801807 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2371075195 |
|
|
Sep 24 12:45:42 PM UTC 24 |
Sep 24 12:45:59 PM UTC 24 |
661693429 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1866106676 |
|
|
Sep 24 12:45:57 PM UTC 24 |
Sep 24 12:45:59 PM UTC 24 |
112610224 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4025904838 |
|
|
Sep 24 12:45:46 PM UTC 24 |
Sep 24 12:45:59 PM UTC 24 |
1165185470 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3920701289 |
|
|
Sep 24 12:45:56 PM UTC 24 |
Sep 24 12:46:00 PM UTC 24 |
81756017 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.884557009 |
|
|
Sep 24 12:45:57 PM UTC 24 |
Sep 24 12:46:00 PM UTC 24 |
460784161 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.417857098 |
|
|
Sep 24 12:45:58 PM UTC 24 |
Sep 24 12:46:01 PM UTC 24 |
16208502 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.144043625 |
|
|
Sep 24 12:45:58 PM UTC 24 |
Sep 24 12:46:01 PM UTC 24 |
34801204 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.61826508 |
|
|
Sep 24 12:45:58 PM UTC 24 |
Sep 24 12:46:01 PM UTC 24 |
79158393 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.756642299 |
|
|
Sep 24 12:45:58 PM UTC 24 |
Sep 24 12:46:01 PM UTC 24 |
25217973 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3770388838 |
|
|
Sep 24 12:45:55 PM UTC 24 |
Sep 24 12:46:01 PM UTC 24 |
135200868 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1402405061 |
|
|
Sep 24 12:45:58 PM UTC 24 |
Sep 24 12:46:02 PM UTC 24 |
1367666072 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2285132196 |
|
|
Sep 24 12:45:59 PM UTC 24 |
Sep 24 12:46:02 PM UTC 24 |
153952088 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.839264381 |
|
|
Sep 24 12:45:58 PM UTC 24 |
Sep 24 12:46:02 PM UTC 24 |
66181971 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4199588315 |
|
|
Sep 24 12:46:03 PM UTC 24 |
Sep 24 12:46:07 PM UTC 24 |
244112141 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.940795119 |
|
|
Sep 24 12:46:05 PM UTC 24 |
Sep 24 12:46:07 PM UTC 24 |
162782349 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4004465066 |
|
|
Sep 24 12:45:57 PM UTC 24 |
Sep 24 12:46:02 PM UTC 24 |
554462857 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1141031007 |
|
|
Sep 24 12:45:57 PM UTC 24 |
Sep 24 12:46:02 PM UTC 24 |
628206829 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2049883987 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:02 PM UTC 24 |
42705972 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3694311035 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:03 PM UTC 24 |
52925472 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3880797126 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:03 PM UTC 24 |
160942121 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2633290712 |
|
|
Sep 24 12:46:08 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
13668856 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4265229452 |
|
|
Sep 24 12:45:54 PM UTC 24 |
Sep 24 12:46:03 PM UTC 24 |
2280370110 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.535019780 |
|
|
Sep 24 12:46:06 PM UTC 24 |
Sep 24 12:46:08 PM UTC 24 |
95164955 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.998317069 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:03 PM UTC 24 |
50865940 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2088992012 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:04 PM UTC 24 |
319059567 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3495336087 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:04 PM UTC 24 |
41384656 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3759959292 |
|
|
Sep 24 12:46:02 PM UTC 24 |
Sep 24 12:46:04 PM UTC 24 |
63277652 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2575649631 |
|
|
Sep 24 12:45:58 PM UTC 24 |
Sep 24 12:46:04 PM UTC 24 |
259149974 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2990326969 |
|
|
Sep 24 12:46:02 PM UTC 24 |
Sep 24 12:46:04 PM UTC 24 |
149720628 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4266142525 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:05 PM UTC 24 |
227045332 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2209359965 |
|
|
Sep 24 12:46:02 PM UTC 24 |
Sep 24 12:46:05 PM UTC 24 |
27571609 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1726306544 |
|
|
Sep 24 12:46:03 PM UTC 24 |
Sep 24 12:46:05 PM UTC 24 |
20307288 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3354786874 |
|
|
Sep 24 12:45:49 PM UTC 24 |
Sep 24 12:46:05 PM UTC 24 |
4982214647 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3284204747 |
|
|
Sep 24 12:46:03 PM UTC 24 |
Sep 24 12:46:06 PM UTC 24 |
18888748 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.463700811 |
|
|
Sep 24 12:46:03 PM UTC 24 |
Sep 24 12:46:06 PM UTC 24 |
100306828 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.374451449 |
|
|
Sep 24 12:46:02 PM UTC 24 |
Sep 24 12:46:06 PM UTC 24 |
70807158 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4089426306 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:06 PM UTC 24 |
983542999 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3689901950 |
|
|
Sep 24 12:46:03 PM UTC 24 |
Sep 24 12:46:06 PM UTC 24 |
58938901 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.364580281 |
|
|
Sep 24 12:46:03 PM UTC 24 |
Sep 24 12:46:07 PM UTC 24 |
51658418 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4007187314 |
|
|
Sep 24 12:46:05 PM UTC 24 |
Sep 24 12:46:07 PM UTC 24 |
46790350 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3846569753 |
|
|
Sep 24 12:46:05 PM UTC 24 |
Sep 24 12:46:07 PM UTC 24 |
102765463 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3880188981 |
|
|
Sep 24 12:46:05 PM UTC 24 |
Sep 24 12:46:07 PM UTC 24 |
26204432 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.475006165 |
|
|
Sep 24 12:46:05 PM UTC 24 |
Sep 24 12:46:07 PM UTC 24 |
109372875 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.390007628 |
|
|
Sep 24 12:46:02 PM UTC 24 |
Sep 24 12:46:07 PM UTC 24 |
607127011 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2398802520 |
|
|
Sep 24 12:46:05 PM UTC 24 |
Sep 24 12:46:08 PM UTC 24 |
61746593 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3017370074 |
|
|
Sep 24 12:45:33 PM UTC 24 |
Sep 24 12:46:09 PM UTC 24 |
12859556988 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1446357826 |
|
|
Sep 24 12:46:03 PM UTC 24 |
Sep 24 12:46:09 PM UTC 24 |
586089456 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.269781323 |
|
|
Sep 24 12:46:06 PM UTC 24 |
Sep 24 12:46:09 PM UTC 24 |
83863894 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4113218831 |
|
|
Sep 24 12:46:06 PM UTC 24 |
Sep 24 12:46:09 PM UTC 24 |
48360060 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3260930835 |
|
|
Sep 24 12:46:06 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
52750709 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2400401983 |
|
|
Sep 24 12:46:05 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
383533328 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3120351795 |
|
|
Sep 24 12:46:08 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
32374143 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3546549939 |
|
|
Sep 24 12:46:08 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
42661406 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2260826338 |
|
|
Sep 24 12:46:06 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
253174292 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4185338987 |
|
|
Sep 24 12:46:08 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
89705671 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.6178708 |
|
|
Sep 24 12:45:54 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
2621277207 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4024523432 |
|
|
Sep 24 12:46:08 PM UTC 24 |
Sep 24 12:46:10 PM UTC 24 |
56024504 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.79765360 |
|
|
Sep 24 12:46:08 PM UTC 24 |
Sep 24 12:46:11 PM UTC 24 |
64012575 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2043485118 |
|
|
Sep 24 12:46:08 PM UTC 24 |
Sep 24 12:46:11 PM UTC 24 |
46322234 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4212500662 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:11 PM UTC 24 |
14487667 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3106190147 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:12 PM UTC 24 |
14052118 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2618916227 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:12 PM UTC 24 |
22140278 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.299988055 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:12 PM UTC 24 |
20967816 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.218468532 |
|
|
Sep 24 12:46:06 PM UTC 24 |
Sep 24 12:46:12 PM UTC 24 |
459174649 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3604307021 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:12 PM UTC 24 |
56859956 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3401726402 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:12 PM UTC 24 |
134368965 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3114301825 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:13 PM UTC 24 |
425460878 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2723940035 |
|
|
Sep 24 12:46:11 PM UTC 24 |
Sep 24 12:46:13 PM UTC 24 |
49495800 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1577078418 |
|
|
Sep 24 12:46:11 PM UTC 24 |
Sep 24 12:46:14 PM UTC 24 |
20170169 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1749760651 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:14 PM UTC 24 |
75035537 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2032901741 |
|
|
Sep 24 12:46:11 PM UTC 24 |
Sep 24 12:46:14 PM UTC 24 |
17665753 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.665118737 |
|
|
Sep 24 12:46:09 PM UTC 24 |
Sep 24 12:46:14 PM UTC 24 |
1444540312 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2495755442 |
|
|
Sep 24 12:46:00 PM UTC 24 |
Sep 24 12:46:14 PM UTC 24 |
5072498926 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3611663261 |
|
|
Sep 24 12:46:11 PM UTC 24 |
Sep 24 12:46:14 PM UTC 24 |
73962937 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2883515759 |
|
|
Sep 24 12:46:08 PM UTC 24 |
Sep 24 12:46:15 PM UTC 24 |
169900378 ps |