| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3840496228 |
|
|
Oct 03 10:25:15 AM UTC 24 |
Oct 03 10:25:18 AM UTC 24 |
20525684 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.3598593334 |
|
|
Oct 03 10:25:07 AM UTC 24 |
Oct 03 10:25:18 AM UTC 24 |
189776283 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.1236234546 |
|
|
Oct 03 10:23:17 AM UTC 24 |
Oct 03 10:25:19 AM UTC 24 |
12121254254 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.3127183038 |
|
|
Oct 03 10:25:09 AM UTC 24 |
Oct 03 10:25:21 AM UTC 24 |
338148725 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.431663594 |
|
|
Oct 03 10:25:39 AM UTC 24 |
Oct 03 10:25:51 AM UTC 24 |
241486352 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.3641252049 |
|
|
Oct 03 10:25:15 AM UTC 24 |
Oct 03 10:25:22 AM UTC 24 |
93095533 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3953943333 |
|
|
Oct 03 10:25:17 AM UTC 24 |
Oct 03 10:25:22 AM UTC 24 |
213130046 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.1387370789 |
|
|
Oct 03 10:24:54 AM UTC 24 |
Oct 03 10:25:22 AM UTC 24 |
2518782308 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2024637200 |
|
|
Oct 03 10:25:11 AM UTC 24 |
Oct 03 10:25:22 AM UTC 24 |
354597795 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2686511365 |
|
|
Oct 03 10:24:01 AM UTC 24 |
Oct 03 10:25:22 AM UTC 24 |
2925023399 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.126368909 |
|
|
Oct 03 10:25:09 AM UTC 24 |
Oct 03 10:25:23 AM UTC 24 |
2883316202 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.1668811962 |
|
|
Oct 03 10:24:58 AM UTC 24 |
Oct 03 10:25:23 AM UTC 24 |
1593890081 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.2425462801 |
|
|
Oct 03 10:25:22 AM UTC 24 |
Oct 03 10:25:24 AM UTC 24 |
50922870 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2555891853 |
|
|
Oct 03 10:25:19 AM UTC 24 |
Oct 03 10:25:24 AM UTC 24 |
840157286 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1536003739 |
|
|
Oct 03 10:24:39 AM UTC 24 |
Oct 03 10:25:26 AM UTC 24 |
1242993518 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.176639623 |
|
|
Oct 03 10:25:23 AM UTC 24 |
Oct 03 10:25:26 AM UTC 24 |
28880421 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3540317884 |
|
|
Oct 03 10:23:48 AM UTC 24 |
Oct 03 10:25:27 AM UTC 24 |
2422289874 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3264345764 |
|
|
Oct 03 10:25:19 AM UTC 24 |
Oct 03 10:25:27 AM UTC 24 |
204950900 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.3363268530 |
|
|
Oct 03 10:25:23 AM UTC 24 |
Oct 03 10:25:28 AM UTC 24 |
490475310 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1971490769 |
|
|
Oct 03 10:25:11 AM UTC 24 |
Oct 03 10:25:29 AM UTC 24 |
1382721439 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.72312441 |
|
|
Oct 03 10:21:11 AM UTC 24 |
Oct 03 10:25:29 AM UTC 24 |
118342425836 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2529976711 |
|
|
Oct 03 10:25:24 AM UTC 24 |
Oct 03 10:25:29 AM UTC 24 |
194939491 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.3213649707 |
|
|
Oct 03 10:25:07 AM UTC 24 |
Oct 03 10:25:30 AM UTC 24 |
381801031 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2793483812 |
|
|
Oct 03 10:25:29 AM UTC 24 |
Oct 03 10:25:31 AM UTC 24 |
34217804 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.2475584192 |
|
|
Oct 03 10:25:17 AM UTC 24 |
Oct 03 10:25:32 AM UTC 24 |
1601141946 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.90092710 |
|
|
Oct 03 10:25:19 AM UTC 24 |
Oct 03 10:25:32 AM UTC 24 |
687721816 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.851756908 |
|
|
Oct 03 10:25:45 AM UTC 24 |
Oct 03 10:25:51 AM UTC 24 |
199289261 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.2628362306 |
|
|
Oct 03 10:25:29 AM UTC 24 |
Oct 03 10:25:32 AM UTC 24 |
119660004 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.1420295565 |
|
|
Oct 03 10:22:49 AM UTC 24 |
Oct 03 10:25:33 AM UTC 24 |
60428703761 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1606698006 |
|
|
Oct 03 10:25:30 AM UTC 24 |
Oct 03 10:25:33 AM UTC 24 |
21488676 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.3909691646 |
|
|
Oct 03 10:25:11 AM UTC 24 |
Oct 03 10:25:33 AM UTC 24 |
920839430 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.212436328 |
|
|
Oct 03 10:25:25 AM UTC 24 |
Oct 03 10:25:34 AM UTC 24 |
1385997542 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.4170316622 |
|
|
Oct 03 10:25:20 AM UTC 24 |
Oct 03 10:25:35 AM UTC 24 |
518860539 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3161573199 |
|
|
Oct 03 10:25:25 AM UTC 24 |
Oct 03 10:25:35 AM UTC 24 |
1271112846 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.4254564738 |
|
|
Oct 03 10:25:24 AM UTC 24 |
Oct 03 10:25:35 AM UTC 24 |
102385391 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.316763230 |
|
|
Oct 03 10:25:30 AM UTC 24 |
Oct 03 10:25:36 AM UTC 24 |
78214853 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3603441871 |
|
|
Oct 03 10:25:26 AM UTC 24 |
Oct 03 10:25:37 AM UTC 24 |
381916629 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3796950165 |
|
|
Oct 03 10:24:10 AM UTC 24 |
Oct 03 10:25:37 AM UTC 24 |
24156464039 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.3520470828 |
|
|
Oct 03 10:25:32 AM UTC 24 |
Oct 03 10:25:37 AM UTC 24 |
140126238 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2915004231 |
|
|
Oct 03 10:25:36 AM UTC 24 |
Oct 03 10:25:38 AM UTC 24 |
28746207 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.4217498619 |
|
|
Oct 03 10:25:17 AM UTC 24 |
Oct 03 10:25:39 AM UTC 24 |
5646266444 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.506083219 |
|
|
Oct 03 10:25:36 AM UTC 24 |
Oct 03 10:25:39 AM UTC 24 |
39520093 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2953184888 |
|
|
Oct 03 10:25:36 AM UTC 24 |
Oct 03 10:25:40 AM UTC 24 |
159731010 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2057323969 |
|
|
Oct 03 10:25:33 AM UTC 24 |
Oct 03 10:25:42 AM UTC 24 |
1166018703 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1915456930 |
|
|
Oct 03 10:25:24 AM UTC 24 |
Oct 03 10:25:42 AM UTC 24 |
5660970529 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.2885324056 |
|
|
Oct 03 10:25:35 AM UTC 24 |
Oct 03 10:25:43 AM UTC 24 |
925492755 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3413817966 |
|
|
Oct 03 10:25:25 AM UTC 24 |
Oct 03 10:25:43 AM UTC 24 |
958651091 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1220988400 |
|
|
Oct 03 10:25:39 AM UTC 24 |
Oct 03 10:25:44 AM UTC 24 |
581061997 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.1454349301 |
|
|
Oct 03 10:25:35 AM UTC 24 |
Oct 03 10:25:46 AM UTC 24 |
862763969 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.4284938934 |
|
|
Oct 03 10:25:25 AM UTC 24 |
Oct 03 10:25:46 AM UTC 24 |
1595571152 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.1880980829 |
|
|
Oct 03 10:25:33 AM UTC 24 |
Oct 03 10:25:46 AM UTC 24 |
2680803988 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.848541881 |
|
|
Oct 03 10:25:44 AM UTC 24 |
Oct 03 10:25:46 AM UTC 24 |
34354859 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.812802087 |
|
|
Oct 03 10:25:40 AM UTC 24 |
Oct 03 10:25:47 AM UTC 24 |
251423408 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.656632195 |
|
|
Oct 03 10:25:45 AM UTC 24 |
Oct 03 10:25:47 AM UTC 24 |
32227444 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.732457884 |
|
|
Oct 03 10:25:32 AM UTC 24 |
Oct 03 10:25:48 AM UTC 24 |
1600311943 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.115657041 |
|
|
Oct 03 10:25:12 AM UTC 24 |
Oct 03 10:25:48 AM UTC 24 |
5788579202 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.1699393224 |
|
|
Oct 03 10:25:15 AM UTC 24 |
Oct 03 10:25:50 AM UTC 24 |
246687061 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.3289405498 |
|
|
Oct 03 10:25:47 AM UTC 24 |
Oct 03 10:25:52 AM UTC 24 |
217193340 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.1853329564 |
|
|
Oct 03 10:25:52 AM UTC 24 |
Oct 03 10:25:54 AM UTC 24 |
26208260 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.2823533192 |
|
|
Oct 03 10:25:39 AM UTC 24 |
Oct 03 10:25:54 AM UTC 24 |
329195969 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3661923411 |
|
|
Oct 03 10:25:33 AM UTC 24 |
Oct 03 10:25:54 AM UTC 24 |
321807447 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2314273421 |
|
|
Oct 03 10:25:40 AM UTC 24 |
Oct 03 10:25:55 AM UTC 24 |
945987569 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.2704187963 |
|
|
Oct 03 10:25:47 AM UTC 24 |
Oct 03 10:25:55 AM UTC 24 |
1477392560 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.1209670519 |
|
|
Oct 03 10:25:39 AM UTC 24 |
Oct 03 10:25:55 AM UTC 24 |
368713861 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2586668373 |
|
|
Oct 03 10:24:21 AM UTC 24 |
Oct 03 10:25:55 AM UTC 24 |
7666656695 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.2004403383 |
|
|
Oct 03 10:25:40 AM UTC 24 |
Oct 03 10:25:56 AM UTC 24 |
1091003394 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.1063851276 |
|
|
Oct 03 10:25:47 AM UTC 24 |
Oct 03 10:25:57 AM UTC 24 |
1030558111 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.2463399263 |
|
|
Oct 03 10:25:47 AM UTC 24 |
Oct 03 10:25:57 AM UTC 24 |
67882444 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4112144402 |
|
|
Oct 03 10:25:55 AM UTC 24 |
Oct 03 10:25:58 AM UTC 24 |
17323777 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3371627471 |
|
|
Oct 03 10:25:53 AM UTC 24 |
Oct 03 10:25:58 AM UTC 24 |
715949830 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.2727734555 |
|
|
Oct 03 10:25:11 AM UTC 24 |
Oct 03 10:25:58 AM UTC 24 |
1904218267 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.1935810667 |
|
|
Oct 03 10:25:41 AM UTC 24 |
Oct 03 10:25:58 AM UTC 24 |
420036289 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.2594491791 |
|
|
Oct 03 10:26:20 AM UTC 24 |
Oct 03 10:26:35 AM UTC 24 |
358468598 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.745619910 |
|
|
Oct 03 10:26:26 AM UTC 24 |
Oct 03 10:26:37 AM UTC 24 |
183995335 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1988571319 |
|
|
Oct 03 10:25:23 AM UTC 24 |
Oct 03 10:26:00 AM UTC 24 |
3875574513 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.3745643129 |
|
|
Oct 03 10:25:55 AM UTC 24 |
Oct 03 10:26:00 AM UTC 24 |
97537377 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3366674864 |
|
|
Oct 03 10:25:05 AM UTC 24 |
Oct 03 10:26:01 AM UTC 24 |
1459011612 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.721058913 |
|
|
Oct 03 10:25:49 AM UTC 24 |
Oct 03 10:26:02 AM UTC 24 |
2658636655 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.3284911370 |
|
|
Oct 03 10:26:00 AM UTC 24 |
Oct 03 10:26:02 AM UTC 24 |
16438798 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2622648338 |
|
|
Oct 03 10:25:49 AM UTC 24 |
Oct 03 10:26:03 AM UTC 24 |
272850494 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3940067025 |
|
|
Oct 03 10:26:01 AM UTC 24 |
Oct 03 10:26:03 AM UTC 24 |
11310649 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.3183845882 |
|
|
Oct 03 10:25:55 AM UTC 24 |
Oct 03 10:26:04 AM UTC 24 |
117366887 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.563641149 |
|
|
Oct 03 10:26:00 AM UTC 24 |
Oct 03 10:26:04 AM UTC 24 |
108908716 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.4026018088 |
|
|
Oct 03 10:25:30 AM UTC 24 |
Oct 03 10:26:04 AM UTC 24 |
2109643966 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3340523285 |
|
|
Oct 03 10:26:02 AM UTC 24 |
Oct 03 10:26:07 AM UTC 24 |
461002127 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.602945509 |
|
|
Oct 03 10:25:44 AM UTC 24 |
Oct 03 10:26:07 AM UTC 24 |
1289921054 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.3292631439 |
|
|
Oct 03 10:25:48 AM UTC 24 |
Oct 03 10:26:08 AM UTC 24 |
2591615106 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3178612717 |
|
|
Oct 03 10:25:58 AM UTC 24 |
Oct 03 10:26:09 AM UTC 24 |
210554756 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.3377760226 |
|
|
Oct 03 10:25:48 AM UTC 24 |
Oct 03 10:26:09 AM UTC 24 |
428090746 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.715620542 |
|
|
Oct 03 10:25:57 AM UTC 24 |
Oct 03 10:26:10 AM UTC 24 |
262719501 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.230775868 |
|
|
Oct 03 10:25:58 AM UTC 24 |
Oct 03 10:26:10 AM UTC 24 |
1428140146 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1941902631 |
|
|
Oct 03 10:25:58 AM UTC 24 |
Oct 03 10:26:11 AM UTC 24 |
1206118878 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.3564314360 |
|
|
Oct 03 10:26:08 AM UTC 24 |
Oct 03 10:26:11 AM UTC 24 |
37862568 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3924258202 |
|
|
Oct 03 10:24:47 AM UTC 24 |
Oct 03 10:26:11 AM UTC 24 |
2391256333 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.1363342739 |
|
|
Oct 03 10:26:04 AM UTC 24 |
Oct 03 10:26:12 AM UTC 24 |
968121244 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.3713062930 |
|
|
Oct 03 10:25:37 AM UTC 24 |
Oct 03 10:26:12 AM UTC 24 |
593913479 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3518055376 |
|
|
Oct 03 10:26:10 AM UTC 24 |
Oct 03 10:26:12 AM UTC 24 |
43426399 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2160472080 |
|
|
Oct 03 10:26:10 AM UTC 24 |
Oct 03 10:26:13 AM UTC 24 |
126348268 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.2407426954 |
|
|
Oct 03 10:26:26 AM UTC 24 |
Oct 03 10:26:38 AM UTC 24 |
1192592946 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.1609650297 |
|
|
Oct 03 10:26:02 AM UTC 24 |
Oct 03 10:26:14 AM UTC 24 |
632182822 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.922087630 |
|
|
Oct 03 10:26:11 AM UTC 24 |
Oct 03 10:26:14 AM UTC 24 |
178527383 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.29810779 |
|
|
Oct 03 10:25:57 AM UTC 24 |
Oct 03 10:26:15 AM UTC 24 |
5636252653 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.1012123419 |
|
|
Oct 03 10:26:05 AM UTC 24 |
Oct 03 10:26:17 AM UTC 24 |
284906805 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.2322529125 |
|
|
Oct 03 10:26:02 AM UTC 24 |
Oct 03 10:26:17 AM UTC 24 |
1058114744 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1108035175 |
|
|
Oct 03 10:26:15 AM UTC 24 |
Oct 03 10:26:17 AM UTC 24 |
25123577 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.3708469072 |
|
|
Oct 03 10:25:45 AM UTC 24 |
Oct 03 10:26:18 AM UTC 24 |
231516251 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.660854845 |
|
|
Oct 03 10:26:16 AM UTC 24 |
Oct 03 10:26:19 AM UTC 24 |
53530582 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3911907418 |
|
|
Oct 03 10:26:21 AM UTC 24 |
Oct 03 10:26:41 AM UTC 24 |
718107159 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.952163196 |
|
|
Oct 03 10:26:05 AM UTC 24 |
Oct 03 10:26:19 AM UTC 24 |
356177751 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.1572315250 |
|
|
Oct 03 10:26:01 AM UTC 24 |
Oct 03 10:26:21 AM UTC 24 |
427548706 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.198171359 |
|
|
Oct 03 10:26:15 AM UTC 24 |
Oct 03 10:26:21 AM UTC 24 |
58752375 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.2655861391 |
|
|
Oct 03 10:26:04 AM UTC 24 |
Oct 03 10:26:21 AM UTC 24 |
327528354 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1331402169 |
|
|
Oct 03 10:26:11 AM UTC 24 |
Oct 03 10:26:23 AM UTC 24 |
227487119 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.411252790 |
|
|
Oct 03 10:26:11 AM UTC 24 |
Oct 03 10:26:23 AM UTC 24 |
235182466 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.291412805 |
|
|
Oct 03 10:26:13 AM UTC 24 |
Oct 03 10:26:23 AM UTC 24 |
166929737 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.549576632 |
|
|
Oct 03 10:26:13 AM UTC 24 |
Oct 03 10:26:24 AM UTC 24 |
1229831159 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2304811510 |
|
|
Oct 03 10:25:57 AM UTC 24 |
Oct 03 10:26:24 AM UTC 24 |
4384927947 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.3614430015 |
|
|
Oct 03 10:26:22 AM UTC 24 |
Oct 03 10:26:24 AM UTC 24 |
183205637 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3283619390 |
|
|
Oct 03 10:26:05 AM UTC 24 |
Oct 03 10:26:24 AM UTC 24 |
9939945452 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.3959699803 |
|
|
Oct 03 10:26:19 AM UTC 24 |
Oct 03 10:26:25 AM UTC 24 |
148444155 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.1890959260 |
|
|
Oct 03 10:26:18 AM UTC 24 |
Oct 03 10:26:25 AM UTC 24 |
144192856 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.3067404789 |
|
|
Oct 03 10:26:21 AM UTC 24 |
Oct 03 10:26:26 AM UTC 24 |
2329560719 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.2647457758 |
|
|
Oct 03 10:25:55 AM UTC 24 |
Oct 03 10:26:26 AM UTC 24 |
590670468 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.139842729 |
|
|
Oct 03 10:26:13 AM UTC 24 |
Oct 03 10:26:26 AM UTC 24 |
1525578421 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3050408761 |
|
|
Oct 03 10:26:24 AM UTC 24 |
Oct 03 10:26:27 AM UTC 24 |
34795775 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2740405692 |
|
|
Oct 03 10:26:11 AM UTC 24 |
Oct 03 10:26:27 AM UTC 24 |
303225781 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.1814519244 |
|
|
Oct 03 10:26:13 AM UTC 24 |
Oct 03 10:26:28 AM UTC 24 |
315493926 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.2084419885 |
|
|
Oct 03 10:26:26 AM UTC 24 |
Oct 03 10:26:29 AM UTC 24 |
110661802 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.4187580405 |
|
|
Oct 03 10:26:26 AM UTC 24 |
Oct 03 10:26:29 AM UTC 24 |
153368031 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.2643713246 |
|
|
Oct 03 10:26:24 AM UTC 24 |
Oct 03 10:26:30 AM UTC 24 |
69789744 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3118696894 |
|
|
Oct 03 10:26:29 AM UTC 24 |
Oct 03 10:26:32 AM UTC 24 |
45665727 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3509548566 |
|
|
Oct 03 10:26:30 AM UTC 24 |
Oct 03 10:26:32 AM UTC 24 |
65567049 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.3025283246 |
|
|
Oct 03 10:26:29 AM UTC 24 |
Oct 03 10:26:33 AM UTC 24 |
33416459 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.302426423 |
|
|
Oct 03 10:26:19 AM UTC 24 |
Oct 03 10:26:33 AM UTC 24 |
346165645 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.1280607909 |
|
|
Oct 03 10:26:21 AM UTC 24 |
Oct 03 10:26:33 AM UTC 24 |
181462238 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3907535978 |
|
|
Oct 03 10:26:32 AM UTC 24 |
Oct 03 10:26:37 AM UTC 24 |
130689532 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.3383466259 |
|
|
Oct 03 10:26:10 AM UTC 24 |
Oct 03 10:26:41 AM UTC 24 |
286556640 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.3330059991 |
|
|
Oct 03 10:26:27 AM UTC 24 |
Oct 03 10:26:41 AM UTC 24 |
1575889722 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.4070673967 |
|
|
Oct 03 10:26:26 AM UTC 24 |
Oct 03 10:26:42 AM UTC 24 |
1507249558 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3808942966 |
|
|
Oct 03 10:24:55 AM UTC 24 |
Oct 03 10:26:43 AM UTC 24 |
14235259842 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.1407040062 |
|
|
Oct 03 10:26:27 AM UTC 24 |
Oct 03 10:26:44 AM UTC 24 |
370665943 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3562775257 |
|
|
Oct 03 10:26:31 AM UTC 24 |
Oct 03 10:26:44 AM UTC 24 |
473878813 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1805168841 |
|
|
Oct 03 10:26:34 AM UTC 24 |
Oct 03 10:26:45 AM UTC 24 |
502231799 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.614396326 |
|
|
Oct 03 10:26:21 AM UTC 24 |
Oct 03 10:26:45 AM UTC 24 |
1279617910 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3348041052 |
|
|
Oct 03 10:26:43 AM UTC 24 |
Oct 03 10:26:45 AM UTC 24 |
11531379 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.763519971 |
|
|
Oct 03 10:26:43 AM UTC 24 |
Oct 03 10:26:45 AM UTC 24 |
64998904 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2588436923 |
|
|
Oct 03 10:26:33 AM UTC 24 |
Oct 03 10:26:45 AM UTC 24 |
426890190 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2295989118 |
|
|
Oct 03 10:26:43 AM UTC 24 |
Oct 03 10:26:45 AM UTC 24 |
44472524 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.3801841207 |
|
|
Oct 03 10:26:18 AM UTC 24 |
Oct 03 10:26:47 AM UTC 24 |
178025105 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1018785352 |
|
|
Oct 03 10:26:33 AM UTC 24 |
Oct 03 10:26:47 AM UTC 24 |
522179700 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3754901806 |
|
|
Oct 03 10:26:37 AM UTC 24 |
Oct 03 10:26:47 AM UTC 24 |
1338443825 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.847019186 |
|
|
Oct 03 10:26:33 AM UTC 24 |
Oct 03 10:26:47 AM UTC 24 |
2008848155 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2385715095 |
|
|
Oct 03 10:26:47 AM UTC 24 |
Oct 03 10:26:50 AM UTC 24 |
30316865 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.3294504967 |
|
|
Oct 03 10:26:44 AM UTC 24 |
Oct 03 10:26:50 AM UTC 24 |
308704691 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.2869043502 |
|
|
Oct 03 10:26:44 AM UTC 24 |
Oct 03 10:26:50 AM UTC 24 |
690101023 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.1680271496 |
|
|
Oct 03 10:26:27 AM UTC 24 |
Oct 03 10:26:50 AM UTC 24 |
638959038 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2779431400 |
|
|
Oct 03 10:26:49 AM UTC 24 |
Oct 03 10:26:51 AM UTC 24 |
12214035 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1577202634 |
|
|
Oct 03 10:26:47 AM UTC 24 |
Oct 03 10:26:53 AM UTC 24 |
110532760 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.938887366 |
|
|
Oct 03 10:26:46 AM UTC 24 |
Oct 03 10:26:54 AM UTC 24 |
244338702 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.3461193084 |
|
|
Oct 03 10:26:46 AM UTC 24 |
Oct 03 10:26:55 AM UTC 24 |
1531082869 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2829755077 |
|
|
Oct 03 10:26:51 AM UTC 24 |
Oct 03 10:26:56 AM UTC 24 |
62476396 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2344698433 |
|
|
Oct 03 10:26:51 AM UTC 24 |
Oct 03 10:26:56 AM UTC 24 |
67634787 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.182336009 |
|
|
Oct 03 10:25:58 AM UTC 24 |
Oct 03 10:26:57 AM UTC 24 |
5810163787 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.4057295691 |
|
|
Oct 03 10:26:24 AM UTC 24 |
Oct 03 10:26:58 AM UTC 24 |
5858713205 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.890131109 |
|
|
Oct 03 10:26:46 AM UTC 24 |
Oct 03 10:26:58 AM UTC 24 |
756355473 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3375109591 |
|
|
Oct 03 10:26:38 AM UTC 24 |
Oct 03 10:26:58 AM UTC 24 |
2071722449 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2856685261 |
|
|
Oct 03 10:26:46 AM UTC 24 |
Oct 03 10:26:59 AM UTC 24 |
706961103 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2028456867 |
|
|
Oct 03 10:26:57 AM UTC 24 |
Oct 03 10:26:59 AM UTC 24 |
31604443 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1982101400 |
|
|
Oct 03 10:26:51 AM UTC 24 |
Oct 03 10:27:00 AM UTC 24 |
1535142327 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.268321849 |
|
|
Oct 03 10:26:58 AM UTC 24 |
Oct 03 10:27:01 AM UTC 24 |
18064450 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.4220848913 |
|
|
Oct 03 10:26:30 AM UTC 24 |
Oct 03 10:27:02 AM UTC 24 |
824701744 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1789379020 |
|
|
Oct 03 10:26:58 AM UTC 24 |
Oct 03 10:27:02 AM UTC 24 |
182588255 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.3172379374 |
|
|
Oct 03 10:26:43 AM UTC 24 |
Oct 03 10:27:03 AM UTC 24 |
1179227424 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.2168311018 |
|
|
Oct 03 10:27:00 AM UTC 24 |
Oct 03 10:27:03 AM UTC 24 |
106921845 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.1248731554 |
|
|
Oct 03 10:26:52 AM UTC 24 |
Oct 03 10:27:04 AM UTC 24 |
460887498 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.2732088643 |
|
|
Oct 03 10:26:46 AM UTC 24 |
Oct 03 10:27:05 AM UTC 24 |
1210892291 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.337747033 |
|
|
Oct 03 10:26:52 AM UTC 24 |
Oct 03 10:27:06 AM UTC 24 |
208081639 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.1070941 |
|
|
Oct 03 10:26:54 AM UTC 24 |
Oct 03 10:27:06 AM UTC 24 |
1616911380 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.4130348738 |
|
|
Oct 03 10:26:51 AM UTC 24 |
Oct 03 10:27:06 AM UTC 24 |
338180658 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.3393267005 |
|
|
Oct 03 10:26:44 AM UTC 24 |
Oct 03 10:27:07 AM UTC 24 |
1077122688 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.2657564650 |
|
|
Oct 03 10:27:05 AM UTC 24 |
Oct 03 10:27:08 AM UTC 24 |
72803640 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1970147304 |
|
|
Oct 03 10:24:29 AM UTC 24 |
Oct 03 10:27:09 AM UTC 24 |
12784211252 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2070826023 |
|
|
Oct 03 10:27:07 AM UTC 24 |
Oct 03 10:27:10 AM UTC 24 |
38867561 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.2659201506 |
|
|
Oct 03 10:27:06 AM UTC 24 |
Oct 03 10:27:11 AM UTC 24 |
64238934 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.671215164 |
|
|
Oct 03 10:27:00 AM UTC 24 |
Oct 03 10:27:12 AM UTC 24 |
124460582 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.1179391572 |
|
|
Oct 03 10:26:55 AM UTC 24 |
Oct 03 10:27:12 AM UTC 24 |
359731429 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.3012780229 |
|
|
Oct 03 10:27:01 AM UTC 24 |
Oct 03 10:27:13 AM UTC 24 |
1013291305 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.541173147 |
|
|
Oct 03 10:27:09 AM UTC 24 |
Oct 03 10:27:14 AM UTC 24 |
87495698 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.1436284716 |
|
|
Oct 03 10:25:35 AM UTC 24 |
Oct 03 10:27:15 AM UTC 24 |
3592822068 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2580266627 |
|
|
Oct 03 10:27:07 AM UTC 24 |
Oct 03 10:27:15 AM UTC 24 |
351797252 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.997642276 |
|
|
Oct 03 10:27:00 AM UTC 24 |
Oct 03 10:27:16 AM UTC 24 |
274747580 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.2872958558 |
|
|
Oct 03 10:27:01 AM UTC 24 |
Oct 03 10:27:16 AM UTC 24 |
3131055099 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3621617034 |
|
|
Oct 03 10:26:22 AM UTC 24 |
Oct 03 10:27:17 AM UTC 24 |
7752841922 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.1248914126 |
|
|
Oct 03 10:27:04 AM UTC 24 |
Oct 03 10:27:17 AM UTC 24 |
1231646393 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3390865564 |
|
|
Oct 03 10:27:16 AM UTC 24 |
Oct 03 10:27:19 AM UTC 24 |
13872419 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.2271651516 |
|
|
Oct 03 10:27:16 AM UTC 24 |
Oct 03 10:27:19 AM UTC 24 |
18322100 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.2566906335 |
|
|
Oct 03 10:26:49 AM UTC 24 |
Oct 03 10:27:19 AM UTC 24 |
384453949 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.2432680257 |
|
|
Oct 03 10:27:04 AM UTC 24 |
Oct 03 10:27:19 AM UTC 24 |
1808686365 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.219103445 |
|
|
Oct 03 10:27:12 AM UTC 24 |
Oct 03 10:27:20 AM UTC 24 |
933571969 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1044039262 |
|
|
Oct 03 10:25:28 AM UTC 24 |
Oct 03 10:27:21 AM UTC 24 |
2765941047 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.635202835 |
|
|
Oct 03 10:24:38 AM UTC 24 |
Oct 03 10:27:21 AM UTC 24 |
7980727736 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.4225172887 |
|
|
Oct 03 10:27:25 AM UTC 24 |
Oct 03 10:27:30 AM UTC 24 |
658154549 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.3962140022 |
|
|
Oct 03 10:26:14 AM UTC 24 |
Oct 03 10:27:22 AM UTC 24 |
4569321025 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.2944617832 |
|
|
Oct 03 10:27:18 AM UTC 24 |
Oct 03 10:27:22 AM UTC 24 |
28967274 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.644672535 |
|
|
Oct 03 10:24:47 AM UTC 24 |
Oct 03 10:27:31 AM UTC 24 |
41220715039 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.2590391185 |
|
|
Oct 03 10:27:16 AM UTC 24 |
Oct 03 10:27:22 AM UTC 24 |
99621590 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.2231743023 |
|
|
Oct 03 10:27:09 AM UTC 24 |
Oct 03 10:27:23 AM UTC 24 |
373040382 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3895757495 |
|
|
Oct 03 10:27:10 AM UTC 24 |
Oct 03 10:27:23 AM UTC 24 |
1080902415 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.576961298 |
|
|
Oct 03 10:27:02 AM UTC 24 |
Oct 03 10:27:24 AM UTC 24 |
1434697944 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.4174191560 |
|
|
Oct 03 10:27:18 AM UTC 24 |
Oct 03 10:27:25 AM UTC 24 |
51889933 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.2647434785 |
|
|
Oct 03 10:27:13 AM UTC 24 |
Oct 03 10:27:25 AM UTC 24 |
246766804 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.895807978 |
|
|
Oct 03 10:26:58 AM UTC 24 |
Oct 03 10:27:26 AM UTC 24 |
1106003322 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.3989693236 |
|
|
Oct 03 10:27:12 AM UTC 24 |
Oct 03 10:27:26 AM UTC 24 |
2463922843 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.2118201205 |
|
|
Oct 03 10:27:20 AM UTC 24 |
Oct 03 10:27:26 AM UTC 24 |
3159346832 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2400393612 |
|
|
Oct 03 10:27:25 AM UTC 24 |
Oct 03 10:27:27 AM UTC 24 |
28889525 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.4071040750 |
|
|
Oct 03 10:27:24 AM UTC 24 |
Oct 03 10:27:27 AM UTC 24 |
17387895 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.4177052716 |
|
|
Oct 03 10:27:24 AM UTC 24 |
Oct 03 10:27:28 AM UTC 24 |
35900891 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2386579463 |
|
|
Oct 03 10:27:20 AM UTC 24 |
Oct 03 10:27:31 AM UTC 24 |
621119974 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3193788427 |
|
|
Oct 03 10:27:25 AM UTC 24 |
Oct 03 10:27:31 AM UTC 24 |
304645587 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1012377434 |
|
|
Oct 03 10:27:26 AM UTC 24 |
Oct 03 10:27:31 AM UTC 24 |
92046371 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.2028250889 |
|
|
Oct 03 10:27:29 AM UTC 24 |
Oct 03 10:27:31 AM UTC 24 |
41899974 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.3161689438 |
|
|
Oct 03 10:27:13 AM UTC 24 |
Oct 03 10:27:32 AM UTC 24 |
381302063 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1267999170 |
|
|
Oct 03 10:26:27 AM UTC 24 |
Oct 03 10:27:32 AM UTC 24 |
3331471957 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.3677954657 |
|
|
Oct 03 10:26:46 AM UTC 24 |
Oct 03 10:27:32 AM UTC 24 |
2158812857 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.3302723800 |
|
|
Oct 03 10:27:07 AM UTC 24 |
Oct 03 10:27:33 AM UTC 24 |
716143113 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3987775986 |
|
|
Oct 03 10:21:29 AM UTC 24 |
Oct 03 10:27:35 AM UTC 24 |
13102029877 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3447093407 |
|
|
Oct 03 10:27:32 AM UTC 24 |
Oct 03 10:27:35 AM UTC 24 |
10601061 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.2675347142 |
|
|
Oct 03 10:27:18 AM UTC 24 |
Oct 03 10:27:36 AM UTC 24 |
634724383 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2590427445 |
|
|
Oct 03 10:27:23 AM UTC 24 |
Oct 03 10:27:36 AM UTC 24 |
411841138 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.74342380 |
|
|
Oct 03 10:27:32 AM UTC 24 |
Oct 03 10:27:36 AM UTC 24 |
17971189 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1466250484 |
|
|
Oct 03 10:27:20 AM UTC 24 |
Oct 03 10:27:36 AM UTC 24 |
7983338577 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.509779098 |
|
|
Oct 03 10:27:21 AM UTC 24 |
Oct 03 10:27:37 AM UTC 24 |
325308209 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2985121257 |
|
|
Oct 03 10:27:25 AM UTC 24 |
Oct 03 10:27:37 AM UTC 24 |
412581893 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.3334642261 |
|
|
Oct 03 10:27:21 AM UTC 24 |
Oct 03 10:27:37 AM UTC 24 |
772410538 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1818554921 |
|
|
Oct 03 10:27:34 AM UTC 24 |
Oct 03 10:27:38 AM UTC 24 |
435605720 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.3931921930 |
|
|
Oct 03 10:27:32 AM UTC 24 |
Oct 03 10:27:38 AM UTC 24 |
277526572 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.317844905 |
|
|
Oct 03 10:27:31 AM UTC 24 |
Oct 03 10:27:39 AM UTC 24 |
406368004 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.2159626914 |
|
|
Oct 03 10:27:27 AM UTC 24 |
Oct 03 10:27:39 AM UTC 24 |
1814713153 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.2045136202 |
|
|
Oct 03 10:27:27 AM UTC 24 |
Oct 03 10:27:40 AM UTC 24 |
1763024725 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4180640483 |
|
|
Oct 03 10:27:37 AM UTC 24 |
Oct 03 10:27:40 AM UTC 24 |
11186573 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1494721080 |
|
|
Oct 03 10:27:37 AM UTC 24 |
Oct 03 10:27:40 AM UTC 24 |
117923947 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2363301320 |
|
|
Oct 03 10:27:37 AM UTC 24 |
Oct 03 10:27:40 AM UTC 24 |
284963683 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.572740311 |
|
|
Oct 03 10:27:26 AM UTC 24 |
Oct 03 10:27:41 AM UTC 24 |
826238087 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.1273996806 |
|
|
Oct 03 10:27:27 AM UTC 24 |
Oct 03 10:27:41 AM UTC 24 |
287212315 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.647926592 |
|
|
Oct 03 10:26:47 AM UTC 24 |
Oct 03 10:27:43 AM UTC 24 |
5807726535 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3289535399 |
|
|
Oct 03 10:27:41 AM UTC 24 |
Oct 03 10:27:43 AM UTC 24 |
83895170 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.3757551630 |
|
|
Oct 03 10:27:41 AM UTC 24 |
Oct 03 10:27:44 AM UTC 24 |
24805172 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.3870466736 |
|
|
Oct 03 10:27:39 AM UTC 24 |
Oct 03 10:27:44 AM UTC 24 |
77775434 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1434339000 |
|
|
Oct 03 10:27:42 AM UTC 24 |
Oct 03 10:27:44 AM UTC 24 |
21419890 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.1540324284 |
|
|
Oct 03 10:27:32 AM UTC 24 |
Oct 03 10:27:45 AM UTC 24 |
268796031 ps |