| T816 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.1023098806 |
|
|
Oct 03 10:27:39 AM UTC 24 |
Oct 03 10:27:46 AM UTC 24 |
129427839 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.3992291645 |
|
|
Oct 03 10:27:39 AM UTC 24 |
Oct 03 10:27:47 AM UTC 24 |
229288577 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2750383975 |
|
|
Oct 03 10:27:39 AM UTC 24 |
Oct 03 10:27:48 AM UTC 24 |
143148789 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.2576080083 |
|
|
Oct 03 10:27:34 AM UTC 24 |
Oct 03 10:27:48 AM UTC 24 |
571549021 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2965106664 |
|
|
Oct 03 10:27:32 AM UTC 24 |
Oct 03 10:27:49 AM UTC 24 |
562529472 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.3700890529 |
|
|
Oct 03 10:27:45 AM UTC 24 |
Oct 03 10:27:50 AM UTC 24 |
309380777 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3528648000 |
|
|
Oct 03 10:27:34 AM UTC 24 |
Oct 03 10:27:50 AM UTC 24 |
841380537 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.881572860 |
|
|
Oct 03 10:26:57 AM UTC 24 |
Oct 03 10:27:53 AM UTC 24 |
14540258697 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.670202832 |
|
|
Oct 03 10:27:51 AM UTC 24 |
Oct 03 10:27:53 AM UTC 24 |
16860077 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1809995791 |
|
|
Oct 03 10:27:25 AM UTC 24 |
Oct 03 10:27:53 AM UTC 24 |
245037088 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.178194573 |
|
|
Oct 03 10:27:51 AM UTC 24 |
Oct 03 10:27:53 AM UTC 24 |
13273717 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.3415085348 |
|
|
Oct 03 10:25:04 AM UTC 24 |
Oct 03 10:27:54 AM UTC 24 |
11050203313 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.466356949 |
|
|
Oct 03 10:27:39 AM UTC 24 |
Oct 03 10:27:54 AM UTC 24 |
571195178 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1622219438 |
|
|
Oct 03 10:27:32 AM UTC 24 |
Oct 03 10:27:55 AM UTC 24 |
376359000 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.2530100421 |
|
|
Oct 03 10:27:51 AM UTC 24 |
Oct 03 10:27:55 AM UTC 24 |
197646610 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.630552941 |
|
|
Oct 03 10:25:50 AM UTC 24 |
Oct 03 10:27:55 AM UTC 24 |
5250141781 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1640068447 |
|
|
Oct 03 10:27:41 AM UTC 24 |
Oct 03 10:27:55 AM UTC 24 |
307514412 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.3935373815 |
|
|
Oct 03 10:27:34 AM UTC 24 |
Oct 03 10:27:56 AM UTC 24 |
772796439 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2582564233 |
|
|
Oct 03 10:27:28 AM UTC 24 |
Oct 03 10:27:57 AM UTC 24 |
6065421346 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.2201899255 |
|
|
Oct 03 10:27:43 AM UTC 24 |
Oct 03 10:27:57 AM UTC 24 |
295658802 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.305729566 |
|
|
Oct 03 10:27:45 AM UTC 24 |
Oct 03 10:27:57 AM UTC 24 |
391327798 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.2911233308 |
|
|
Oct 03 10:27:39 AM UTC 24 |
Oct 03 10:27:58 AM UTC 24 |
493403807 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.242357064 |
|
|
Oct 03 10:27:57 AM UTC 24 |
Oct 03 10:27:59 AM UTC 24 |
32638413 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.1627651736 |
|
|
Oct 03 10:27:55 AM UTC 24 |
Oct 03 10:27:59 AM UTC 24 |
1538701549 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.3348028979 |
|
|
Oct 03 10:27:47 AM UTC 24 |
Oct 03 10:28:00 AM UTC 24 |
492519508 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.2966280178 |
|
|
Oct 03 10:27:55 AM UTC 24 |
Oct 03 10:28:00 AM UTC 24 |
72149813 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2811996877 |
|
|
Oct 03 10:27:57 AM UTC 24 |
Oct 03 10:28:00 AM UTC 24 |
38754463 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.1770671400 |
|
|
Oct 03 10:27:46 AM UTC 24 |
Oct 03 10:28:00 AM UTC 24 |
371572785 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1610576781 |
|
|
Oct 03 10:27:58 AM UTC 24 |
Oct 03 10:28:00 AM UTC 24 |
27320779 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2277465982 |
|
|
Oct 03 10:27:47 AM UTC 24 |
Oct 03 10:28:00 AM UTC 24 |
1906000211 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.3179338098 |
|
|
Oct 03 10:27:55 AM UTC 24 |
Oct 03 10:28:01 AM UTC 24 |
54088508 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1840039827 |
|
|
Oct 03 10:27:46 AM UTC 24 |
Oct 03 10:28:01 AM UTC 24 |
3901797477 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.4194647525 |
|
|
Oct 03 10:27:37 AM UTC 24 |
Oct 03 10:28:01 AM UTC 24 |
208121134 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.2974934576 |
|
|
Oct 03 10:27:59 AM UTC 24 |
Oct 03 10:28:03 AM UTC 24 |
199408458 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3944043774 |
|
|
Oct 03 10:27:55 AM UTC 24 |
Oct 03 10:28:04 AM UTC 24 |
431641352 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.2283480264 |
|
|
Oct 03 10:27:41 AM UTC 24 |
Oct 03 10:28:05 AM UTC 24 |
1194016148 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.44343308 |
|
|
Oct 03 10:27:45 AM UTC 24 |
Oct 03 10:28:05 AM UTC 24 |
425675669 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.1529063552 |
|
|
Oct 03 10:28:02 AM UTC 24 |
Oct 03 10:28:05 AM UTC 24 |
20012703 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3995562006 |
|
|
Oct 03 10:27:55 AM UTC 24 |
Oct 03 10:28:06 AM UTC 24 |
1015132232 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1958458867 |
|
|
Oct 03 10:27:56 AM UTC 24 |
Oct 03 10:28:07 AM UTC 24 |
4196065101 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3993378639 |
|
|
Oct 03 10:27:42 AM UTC 24 |
Oct 03 10:28:07 AM UTC 24 |
908629746 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2450402388 |
|
|
Oct 03 10:25:35 AM UTC 24 |
Oct 03 10:28:08 AM UTC 24 |
38435479220 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.416598527 |
|
|
Oct 03 10:27:58 AM UTC 24 |
Oct 03 10:28:10 AM UTC 24 |
95352849 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.861752067 |
|
|
Oct 03 10:27:14 AM UTC 24 |
Oct 03 10:28:12 AM UTC 24 |
11984154260 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.3117100225 |
|
|
Oct 03 10:27:55 AM UTC 24 |
Oct 03 10:28:12 AM UTC 24 |
399414964 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1606893962 |
|
|
Oct 03 10:27:59 AM UTC 24 |
Oct 03 10:28:13 AM UTC 24 |
1339226682 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.4156328606 |
|
|
Oct 03 10:28:02 AM UTC 24 |
Oct 03 10:28:13 AM UTC 24 |
297392261 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3778991399 |
|
|
Oct 03 10:27:41 AM UTC 24 |
Oct 03 10:28:14 AM UTC 24 |
3496107020 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.4294908639 |
|
|
Oct 03 10:28:01 AM UTC 24 |
Oct 03 10:28:14 AM UTC 24 |
4522045046 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.896894442 |
|
|
Oct 03 10:27:52 AM UTC 24 |
Oct 03 10:28:15 AM UTC 24 |
236271879 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1300921533 |
|
|
Oct 03 10:28:01 AM UTC 24 |
Oct 03 10:28:17 AM UTC 24 |
442561511 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1341710583 |
|
|
Oct 03 10:27:56 AM UTC 24 |
Oct 03 10:28:17 AM UTC 24 |
6278224684 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.3355857784 |
|
|
Oct 03 10:28:02 AM UTC 24 |
Oct 03 10:28:18 AM UTC 24 |
3704850100 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1012518307 |
|
|
Oct 03 10:28:01 AM UTC 24 |
Oct 03 10:28:18 AM UTC 24 |
356817323 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.573865608 |
|
|
Oct 03 10:27:58 AM UTC 24 |
Oct 03 10:28:20 AM UTC 24 |
923136182 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.328150566 |
|
|
Oct 03 10:25:21 AM UTC 24 |
Oct 03 10:28:24 AM UTC 24 |
45016010378 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3067658836 |
|
|
Oct 03 10:27:35 AM UTC 24 |
Oct 03 10:28:25 AM UTC 24 |
5694729222 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.3842070367 |
|
|
Oct 03 10:26:38 AM UTC 24 |
Oct 03 10:28:27 AM UTC 24 |
6669065297 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2090687206 |
|
|
Oct 03 10:26:56 AM UTC 24 |
Oct 03 10:28:30 AM UTC 24 |
3533362903 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.3741098952 |
|
|
Oct 03 10:26:08 AM UTC 24 |
Oct 03 10:28:36 AM UTC 24 |
13087263737 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.244793819 |
|
|
Oct 03 10:27:49 AM UTC 24 |
Oct 03 10:28:39 AM UTC 24 |
5183992906 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1879633793 |
|
|
Oct 03 10:27:57 AM UTC 24 |
Oct 03 10:28:47 AM UTC 24 |
1768538784 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.487334795 |
|
|
Oct 03 10:26:39 AM UTC 24 |
Oct 03 10:28:49 AM UTC 24 |
4114145181 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.4203635626 |
|
|
Oct 03 10:27:23 AM UTC 24 |
Oct 03 10:28:51 AM UTC 24 |
5323093281 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.1566108587 |
|
|
Oct 03 10:27:37 AM UTC 24 |
Oct 03 10:29:16 AM UTC 24 |
2226479563 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1467205027 |
|
|
Oct 03 10:26:27 AM UTC 24 |
Oct 03 10:29:27 AM UTC 24 |
5040537271 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.1075430033 |
|
|
Oct 03 10:25:26 AM UTC 24 |
Oct 03 10:29:34 AM UTC 24 |
24838283365 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1859854440 |
|
|
Oct 03 10:27:04 AM UTC 24 |
Oct 03 10:29:59 AM UTC 24 |
10368380532 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.1276434158 |
|
|
Oct 03 10:27:41 AM UTC 24 |
Oct 03 10:30:15 AM UTC 24 |
12799332620 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.1436551891 |
|
|
Oct 03 10:27:57 AM UTC 24 |
Oct 03 10:30:24 AM UTC 24 |
5026070513 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3139848593 |
|
|
Oct 03 10:27:23 AM UTC 24 |
Oct 03 10:30:34 AM UTC 24 |
8374295283 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2191842376 |
|
|
Oct 03 10:28:02 AM UTC 24 |
Oct 03 10:30:48 AM UTC 24 |
9283742081 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.532016846 |
|
|
Oct 03 10:27:27 AM UTC 24 |
Oct 03 10:31:22 AM UTC 24 |
6376454027 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3640353980 |
|
|
Oct 03 10:25:58 AM UTC 24 |
Oct 03 10:31:39 AM UTC 24 |
9693832521 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.9620145 |
|
|
Oct 03 10:24:28 AM UTC 24 |
Oct 03 10:32:02 AM UTC 24 |
27953135992 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.3353823550 |
|
|
Oct 03 10:25:44 AM UTC 24 |
Oct 03 10:35:10 AM UTC 24 |
28463315597 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4022149676 |
|
|
Oct 03 10:28:02 AM UTC 24 |
Oct 03 10:28:06 AM UTC 24 |
770852946 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3537952359 |
|
|
Oct 03 10:28:03 AM UTC 24 |
Oct 03 10:28:07 AM UTC 24 |
378811722 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2412671920 |
|
|
Oct 03 10:28:06 AM UTC 24 |
Oct 03 10:28:09 AM UTC 24 |
113859715 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3896297706 |
|
|
Oct 03 10:28:06 AM UTC 24 |
Oct 03 10:28:09 AM UTC 24 |
344860453 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.527113250 |
|
|
Oct 03 10:28:08 AM UTC 24 |
Oct 03 10:28:10 AM UTC 24 |
15608905 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1388611810 |
|
|
Oct 03 10:28:08 AM UTC 24 |
Oct 03 10:28:10 AM UTC 24 |
40556108 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1965728115 |
|
|
Oct 03 10:28:06 AM UTC 24 |
Oct 03 10:28:10 AM UTC 24 |
75558167 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3904316600 |
|
|
Oct 03 10:28:07 AM UTC 24 |
Oct 03 10:28:11 AM UTC 24 |
40369729 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.865265843 |
|
|
Oct 03 10:28:09 AM UTC 24 |
Oct 03 10:28:12 AM UTC 24 |
107789581 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2324551812 |
|
|
Oct 03 10:28:10 AM UTC 24 |
Oct 03 10:28:13 AM UTC 24 |
18446548 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1528364772 |
|
|
Oct 03 10:28:10 AM UTC 24 |
Oct 03 10:28:13 AM UTC 24 |
37196956 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.11805597 |
|
|
Oct 03 10:28:10 AM UTC 24 |
Oct 03 10:28:13 AM UTC 24 |
326749625 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3195548673 |
|
|
Oct 03 10:28:10 AM UTC 24 |
Oct 03 10:28:13 AM UTC 24 |
61218854 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2433437540 |
|
|
Oct 03 10:28:10 AM UTC 24 |
Oct 03 10:28:14 AM UTC 24 |
28017739 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1168783191 |
|
|
Oct 03 10:28:07 AM UTC 24 |
Oct 03 10:28:14 AM UTC 24 |
77443328 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.55267115 |
|
|
Oct 03 10:28:12 AM UTC 24 |
Oct 03 10:28:14 AM UTC 24 |
17040976 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.985276765 |
|
|
Oct 03 10:28:06 AM UTC 24 |
Oct 03 10:28:15 AM UTC 24 |
1671657131 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4113023195 |
|
|
Oct 03 10:28:13 AM UTC 24 |
Oct 03 10:28:16 AM UTC 24 |
51060045 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.143559285 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:17 AM UTC 24 |
61110458 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4028265093 |
|
|
Oct 03 10:28:13 AM UTC 24 |
Oct 03 10:28:17 AM UTC 24 |
340770747 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.291535082 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:17 AM UTC 24 |
18106803 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1899054724 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:17 AM UTC 24 |
45712450 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2513950406 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:18 AM UTC 24 |
295077566 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2833037973 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:18 AM UTC 24 |
32798091 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1716539822 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:18 AM UTC 24 |
19475952 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1304520053 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:18 AM UTC 24 |
31941026 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3088732297 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:18 AM UTC 24 |
15602902 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2345309948 |
|
|
Oct 03 10:28:13 AM UTC 24 |
Oct 03 10:28:18 AM UTC 24 |
106781386 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.926899026 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:19 AM UTC 24 |
311113821 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1366898598 |
|
|
Oct 03 10:28:16 AM UTC 24 |
Oct 03 10:28:19 AM UTC 24 |
159645042 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.964273961 |
|
|
Oct 03 10:28:13 AM UTC 24 |
Oct 03 10:28:19 AM UTC 24 |
953174453 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1455302017 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:19 AM UTC 24 |
194361851 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3899836291 |
|
|
Oct 03 10:28:16 AM UTC 24 |
Oct 03 10:28:20 AM UTC 24 |
55274538 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1009158749 |
|
|
Oct 03 10:28:18 AM UTC 24 |
Oct 03 10:28:20 AM UTC 24 |
21574464 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.353518487 |
|
|
Oct 03 10:28:18 AM UTC 24 |
Oct 03 10:28:20 AM UTC 24 |
14950344 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.206994055 |
|
|
Oct 03 10:28:18 AM UTC 24 |
Oct 03 10:28:20 AM UTC 24 |
40545467 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3335285476 |
|
|
Oct 03 10:28:18 AM UTC 24 |
Oct 03 10:28:21 AM UTC 24 |
78501751 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1848913139 |
|
|
Oct 03 10:28:19 AM UTC 24 |
Oct 03 10:28:22 AM UTC 24 |
147997020 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1903499561 |
|
|
Oct 03 10:28:19 AM UTC 24 |
Oct 03 10:28:22 AM UTC 24 |
22867773 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3336358960 |
|
|
Oct 03 10:28:19 AM UTC 24 |
Oct 03 10:28:22 AM UTC 24 |
22688600 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.693065226 |
|
|
Oct 03 10:28:20 AM UTC 24 |
Oct 03 10:28:23 AM UTC 24 |
189965931 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.688893210 |
|
|
Oct 03 10:28:20 AM UTC 24 |
Oct 03 10:28:23 AM UTC 24 |
97566865 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3415344658 |
|
|
Oct 03 10:28:20 AM UTC 24 |
Oct 03 10:28:23 AM UTC 24 |
38134892 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2122768916 |
|
|
Oct 03 10:28:16 AM UTC 24 |
Oct 03 10:28:23 AM UTC 24 |
948288306 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4202834299 |
|
|
Oct 03 10:28:20 AM UTC 24 |
Oct 03 10:28:23 AM UTC 24 |
57305856 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2575518191 |
|
|
Oct 03 10:28:21 AM UTC 24 |
Oct 03 10:28:23 AM UTC 24 |
170010230 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.96393728 |
|
|
Oct 03 10:28:21 AM UTC 24 |
Oct 03 10:28:24 AM UTC 24 |
18098532 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2439293234 |
|
|
Oct 03 10:28:21 AM UTC 24 |
Oct 03 10:28:24 AM UTC 24 |
75876471 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.526377542 |
|
|
Oct 03 10:28:21 AM UTC 24 |
Oct 03 10:28:24 AM UTC 24 |
250221249 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2093197876 |
|
|
Oct 03 10:28:21 AM UTC 24 |
Oct 03 10:28:24 AM UTC 24 |
22602218 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1013497137 |
|
|
Oct 03 10:28:21 AM UTC 24 |
Oct 03 10:28:25 AM UTC 24 |
80445822 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2621026472 |
|
|
Oct 03 10:28:21 AM UTC 24 |
Oct 03 10:28:25 AM UTC 24 |
71470144 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1840280102 |
|
|
Oct 03 10:28:19 AM UTC 24 |
Oct 03 10:28:25 AM UTC 24 |
199576642 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4140561229 |
|
|
Oct 03 10:28:21 AM UTC 24 |
Oct 03 10:28:25 AM UTC 24 |
283447257 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3902439645 |
|
|
Oct 03 10:28:12 AM UTC 24 |
Oct 03 10:28:26 AM UTC 24 |
1146051119 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.534077903 |
|
|
Oct 03 10:28:23 AM UTC 24 |
Oct 03 10:28:26 AM UTC 24 |
262286121 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3565730493 |
|
|
Oct 03 10:28:20 AM UTC 24 |
Oct 03 10:28:26 AM UTC 24 |
664306110 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1554445636 |
|
|
Oct 03 10:28:24 AM UTC 24 |
Oct 03 10:28:26 AM UTC 24 |
59854314 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2152798909 |
|
|
Oct 03 10:28:24 AM UTC 24 |
Oct 03 10:28:26 AM UTC 24 |
120020258 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3802904251 |
|
|
Oct 03 10:28:04 AM UTC 24 |
Oct 03 10:28:27 AM UTC 24 |
833939362 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4006168703 |
|
|
Oct 03 10:28:20 AM UTC 24 |
Oct 03 10:28:27 AM UTC 24 |
417946233 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.119840559 |
|
|
Oct 03 10:28:20 AM UTC 24 |
Oct 03 10:28:27 AM UTC 24 |
884895726 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3855873784 |
|
|
Oct 03 10:28:24 AM UTC 24 |
Oct 03 10:28:27 AM UTC 24 |
60813004 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.120689503 |
|
|
Oct 03 10:28:24 AM UTC 24 |
Oct 03 10:28:27 AM UTC 24 |
325081250 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4278746747 |
|
|
Oct 03 10:28:24 AM UTC 24 |
Oct 03 10:28:28 AM UTC 24 |
351626090 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1356688470 |
|
|
Oct 03 10:28:24 AM UTC 24 |
Oct 03 10:28:28 AM UTC 24 |
407428997 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3030477292 |
|
|
Oct 03 10:28:26 AM UTC 24 |
Oct 03 10:28:28 AM UTC 24 |
22241663 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3258008136 |
|
|
Oct 03 10:28:25 AM UTC 24 |
Oct 03 10:28:28 AM UTC 24 |
21976928 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.552865268 |
|
|
Oct 03 10:28:25 AM UTC 24 |
Oct 03 10:28:28 AM UTC 24 |
29057869 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3076548327 |
|
|
Oct 03 10:28:25 AM UTC 24 |
Oct 03 10:28:28 AM UTC 24 |
118231311 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.573107938 |
|
|
Oct 03 10:28:23 AM UTC 24 |
Oct 03 10:28:29 AM UTC 24 |
1618904493 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2980732271 |
|
|
Oct 03 10:28:24 AM UTC 24 |
Oct 03 10:28:29 AM UTC 24 |
161706096 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2618832451 |
|
|
Oct 03 10:28:26 AM UTC 24 |
Oct 03 10:28:29 AM UTC 24 |
544229896 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3522555814 |
|
|
Oct 03 10:28:27 AM UTC 24 |
Oct 03 10:28:29 AM UTC 24 |
227698385 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1550892681 |
|
|
Oct 03 10:28:27 AM UTC 24 |
Oct 03 10:28:30 AM UTC 24 |
51238654 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1617393797 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:31 AM UTC 24 |
25559408 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2720621384 |
|
|
Oct 03 10:28:27 AM UTC 24 |
Oct 03 10:28:30 AM UTC 24 |
49443779 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.302986285 |
|
|
Oct 03 10:28:27 AM UTC 24 |
Oct 03 10:28:30 AM UTC 24 |
120563433 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1846451070 |
|
|
Oct 03 10:28:27 AM UTC 24 |
Oct 03 10:28:30 AM UTC 24 |
37882618 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1163638718 |
|
|
Oct 03 10:28:26 AM UTC 24 |
Oct 03 10:28:31 AM UTC 24 |
896431861 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4123457431 |
|
|
Oct 03 10:28:42 AM UTC 24 |
Oct 03 10:28:44 AM UTC 24 |
225656205 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2489900387 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:31 AM UTC 24 |
52476470 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3122021175 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:31 AM UTC 24 |
67929919 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1332936745 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:32 AM UTC 24 |
119120147 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1679495520 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:32 AM UTC 24 |
76820963 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3020208221 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:32 AM UTC 24 |
194771196 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1913341890 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:32 AM UTC 24 |
22139433 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1575946427 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:32 AM UTC 24 |
71514741 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1445393399 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:32 AM UTC 24 |
151976936 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2571577586 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:32 AM UTC 24 |
105916029 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2541101451 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:33 AM UTC 24 |
311251011 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1400000637 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:33 AM UTC 24 |
145668837 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3063480962 |
|
|
Oct 03 10:28:31 AM UTC 24 |
Oct 03 10:28:33 AM UTC 24 |
69497841 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2101729315 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:33 AM UTC 24 |
821658345 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4276450817 |
|
|
Oct 03 10:28:31 AM UTC 24 |
Oct 03 10:28:33 AM UTC 24 |
46424237 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.306373504 |
|
|
Oct 03 10:28:31 AM UTC 24 |
Oct 03 10:28:33 AM UTC 24 |
29343055 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2105187025 |
|
|
Oct 03 10:28:31 AM UTC 24 |
Oct 03 10:28:34 AM UTC 24 |
190560759 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4246964616 |
|
|
Oct 03 10:28:32 AM UTC 24 |
Oct 03 10:28:34 AM UTC 24 |
43542880 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2485233800 |
|
|
Oct 03 10:28:32 AM UTC 24 |
Oct 03 10:28:35 AM UTC 24 |
15277274 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1763382993 |
|
|
Oct 03 10:28:32 AM UTC 24 |
Oct 03 10:28:35 AM UTC 24 |
376187055 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.659588474 |
|
|
Oct 03 10:28:31 AM UTC 24 |
Oct 03 10:28:35 AM UTC 24 |
419770048 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.281095644 |
|
|
Oct 03 10:28:32 AM UTC 24 |
Oct 03 10:28:35 AM UTC 24 |
21101729 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.376842690 |
|
|
Oct 03 10:28:42 AM UTC 24 |
Oct 03 10:28:44 AM UTC 24 |
37307272 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.410765490 |
|
|
Oct 03 10:28:31 AM UTC 24 |
Oct 03 10:28:35 AM UTC 24 |
153500173 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3762297938 |
|
|
Oct 03 10:28:32 AM UTC 24 |
Oct 03 10:28:36 AM UTC 24 |
1181119782 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1080798668 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:36 AM UTC 24 |
27908126 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4270782269 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:36 AM UTC 24 |
27608574 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.692471270 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:36 AM UTC 24 |
284858892 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3985251848 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:37 AM UTC 24 |
21484818 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1392544231 |
|
|
Oct 03 10:28:43 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
71665795 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2237488330 |
|
|
Oct 03 10:28:26 AM UTC 24 |
Oct 03 10:28:37 AM UTC 24 |
831356635 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3680280727 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:37 AM UTC 24 |
91378694 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3880009900 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:37 AM UTC 24 |
98275621 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4224228920 |
|
|
Oct 03 10:28:32 AM UTC 24 |
Oct 03 10:28:37 AM UTC 24 |
223945678 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2401008198 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:38 AM UTC 24 |
1069347087 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.253821128 |
|
|
Oct 03 10:28:35 AM UTC 24 |
Oct 03 10:28:38 AM UTC 24 |
245244615 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1511812398 |
|
|
Oct 03 10:28:12 AM UTC 24 |
Oct 03 10:28:38 AM UTC 24 |
2738843087 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1980254123 |
|
|
Oct 03 10:28:35 AM UTC 24 |
Oct 03 10:28:38 AM UTC 24 |
50990640 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3798830697 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:44 AM UTC 24 |
141897896 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.496043443 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
198880008 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.169698417 |
|
|
Oct 03 10:28:31 AM UTC 24 |
Oct 03 10:28:39 AM UTC 24 |
942732358 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3164620719 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:39 AM UTC 24 |
193841260 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1988268493 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:39 AM UTC 24 |
21567649 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1182446272 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:39 AM UTC 24 |
47931843 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2259706251 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:40 AM UTC 24 |
828549966 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4034070754 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:40 AM UTC 24 |
116676216 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3741029876 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:40 AM UTC 24 |
47571747 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.475903582 |
|
|
Oct 03 10:28:27 AM UTC 24 |
Oct 03 10:28:40 AM UTC 24 |
448320053 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3405286443 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:40 AM UTC 24 |
71437355 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.744242315 |
|
|
Oct 03 10:28:29 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
7986007190 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.73018242 |
|
|
Oct 03 10:28:35 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
174814291 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3348923535 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
179816170 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1731412302 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
208004140 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3139365319 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
14211435 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1437623704 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
29654646 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1512690298 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
15515926 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.646081989 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
18042708 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2782630001 |
|
|
Oct 03 10:28:35 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
1299809303 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.503467474 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:41 AM UTC 24 |
61273398 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2241677843 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:42 AM UTC 24 |
81961578 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2971204721 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:42 AM UTC 24 |
78562475 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.585457651 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:42 AM UTC 24 |
90823173 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2856605054 |
|
|
Oct 03 10:28:37 AM UTC 24 |
Oct 03 10:28:42 AM UTC 24 |
125826830 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.262573869 |
|
|
Oct 03 10:28:31 AM UTC 24 |
Oct 03 10:28:42 AM UTC 24 |
3708801690 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1955315235 |
|
|
Oct 03 10:28:40 AM UTC 24 |
Oct 03 10:28:43 AM UTC 24 |
15886911 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1726528025 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:43 AM UTC 24 |
62075511 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2285813853 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:43 AM UTC 24 |
33451139 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3425871196 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:43 AM UTC 24 |
48338839 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4200878846 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:43 AM UTC 24 |
145993231 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2453780241 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:44 AM UTC 24 |
51298416 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1580399727 |
|
|
Oct 03 10:28:39 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
128710912 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1397093991 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
430505425 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1200475880 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
109784668 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2449483215 |
|
|
Oct 03 10:28:42 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
35201467 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2805877973 |
|
|
Oct 03 10:28:43 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
32845589 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1887452097 |
|
|
Oct 03 10:28:43 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
74393462 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3973685264 |
|
|
Oct 03 10:28:40 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
147024711 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2656156058 |
|
|
Oct 03 10:28:43 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
19582557 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4050859813 |
|
|
Oct 03 10:28:43 AM UTC 24 |
Oct 03 10:28:45 AM UTC 24 |
67361787 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.602063260 |
|
|
Oct 03 10:28:32 AM UTC 24 |
Oct 03 10:28:46 AM UTC 24 |
4546425922 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2442297707 |
|
|
Oct 03 10:28:35 AM UTC 24 |
Oct 03 10:28:46 AM UTC 24 |
966171541 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3446754972 |
|
|
Oct 03 10:28:42 AM UTC 24 |
Oct 03 10:28:46 AM UTC 24 |
55397087 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2876908300 |
|
|
Oct 03 10:28:43 AM UTC 24 |
Oct 03 10:28:46 AM UTC 24 |
44180436 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4115406563 |
|
|
Oct 03 10:28:15 AM UTC 24 |
Oct 03 10:28:46 AM UTC 24 |
17475301891 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.504545663 |
|
|
Oct 03 10:28:34 AM UTC 24 |
Oct 03 10:28:46 AM UTC 24 |
1030416476 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3849474850 |
|
|
Oct 03 10:28:41 AM UTC 24 |
Oct 03 10:28:47 AM UTC 24 |
675585050 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3115065103 |
|
|
Oct 03 10:28:44 AM UTC 24 |
Oct 03 10:28:47 AM UTC 24 |
32109057 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3713671334 |
|
|
Oct 03 10:28:45 AM UTC 24 |
Oct 03 10:28:47 AM UTC 24 |
24757463 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.881555122 |
|
|
Oct 03 10:28:44 AM UTC 24 |
Oct 03 10:28:47 AM UTC 24 |
17581405 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.293871615 |
|
|
Oct 03 10:28:23 AM UTC 24 |
Oct 03 10:28:47 AM UTC 24 |
1800272704 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2171559153 |
|
|
Oct 03 10:28:44 AM UTC 24 |
Oct 03 10:28:47 AM UTC 24 |
26130598 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2399162207 |
|
|
Oct 03 10:28:44 AM UTC 24 |
Oct 03 10:28:47 AM UTC 24 |
52523314 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4008772672 |
|
|
Oct 03 10:28:43 AM UTC 24 |
Oct 03 10:28:48 AM UTC 24 |
90217967 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1251999762 |
|
|
Oct 03 10:28:44 AM UTC 24 |
Oct 03 10:28:48 AM UTC 24 |
75755829 ps |