| T819 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.1103656123 |
|
|
Oct 12 02:14:18 PM UTC 24 |
Oct 12 02:14:24 PM UTC 24 |
235576013 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.3052856634 |
|
|
Oct 12 02:14:20 PM UTC 24 |
Oct 12 02:14:24 PM UTC 24 |
271152437 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.3850476440 |
|
|
Oct 12 02:14:12 PM UTC 24 |
Oct 12 02:14:24 PM UTC 24 |
907369272 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3670967360 |
|
|
Oct 12 02:13:24 PM UTC 24 |
Oct 12 02:15:10 PM UTC 24 |
5951768216 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1838986590 |
|
|
Oct 12 02:14:12 PM UTC 24 |
Oct 12 02:14:25 PM UTC 24 |
1348714226 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3183520501 |
|
|
Oct 12 02:12:34 PM UTC 24 |
Oct 12 02:15:10 PM UTC 24 |
4701783111 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.4237043339 |
|
|
Oct 12 02:14:11 PM UTC 24 |
Oct 12 02:14:26 PM UTC 24 |
889388520 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1601761692 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:14:28 PM UTC 24 |
14130016 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4237758382 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:14:28 PM UTC 24 |
12929425 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2603641675 |
|
|
Oct 12 02:14:18 PM UTC 24 |
Oct 12 02:14:28 PM UTC 24 |
239162279 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2810018390 |
|
|
Oct 12 02:14:18 PM UTC 24 |
Oct 12 02:14:29 PM UTC 24 |
294539140 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.1641877560 |
|
|
Oct 12 02:14:23 PM UTC 24 |
Oct 12 02:14:30 PM UTC 24 |
138066160 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3202156911 |
|
|
Oct 12 02:14:16 PM UTC 24 |
Oct 12 02:14:30 PM UTC 24 |
106678777 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.1407848915 |
|
|
Oct 12 02:14:23 PM UTC 24 |
Oct 12 02:14:30 PM UTC 24 |
431693927 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.2460140461 |
|
|
Oct 12 02:14:18 PM UTC 24 |
Oct 12 02:14:30 PM UTC 24 |
2592585287 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.3730660418 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:14:30 PM UTC 24 |
39111748 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3929201887 |
|
|
Oct 12 02:14:18 PM UTC 24 |
Oct 12 02:14:30 PM UTC 24 |
1892283526 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.960651984 |
|
|
Oct 12 02:14:18 PM UTC 24 |
Oct 12 02:14:32 PM UTC 24 |
1089279123 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.3934156127 |
|
|
Oct 12 02:14:27 PM UTC 24 |
Oct 12 02:14:32 PM UTC 24 |
80486227 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.210459995 |
|
|
Oct 12 02:14:08 PM UTC 24 |
Oct 12 02:14:33 PM UTC 24 |
1760921920 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.250692016 |
|
|
Oct 12 02:14:18 PM UTC 24 |
Oct 12 02:14:33 PM UTC 24 |
258845152 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1720672854 |
|
|
Oct 12 02:14:03 PM UTC 24 |
Oct 12 02:14:33 PM UTC 24 |
751948273 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.124255946 |
|
|
Oct 12 02:14:31 PM UTC 24 |
Oct 12 02:14:33 PM UTC 24 |
66271260 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.2174188345 |
|
|
Oct 12 02:14:24 PM UTC 24 |
Oct 12 02:14:34 PM UTC 24 |
1278786184 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2981440713 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:14:36 PM UTC 24 |
273401729 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.2569764347 |
|
|
Oct 12 02:14:24 PM UTC 24 |
Oct 12 02:14:38 PM UTC 24 |
385726040 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.3658735959 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:14:39 PM UTC 24 |
622090219 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1409517031 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:14:40 PM UTC 24 |
629941915 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.115514885 |
|
|
Oct 12 02:13:35 PM UTC 24 |
Oct 12 02:14:41 PM UTC 24 |
7469424389 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.71177764 |
|
|
Oct 12 02:14:30 PM UTC 24 |
Oct 12 02:14:42 PM UTC 24 |
1993935425 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.37531099 |
|
|
Oct 12 02:13:28 PM UTC 24 |
Oct 12 02:14:42 PM UTC 24 |
17535437593 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1849505053 |
|
|
Oct 12 02:14:30 PM UTC 24 |
Oct 12 02:14:42 PM UTC 24 |
546980202 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1338760880 |
|
|
Oct 12 02:14:31 PM UTC 24 |
Oct 12 02:14:42 PM UTC 24 |
229406330 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2883988226 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:14:43 PM UTC 24 |
3610672601 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.1306929490 |
|
|
Oct 12 02:14:21 PM UTC 24 |
Oct 12 02:14:43 PM UTC 24 |
138709116 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.706488739 |
|
|
Oct 12 02:14:27 PM UTC 24 |
Oct 12 02:14:43 PM UTC 24 |
1394801556 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.400195553 |
|
|
Oct 12 02:14:30 PM UTC 24 |
Oct 12 02:14:43 PM UTC 24 |
1367769364 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.3556878247 |
|
|
Oct 12 02:14:29 PM UTC 24 |
Oct 12 02:14:45 PM UTC 24 |
803663156 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.3180917953 |
|
|
Oct 12 02:14:31 PM UTC 24 |
Oct 12 02:14:46 PM UTC 24 |
759440833 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.3781700369 |
|
|
Oct 12 02:14:27 PM UTC 24 |
Oct 12 02:14:49 PM UTC 24 |
1661685300 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3404932481 |
|
|
Oct 12 02:13:07 PM UTC 24 |
Oct 12 02:14:52 PM UTC 24 |
2573456868 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3431431696 |
|
|
Oct 12 02:13:12 PM UTC 24 |
Oct 12 02:14:56 PM UTC 24 |
4633881792 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3058321509 |
|
|
Oct 12 02:14:16 PM UTC 24 |
Oct 12 02:14:58 PM UTC 24 |
267866106 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.183112892 |
|
|
Oct 12 02:11:00 PM UTC 24 |
Oct 12 02:15:07 PM UTC 24 |
5945561732 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2627847447 |
|
|
Oct 12 02:11:57 PM UTC 24 |
Oct 12 02:15:08 PM UTC 24 |
6406210516 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1890430817 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:15:08 PM UTC 24 |
3749740353 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3166452941 |
|
|
Oct 12 02:13:43 PM UTC 24 |
Oct 12 02:15:14 PM UTC 24 |
3911076755 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.215891602 |
|
|
Oct 12 02:11:53 PM UTC 24 |
Oct 12 02:15:19 PM UTC 24 |
5645122162 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.2333089890 |
|
|
Oct 12 02:14:20 PM UTC 24 |
Oct 12 02:15:29 PM UTC 24 |
8862069939 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.1953582388 |
|
|
Oct 12 02:11:41 PM UTC 24 |
Oct 12 02:15:31 PM UTC 24 |
45024312794 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2426279878 |
|
|
Oct 12 02:13:48 PM UTC 24 |
Oct 12 02:15:33 PM UTC 24 |
10333586925 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.2162665499 |
|
|
Oct 12 02:14:31 PM UTC 24 |
Oct 12 02:15:38 PM UTC 24 |
10207909745 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.958810079 |
|
|
Oct 12 02:14:12 PM UTC 24 |
Oct 12 02:15:39 PM UTC 24 |
3575816962 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.1952449783 |
|
|
Oct 12 02:13:24 PM UTC 24 |
Oct 12 02:15:44 PM UTC 24 |
3454183574 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.1323240524 |
|
|
Oct 12 02:12:50 PM UTC 24 |
Oct 12 02:16:07 PM UTC 24 |
99117549096 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.266319875 |
|
|
Oct 12 02:13:12 PM UTC 24 |
Oct 12 02:16:08 PM UTC 24 |
11904086745 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.4091383738 |
|
|
Oct 12 02:14:26 PM UTC 24 |
Oct 12 02:16:16 PM UTC 24 |
3933944923 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.390685389 |
|
|
Oct 12 02:10:43 PM UTC 24 |
Oct 12 02:16:30 PM UTC 24 |
43565779787 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.506997088 |
|
|
Oct 12 02:13:07 PM UTC 24 |
Oct 12 02:16:39 PM UTC 24 |
92059188851 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.2519579246 |
|
|
Oct 12 02:13:27 PM UTC 24 |
Oct 12 02:16:41 PM UTC 24 |
8739503905 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2175383411 |
|
|
Oct 12 02:11:31 PM UTC 24 |
Oct 12 02:16:46 PM UTC 24 |
43279578777 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.816910520 |
|
|
Oct 12 02:12:56 PM UTC 24 |
Oct 12 02:16:59 PM UTC 24 |
54113719287 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3408697725 |
|
|
Oct 12 02:12:14 PM UTC 24 |
Oct 12 02:17:09 PM UTC 24 |
33348159409 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3317845026 |
|
|
Oct 12 02:14:07 PM UTC 24 |
Oct 12 02:17:10 PM UTC 24 |
11523475240 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2195312692 |
|
|
Oct 12 02:13:42 PM UTC 24 |
Oct 12 02:18:07 PM UTC 24 |
16744430218 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3464248032 |
|
|
Oct 12 02:14:05 PM UTC 24 |
Oct 12 02:18:20 PM UTC 24 |
8042516347 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.1156324169 |
|
|
Oct 12 02:14:31 PM UTC 24 |
Oct 12 02:19:13 PM UTC 24 |
9297551520 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2828403800 |
|
|
Oct 12 02:13:54 PM UTC 24 |
Oct 12 02:20:32 PM UTC 24 |
11959000110 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.4210310537 |
|
|
Oct 12 02:13:34 PM UTC 24 |
Oct 12 02:21:11 PM UTC 24 |
16615214828 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.601596849 |
|
|
Oct 12 02:13:18 PM UTC 24 |
Oct 12 02:29:51 PM UTC 24 |
34991918970 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.30525429 |
|
|
Oct 12 02:39:24 PM UTC 24 |
Oct 12 02:39:28 PM UTC 24 |
107560420 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2938984797 |
|
|
Oct 12 02:39:26 PM UTC 24 |
Oct 12 02:39:32 PM UTC 24 |
104783553 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3797570610 |
|
|
Oct 12 02:39:33 PM UTC 24 |
Oct 12 02:39:36 PM UTC 24 |
197402795 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3139484306 |
|
|
Oct 12 02:39:36 PM UTC 24 |
Oct 12 02:39:39 PM UTC 24 |
64141523 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4256179672 |
|
|
Oct 12 02:39:36 PM UTC 24 |
Oct 12 02:39:40 PM UTC 24 |
312857607 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2250598527 |
|
|
Oct 12 02:39:38 PM UTC 24 |
Oct 12 02:39:41 PM UTC 24 |
14208544 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3305372105 |
|
|
Oct 12 02:39:37 PM UTC 24 |
Oct 12 02:39:41 PM UTC 24 |
64997486 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2929111783 |
|
|
Oct 12 02:39:37 PM UTC 24 |
Oct 12 02:39:42 PM UTC 24 |
43813113 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2202616975 |
|
|
Oct 12 02:39:39 PM UTC 24 |
Oct 12 02:39:42 PM UTC 24 |
85380890 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1097491069 |
|
|
Oct 12 02:39:32 PM UTC 24 |
Oct 12 02:39:43 PM UTC 24 |
800103119 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3683873056 |
|
|
Oct 12 02:39:42 PM UTC 24 |
Oct 12 02:39:45 PM UTC 24 |
59342508 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3730337296 |
|
|
Oct 12 02:39:42 PM UTC 24 |
Oct 12 02:39:45 PM UTC 24 |
97718443 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2078805221 |
|
|
Oct 12 02:39:42 PM UTC 24 |
Oct 12 02:39:45 PM UTC 24 |
204041741 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3289808486 |
|
|
Oct 12 02:39:41 PM UTC 24 |
Oct 12 02:39:46 PM UTC 24 |
355058456 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2433435254 |
|
|
Oct 12 02:39:43 PM UTC 24 |
Oct 12 02:39:48 PM UTC 24 |
160516577 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1364616722 |
|
|
Oct 12 02:39:43 PM UTC 24 |
Oct 12 02:39:48 PM UTC 24 |
161332886 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.778395332 |
|
|
Oct 12 02:39:45 PM UTC 24 |
Oct 12 02:39:48 PM UTC 24 |
17802165 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.836716402 |
|
|
Oct 12 02:39:47 PM UTC 24 |
Oct 12 02:39:49 PM UTC 24 |
307169111 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1893417972 |
|
|
Oct 12 02:39:47 PM UTC 24 |
Oct 12 02:39:50 PM UTC 24 |
42230584 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4179693258 |
|
|
Oct 12 02:39:48 PM UTC 24 |
Oct 12 02:39:51 PM UTC 24 |
76120652 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2365519054 |
|
|
Oct 12 02:39:49 PM UTC 24 |
Oct 12 02:39:52 PM UTC 24 |
15609372 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.640097880 |
|
|
Oct 12 02:39:46 PM UTC 24 |
Oct 12 02:39:52 PM UTC 24 |
202761692 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3032649863 |
|
|
Oct 12 02:39:48 PM UTC 24 |
Oct 12 02:39:52 PM UTC 24 |
470232932 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2532930146 |
|
|
Oct 12 02:39:49 PM UTC 24 |
Oct 12 02:39:53 PM UTC 24 |
244783087 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.522412083 |
|
|
Oct 12 02:39:50 PM UTC 24 |
Oct 12 02:39:53 PM UTC 24 |
196863001 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.992405055 |
|
|
Oct 12 02:39:51 PM UTC 24 |
Oct 12 02:39:54 PM UTC 24 |
26197797 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3631889468 |
|
|
Oct 12 02:39:44 PM UTC 24 |
Oct 12 02:39:55 PM UTC 24 |
262802017 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2890342093 |
|
|
Oct 12 02:39:53 PM UTC 24 |
Oct 12 02:39:56 PM UTC 24 |
525737268 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.938566300 |
|
|
Oct 12 02:39:54 PM UTC 24 |
Oct 12 02:39:57 PM UTC 24 |
39705435 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2170772731 |
|
|
Oct 12 02:39:52 PM UTC 24 |
Oct 12 02:39:57 PM UTC 24 |
54874559 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1001389404 |
|
|
Oct 12 02:39:53 PM UTC 24 |
Oct 12 02:39:58 PM UTC 24 |
528323707 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2500674716 |
|
|
Oct 12 02:39:54 PM UTC 24 |
Oct 12 02:39:58 PM UTC 24 |
215017832 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1158736131 |
|
|
Oct 12 02:39:55 PM UTC 24 |
Oct 12 02:39:58 PM UTC 24 |
22104948 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3832303046 |
|
|
Oct 12 02:39:56 PM UTC 24 |
Oct 12 02:40:00 PM UTC 24 |
66664624 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2168664951 |
|
|
Oct 12 02:39:58 PM UTC 24 |
Oct 12 02:40:01 PM UTC 24 |
36705459 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.880745330 |
|
|
Oct 12 02:39:58 PM UTC 24 |
Oct 12 02:40:01 PM UTC 24 |
53151028 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.429038578 |
|
|
Oct 12 02:39:57 PM UTC 24 |
Oct 12 02:40:01 PM UTC 24 |
143172455 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1582907227 |
|
|
Oct 12 02:39:59 PM UTC 24 |
Oct 12 02:40:01 PM UTC 24 |
25180550 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3409990724 |
|
|
Oct 12 02:39:58 PM UTC 24 |
Oct 12 02:40:02 PM UTC 24 |
20462875 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.896328514 |
|
|
Oct 12 02:39:29 PM UTC 24 |
Oct 12 02:40:02 PM UTC 24 |
5500733443 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3677814852 |
|
|
Oct 12 02:40:00 PM UTC 24 |
Oct 12 02:40:02 PM UTC 24 |
38081446 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1288478774 |
|
|
Oct 12 02:40:00 PM UTC 24 |
Oct 12 02:40:03 PM UTC 24 |
31835812 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2898345842 |
|
|
Oct 12 02:39:54 PM UTC 24 |
Oct 12 02:40:03 PM UTC 24 |
527101597 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4025743165 |
|
|
Oct 12 02:40:02 PM UTC 24 |
Oct 12 02:40:04 PM UTC 24 |
68003849 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3983048231 |
|
|
Oct 12 02:40:02 PM UTC 24 |
Oct 12 02:40:05 PM UTC 24 |
93508136 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3498828312 |
|
|
Oct 12 02:40:12 PM UTC 24 |
Oct 12 02:40:15 PM UTC 24 |
14365212 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1892663896 |
|
|
Oct 12 02:40:03 PM UTC 24 |
Oct 12 02:40:06 PM UTC 24 |
37484409 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3638439303 |
|
|
Oct 12 02:40:01 PM UTC 24 |
Oct 12 02:40:07 PM UTC 24 |
458559015 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1050996889 |
|
|
Oct 12 02:40:05 PM UTC 24 |
Oct 12 02:40:07 PM UTC 24 |
36564275 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3283155505 |
|
|
Oct 12 02:40:03 PM UTC 24 |
Oct 12 02:40:08 PM UTC 24 |
114576970 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.35325191 |
|
|
Oct 12 02:39:44 PM UTC 24 |
Oct 12 02:40:08 PM UTC 24 |
7362727914 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.536681321 |
|
|
Oct 12 02:40:06 PM UTC 24 |
Oct 12 02:40:09 PM UTC 24 |
16467086 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1537422801 |
|
|
Oct 12 02:40:06 PM UTC 24 |
Oct 12 02:40:09 PM UTC 24 |
93545171 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.101686321 |
|
|
Oct 12 02:40:06 PM UTC 24 |
Oct 12 02:40:09 PM UTC 24 |
368430735 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.939121862 |
|
|
Oct 12 02:40:03 PM UTC 24 |
Oct 12 02:40:09 PM UTC 24 |
136679907 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1595644390 |
|
|
Oct 12 02:40:04 PM UTC 24 |
Oct 12 02:40:10 PM UTC 24 |
367936880 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3422430849 |
|
|
Oct 12 02:40:07 PM UTC 24 |
Oct 12 02:40:10 PM UTC 24 |
19163328 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2634096918 |
|
|
Oct 12 02:40:02 PM UTC 24 |
Oct 12 02:40:10 PM UTC 24 |
1670927458 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2843937550 |
|
|
Oct 12 02:40:08 PM UTC 24 |
Oct 12 02:40:11 PM UTC 24 |
23925389 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.174049801 |
|
|
Oct 12 02:40:09 PM UTC 24 |
Oct 12 02:40:12 PM UTC 24 |
37437092 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1637876895 |
|
|
Oct 12 02:40:10 PM UTC 24 |
Oct 12 02:40:13 PM UTC 24 |
45428207 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.115904971 |
|
|
Oct 12 02:40:08 PM UTC 24 |
Oct 12 02:40:13 PM UTC 24 |
594131856 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2309586322 |
|
|
Oct 12 02:40:11 PM UTC 24 |
Oct 12 02:40:13 PM UTC 24 |
97739543 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2389578493 |
|
|
Oct 12 02:40:11 PM UTC 24 |
Oct 12 02:40:15 PM UTC 24 |
506572765 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1160683702 |
|
|
Oct 12 02:40:11 PM UTC 24 |
Oct 12 02:40:15 PM UTC 24 |
193355327 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.558454933 |
|
|
Oct 12 02:40:12 PM UTC 24 |
Oct 12 02:40:15 PM UTC 24 |
16372719 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3682989499 |
|
|
Oct 12 02:40:13 PM UTC 24 |
Oct 12 02:40:16 PM UTC 24 |
29675298 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1528828718 |
|
|
Oct 12 02:40:11 PM UTC 24 |
Oct 12 02:40:17 PM UTC 24 |
107370352 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2029345005 |
|
|
Oct 12 02:40:14 PM UTC 24 |
Oct 12 02:40:17 PM UTC 24 |
48517091 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3932980607 |
|
|
Oct 12 02:40:14 PM UTC 24 |
Oct 12 02:40:17 PM UTC 24 |
145434295 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3165531911 |
|
|
Oct 12 02:40:15 PM UTC 24 |
Oct 12 02:40:18 PM UTC 24 |
24186166 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3535511057 |
|
|
Oct 12 02:40:16 PM UTC 24 |
Oct 12 02:40:18 PM UTC 24 |
213240200 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.329118301 |
|
|
Oct 12 02:40:16 PM UTC 24 |
Oct 12 02:40:19 PM UTC 24 |
88172245 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4131800833 |
|
|
Oct 12 02:40:17 PM UTC 24 |
Oct 12 02:40:20 PM UTC 24 |
109511975 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.163505858 |
|
|
Oct 12 02:40:09 PM UTC 24 |
Oct 12 02:40:20 PM UTC 24 |
901649567 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1910817019 |
|
|
Oct 12 02:40:19 PM UTC 24 |
Oct 12 02:40:21 PM UTC 24 |
47770770 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.761203200 |
|
|
Oct 12 02:40:16 PM UTC 24 |
Oct 12 02:40:21 PM UTC 24 |
229730899 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3136944824 |
|
|
Oct 12 02:40:19 PM UTC 24 |
Oct 12 02:40:22 PM UTC 24 |
68835567 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.218488782 |
|
|
Oct 12 02:40:19 PM UTC 24 |
Oct 12 02:40:22 PM UTC 24 |
184009174 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2817827128 |
|
|
Oct 12 02:40:09 PM UTC 24 |
Oct 12 02:40:22 PM UTC 24 |
1386503613 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3768376713 |
|
|
Oct 12 02:40:19 PM UTC 24 |
Oct 12 02:40:23 PM UTC 24 |
61956789 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.326564421 |
|
|
Oct 12 02:40:20 PM UTC 24 |
Oct 12 02:40:23 PM UTC 24 |
26709727 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4024332663 |
|
|
Oct 12 02:40:17 PM UTC 24 |
Oct 12 02:40:23 PM UTC 24 |
635655862 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1319469089 |
|
|
Oct 12 02:40:20 PM UTC 24 |
Oct 12 02:40:24 PM UTC 24 |
67920923 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.159767837 |
|
|
Oct 12 02:40:19 PM UTC 24 |
Oct 12 02:40:25 PM UTC 24 |
124012730 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.47395693 |
|
|
Oct 12 02:40:22 PM UTC 24 |
Oct 12 02:40:25 PM UTC 24 |
25662101 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1912913616 |
|
|
Oct 12 02:40:20 PM UTC 24 |
Oct 12 02:40:25 PM UTC 24 |
276080395 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4123954997 |
|
|
Oct 12 02:40:21 PM UTC 24 |
Oct 12 02:40:26 PM UTC 24 |
1142162820 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3300846 |
|
|
Oct 12 02:40:02 PM UTC 24 |
Oct 12 02:40:26 PM UTC 24 |
827809251 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1360227634 |
|
|
Oct 12 02:40:24 PM UTC 24 |
Oct 12 02:40:27 PM UTC 24 |
73840561 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1599489469 |
|
|
Oct 12 02:40:24 PM UTC 24 |
Oct 12 02:40:27 PM UTC 24 |
25921369 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3646435244 |
|
|
Oct 12 02:40:24 PM UTC 24 |
Oct 12 02:40:27 PM UTC 24 |
33380602 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3244198816 |
|
|
Oct 12 02:40:22 PM UTC 24 |
Oct 12 02:40:27 PM UTC 24 |
143881880 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1564783453 |
|
|
Oct 12 02:40:24 PM UTC 24 |
Oct 12 02:40:27 PM UTC 24 |
263062152 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.406659565 |
|
|
Oct 12 02:40:21 PM UTC 24 |
Oct 12 02:40:28 PM UTC 24 |
7100352710 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1742762640 |
|
|
Oct 12 02:40:25 PM UTC 24 |
Oct 12 02:40:28 PM UTC 24 |
78686327 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2836494534 |
|
|
Oct 12 02:40:24 PM UTC 24 |
Oct 12 02:40:29 PM UTC 24 |
116927568 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1070350901 |
|
|
Oct 12 02:40:25 PM UTC 24 |
Oct 12 02:40:29 PM UTC 24 |
564483988 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3384411188 |
|
|
Oct 12 02:40:28 PM UTC 24 |
Oct 12 02:40:30 PM UTC 24 |
45715048 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3831475346 |
|
|
Oct 12 02:40:28 PM UTC 24 |
Oct 12 02:40:30 PM UTC 24 |
39268732 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.145362669 |
|
|
Oct 12 02:40:26 PM UTC 24 |
Oct 12 02:40:31 PM UTC 24 |
161971506 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3667637201 |
|
|
Oct 12 02:40:28 PM UTC 24 |
Oct 12 02:40:31 PM UTC 24 |
47960415 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2908493751 |
|
|
Oct 12 02:40:29 PM UTC 24 |
Oct 12 02:40:31 PM UTC 24 |
45835737 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.169940477 |
|
|
Oct 12 02:40:29 PM UTC 24 |
Oct 12 02:40:32 PM UTC 24 |
32447145 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3296911390 |
|
|
Oct 12 02:40:28 PM UTC 24 |
Oct 12 02:40:32 PM UTC 24 |
106351223 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3901860626 |
|
|
Oct 12 02:40:28 PM UTC 24 |
Oct 12 02:40:32 PM UTC 24 |
189275427 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1484911874 |
|
|
Oct 12 02:40:28 PM UTC 24 |
Oct 12 02:40:33 PM UTC 24 |
248395997 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3680297142 |
|
|
Oct 12 02:40:29 PM UTC 24 |
Oct 12 02:40:33 PM UTC 24 |
311616473 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.786974438 |
|
|
Oct 12 02:40:30 PM UTC 24 |
Oct 12 02:40:34 PM UTC 24 |
121336531 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2760959573 |
|
|
Oct 12 02:40:46 PM UTC 24 |
Oct 12 02:40:49 PM UTC 24 |
60718014 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3255274807 |
|
|
Oct 12 02:40:44 PM UTC 24 |
Oct 12 02:40:50 PM UTC 24 |
108908240 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3983406239 |
|
|
Oct 12 02:40:32 PM UTC 24 |
Oct 12 02:40:35 PM UTC 24 |
104473493 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1231268641 |
|
|
Oct 12 02:40:33 PM UTC 24 |
Oct 12 02:40:35 PM UTC 24 |
25058907 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.363810889 |
|
|
Oct 12 02:40:33 PM UTC 24 |
Oct 12 02:40:35 PM UTC 24 |
56401424 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.413930738 |
|
|
Oct 12 02:40:32 PM UTC 24 |
Oct 12 02:40:36 PM UTC 24 |
72683050 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3556969323 |
|
|
Oct 12 02:40:32 PM UTC 24 |
Oct 12 02:40:37 PM UTC 24 |
209936489 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3201361723 |
|
|
Oct 12 02:40:33 PM UTC 24 |
Oct 12 02:40:37 PM UTC 24 |
163437643 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1527641756 |
|
|
Oct 12 02:40:33 PM UTC 24 |
Oct 12 02:40:37 PM UTC 24 |
35247699 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1690701563 |
|
|
Oct 12 02:40:34 PM UTC 24 |
Oct 12 02:40:37 PM UTC 24 |
52551993 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1400420435 |
|
|
Oct 12 02:40:34 PM UTC 24 |
Oct 12 02:40:37 PM UTC 24 |
59426784 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3104627478 |
|
|
Oct 12 02:40:34 PM UTC 24 |
Oct 12 02:40:39 PM UTC 24 |
171281449 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4205619958 |
|
|
Oct 12 02:40:37 PM UTC 24 |
Oct 12 02:40:39 PM UTC 24 |
26404622 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2978827812 |
|
|
Oct 12 02:40:26 PM UTC 24 |
Oct 12 02:40:40 PM UTC 24 |
966418462 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3143749361 |
|
|
Oct 12 02:40:38 PM UTC 24 |
Oct 12 02:40:41 PM UTC 24 |
21816821 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.885877623 |
|
|
Oct 12 02:40:38 PM UTC 24 |
Oct 12 02:40:41 PM UTC 24 |
43946862 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4177357608 |
|
|
Oct 12 02:40:38 PM UTC 24 |
Oct 12 02:40:41 PM UTC 24 |
28744886 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2965089980 |
|
|
Oct 12 02:40:38 PM UTC 24 |
Oct 12 02:40:42 PM UTC 24 |
105306796 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2265981949 |
|
|
Oct 12 02:40:26 PM UTC 24 |
Oct 12 02:40:42 PM UTC 24 |
1233971189 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3943545279 |
|
|
Oct 12 02:40:37 PM UTC 24 |
Oct 12 02:40:42 PM UTC 24 |
1831717478 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1173683906 |
|
|
Oct 12 02:40:40 PM UTC 24 |
Oct 12 02:40:42 PM UTC 24 |
23951533 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3039743375 |
|
|
Oct 12 02:40:38 PM UTC 24 |
Oct 12 02:40:42 PM UTC 24 |
362808509 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3086051141 |
|
|
Oct 12 02:40:38 PM UTC 24 |
Oct 12 02:40:43 PM UTC 24 |
95230222 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.630817586 |
|
|
Oct 12 02:40:37 PM UTC 24 |
Oct 12 02:40:44 PM UTC 24 |
1816743719 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1863687346 |
|
|
Oct 12 02:40:41 PM UTC 24 |
Oct 12 02:40:44 PM UTC 24 |
17970137 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.620504736 |
|
|
Oct 12 02:40:40 PM UTC 24 |
Oct 12 02:40:44 PM UTC 24 |
81893958 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1881098764 |
|
|
Oct 12 02:40:41 PM UTC 24 |
Oct 12 02:40:44 PM UTC 24 |
98236405 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1732869117 |
|
|
Oct 12 02:40:40 PM UTC 24 |
Oct 12 02:40:45 PM UTC 24 |
119650401 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1712532444 |
|
|
Oct 12 02:40:42 PM UTC 24 |
Oct 12 02:40:45 PM UTC 24 |
14133528 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.202943398 |
|
|
Oct 12 02:40:44 PM UTC 24 |
Oct 12 02:40:46 PM UTC 24 |
18302210 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3469910251 |
|
|
Oct 12 02:40:42 PM UTC 24 |
Oct 12 02:40:46 PM UTC 24 |
42150684 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.455602920 |
|
|
Oct 12 02:40:32 PM UTC 24 |
Oct 12 02:40:46 PM UTC 24 |
589448743 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1384156479 |
|
|
Oct 12 02:40:42 PM UTC 24 |
Oct 12 02:40:47 PM UTC 24 |
114771680 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3697848820 |
|
|
Oct 12 02:40:44 PM UTC 24 |
Oct 12 02:40:47 PM UTC 24 |
92817096 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1388141402 |
|
|
Oct 12 02:40:45 PM UTC 24 |
Oct 12 02:40:47 PM UTC 24 |
65070350 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1400805314 |
|
|
Oct 12 02:40:45 PM UTC 24 |
Oct 12 02:40:47 PM UTC 24 |
34527535 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1967950931 |
|
|
Oct 12 02:40:44 PM UTC 24 |
Oct 12 02:40:48 PM UTC 24 |
297545947 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3278650122 |
|
|
Oct 12 02:40:45 PM UTC 24 |
Oct 12 02:40:48 PM UTC 24 |
295802441 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1861372407 |
|
|
Oct 12 02:40:45 PM UTC 24 |
Oct 12 02:40:48 PM UTC 24 |
86099836 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3092256599 |
|
|
Oct 12 02:40:46 PM UTC 24 |
Oct 12 02:40:48 PM UTC 24 |
51542755 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3158377675 |
|
|
Oct 12 02:40:46 PM UTC 24 |
Oct 12 02:40:50 PM UTC 24 |
103291560 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2873582321 |
|
|
Oct 12 02:40:45 PM UTC 24 |
Oct 12 02:40:50 PM UTC 24 |
57240170 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3544935178 |
|
|
Oct 12 02:40:48 PM UTC 24 |
Oct 12 02:40:50 PM UTC 24 |
14183982 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4240247036 |
|
|
Oct 12 02:40:48 PM UTC 24 |
Oct 12 02:40:50 PM UTC 24 |
24837754 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1508523568 |
|
|
Oct 12 02:40:48 PM UTC 24 |
Oct 12 02:40:52 PM UTC 24 |
43667291 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3330859633 |
|
|
Oct 12 02:40:49 PM UTC 24 |
Oct 12 02:40:52 PM UTC 24 |
19757128 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1142991543 |
|
|
Oct 12 02:40:49 PM UTC 24 |
Oct 12 02:40:52 PM UTC 24 |
14850361 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1447870742 |
|
|
Oct 12 02:40:48 PM UTC 24 |
Oct 12 02:40:52 PM UTC 24 |
38462830 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2590257348 |
|
|
Oct 12 02:40:49 PM UTC 24 |
Oct 12 02:40:52 PM UTC 24 |
128434973 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1871449291 |
|
|
Oct 12 02:40:49 PM UTC 24 |
Oct 12 02:40:53 PM UTC 24 |
100934238 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1996792528 |
|
|
Oct 12 02:40:16 PM UTC 24 |
Oct 12 02:40:53 PM UTC 24 |
4539627560 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.948211853 |
|
|
Oct 12 02:40:51 PM UTC 24 |
Oct 12 02:40:53 PM UTC 24 |
55384342 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.262555648 |
|
|
Oct 12 02:40:51 PM UTC 24 |
Oct 12 02:40:53 PM UTC 24 |
13019688 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1784965892 |
|
|
Oct 12 02:40:49 PM UTC 24 |
Oct 12 02:40:53 PM UTC 24 |
107518766 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.50574268 |
|
|
Oct 12 02:40:51 PM UTC 24 |
Oct 12 02:40:53 PM UTC 24 |
29340180 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.387100348 |
|
|
Oct 12 02:40:35 PM UTC 24 |
Oct 12 02:40:56 PM UTC 24 |
4557875075 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1290728685 |
|
|
Oct 12 02:40:53 PM UTC 24 |
Oct 12 02:40:55 PM UTC 24 |
27066839 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.831660275 |
|
|
Oct 12 02:40:51 PM UTC 24 |
Oct 12 02:40:55 PM UTC 24 |
62602536 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3902595074 |
|
|
Oct 12 02:40:53 PM UTC 24 |
Oct 12 02:40:56 PM UTC 24 |
14811910 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1169047035 |
|
|
Oct 12 02:40:53 PM UTC 24 |
Oct 12 02:40:56 PM UTC 24 |
82630158 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3049633375 |
|
|
Oct 12 02:40:48 PM UTC 24 |
Oct 12 02:40:56 PM UTC 24 |
171018773 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3358461506 |
|
|
Oct 12 02:40:52 PM UTC 24 |
Oct 12 02:40:56 PM UTC 24 |
613821913 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1113301395 |
|
|
Oct 12 02:40:54 PM UTC 24 |
Oct 12 02:40:57 PM UTC 24 |
22177632 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2038523393 |
|
|
Oct 12 02:40:53 PM UTC 24 |
Oct 12 02:40:57 PM UTC 24 |
124101486 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4064131060 |
|
|
Oct 12 02:40:54 PM UTC 24 |
Oct 12 02:40:57 PM UTC 24 |
16372837 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3918950306 |
|
|
Oct 12 02:40:55 PM UTC 24 |
Oct 12 02:40:58 PM UTC 24 |
406847108 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4045373660 |
|
|
Oct 12 02:40:54 PM UTC 24 |
Oct 12 02:40:58 PM UTC 24 |
483941754 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2525473809 |
|
|
Oct 12 02:40:55 PM UTC 24 |
Oct 12 02:40:58 PM UTC 24 |
233125443 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1837550455 |
|
|
Oct 12 02:40:55 PM UTC 24 |
Oct 12 02:40:59 PM UTC 24 |
141015788 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4114791777 |
|
|
Oct 12 02:40:48 PM UTC 24 |
Oct 12 02:40:59 PM UTC 24 |
379200095 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.620406925 |
|
|
Oct 12 02:40:57 PM UTC 24 |
Oct 12 02:40:59 PM UTC 24 |
37166785 ps |