| T180 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2557499024 |
|
|
Oct 15 04:37:02 AM UTC 24 |
Oct 15 04:38:14 AM UTC 24 |
3327861965 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.2759632337 |
|
|
Oct 15 04:37:43 AM UTC 24 |
Oct 15 04:38:14 AM UTC 24 |
1329462062 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.3800056228 |
|
|
Oct 15 04:38:04 AM UTC 24 |
Oct 15 04:38:14 AM UTC 24 |
189858299 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.3503641976 |
|
|
Oct 15 04:38:09 AM UTC 24 |
Oct 15 04:38:14 AM UTC 24 |
69302398 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.1319027893 |
|
|
Oct 15 04:38:10 AM UTC 24 |
Oct 15 04:38:15 AM UTC 24 |
75618613 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3711160782 |
|
|
Oct 15 04:38:04 AM UTC 24 |
Oct 15 04:38:18 AM UTC 24 |
541427127 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.346801948 |
|
|
Oct 15 04:37:54 AM UTC 24 |
Oct 15 04:38:19 AM UTC 24 |
423433411 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.2134032514 |
|
|
Oct 15 04:38:12 AM UTC 24 |
Oct 15 04:38:20 AM UTC 24 |
4816673548 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.3536951434 |
|
|
Oct 15 04:38:15 AM UTC 24 |
Oct 15 04:38:21 AM UTC 24 |
110272556 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2227745336 |
|
|
Oct 15 04:38:20 AM UTC 24 |
Oct 15 04:38:23 AM UTC 24 |
155333918 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.509076304 |
|
|
Oct 15 04:38:02 AM UTC 24 |
Oct 15 04:38:23 AM UTC 24 |
568999504 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1140917083 |
|
|
Oct 15 04:37:31 AM UTC 24 |
Oct 15 04:38:24 AM UTC 24 |
5834372497 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.349800725 |
|
|
Oct 15 04:38:22 AM UTC 24 |
Oct 15 04:38:24 AM UTC 24 |
17816123 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.761595357 |
|
|
Oct 15 04:37:52 AM UTC 24 |
Oct 15 04:38:24 AM UTC 24 |
858925132 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.2429985192 |
|
|
Oct 15 04:38:10 AM UTC 24 |
Oct 15 04:38:25 AM UTC 24 |
440202990 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.3347117806 |
|
|
Oct 15 04:38:15 AM UTC 24 |
Oct 15 04:38:26 AM UTC 24 |
964132215 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.163856964 |
|
|
Oct 15 04:38:24 AM UTC 24 |
Oct 15 04:38:26 AM UTC 24 |
22245325 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.432563162 |
|
|
Oct 15 04:38:15 AM UTC 24 |
Oct 15 04:38:26 AM UTC 24 |
1182965336 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3369610904 |
|
|
Oct 15 04:39:01 AM UTC 24 |
Oct 15 04:39:13 AM UTC 24 |
319206239 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.4034544629 |
|
|
Oct 15 04:38:10 AM UTC 24 |
Oct 15 04:38:27 AM UTC 24 |
455470011 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.181284014 |
|
|
Oct 15 04:38:25 AM UTC 24 |
Oct 15 04:38:28 AM UTC 24 |
100415623 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3284018924 |
|
|
Oct 15 04:38:09 AM UTC 24 |
Oct 15 04:38:31 AM UTC 24 |
322892438 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.4023577067 |
|
|
Oct 15 04:38:26 AM UTC 24 |
Oct 15 04:38:32 AM UTC 24 |
596988345 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.4291402682 |
|
|
Oct 15 04:37:38 AM UTC 24 |
Oct 15 04:38:32 AM UTC 24 |
10256806792 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2501683027 |
|
|
Oct 15 04:38:15 AM UTC 24 |
Oct 15 04:38:35 AM UTC 24 |
1403184145 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.414841730 |
|
|
Oct 15 04:38:16 AM UTC 24 |
Oct 15 04:38:36 AM UTC 24 |
688797308 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.3330259862 |
|
|
Oct 15 04:38:15 AM UTC 24 |
Oct 15 04:38:37 AM UTC 24 |
762533292 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.2534761243 |
|
|
Oct 15 04:37:22 AM UTC 24 |
Oct 15 04:38:37 AM UTC 24 |
1427553191 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2817591175 |
|
|
Oct 15 04:38:25 AM UTC 24 |
Oct 15 04:38:37 AM UTC 24 |
203723200 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.564739739 |
|
|
Oct 15 04:38:26 AM UTC 24 |
Oct 15 04:38:39 AM UTC 24 |
469438025 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2227409461 |
|
|
Oct 15 04:38:38 AM UTC 24 |
Oct 15 04:38:40 AM UTC 24 |
25721912 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2087200869 |
|
|
Oct 15 04:38:38 AM UTC 24 |
Oct 15 04:38:40 AM UTC 24 |
12274283 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.2047359055 |
|
|
Oct 15 04:38:32 AM UTC 24 |
Oct 15 04:38:42 AM UTC 24 |
700026966 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.1905427165 |
|
|
Oct 15 04:38:38 AM UTC 24 |
Oct 15 04:38:44 AM UTC 24 |
108926749 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3212651025 |
|
|
Oct 15 04:38:28 AM UTC 24 |
Oct 15 04:38:44 AM UTC 24 |
1871792062 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.49347028 |
|
|
Oct 15 04:38:25 AM UTC 24 |
Oct 15 04:38:46 AM UTC 24 |
326746642 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.641514360 |
|
|
Oct 15 04:38:41 AM UTC 24 |
Oct 15 04:38:46 AM UTC 24 |
153699267 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.3164196589 |
|
|
Oct 15 04:38:29 AM UTC 24 |
Oct 15 04:38:47 AM UTC 24 |
1750802367 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3112793087 |
|
|
Oct 15 04:38:04 AM UTC 24 |
Oct 15 04:38:48 AM UTC 24 |
911487151 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.902540781 |
|
|
Oct 15 04:38:33 AM UTC 24 |
Oct 15 04:38:48 AM UTC 24 |
3691583941 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.573224642 |
|
|
Oct 15 04:38:24 AM UTC 24 |
Oct 15 04:38:49 AM UTC 24 |
151511870 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.410867946 |
|
|
Oct 15 04:37:29 AM UTC 24 |
Oct 15 04:38:49 AM UTC 24 |
2099153005 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.614081438 |
|
|
Oct 15 04:38:40 AM UTC 24 |
Oct 15 04:38:51 AM UTC 24 |
63757012 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.1110472541 |
|
|
Oct 15 04:38:32 AM UTC 24 |
Oct 15 04:38:51 AM UTC 24 |
499292661 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.3133295712 |
|
|
Oct 15 04:38:43 AM UTC 24 |
Oct 15 04:38:54 AM UTC 24 |
1644786538 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.1099274090 |
|
|
Oct 15 04:37:54 AM UTC 24 |
Oct 15 04:38:55 AM UTC 24 |
9032507457 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.2109583344 |
|
|
Oct 15 04:38:45 AM UTC 24 |
Oct 15 04:38:57 AM UTC 24 |
669482445 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.1728102088 |
|
|
Oct 15 04:38:55 AM UTC 24 |
Oct 15 04:38:58 AM UTC 24 |
17617686 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3042679206 |
|
|
Oct 15 04:38:56 AM UTC 24 |
Oct 15 04:38:59 AM UTC 24 |
43344963 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.2974103398 |
|
|
Oct 15 04:38:41 AM UTC 24 |
Oct 15 04:38:59 AM UTC 24 |
348513588 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3249873344 |
|
|
Oct 15 04:38:29 AM UTC 24 |
Oct 15 04:39:00 AM UTC 24 |
3564558490 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3374412954 |
|
|
Oct 15 04:38:49 AM UTC 24 |
Oct 15 04:39:01 AM UTC 24 |
395885766 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.1150776174 |
|
|
Oct 15 04:38:55 AM UTC 24 |
Oct 15 04:39:01 AM UTC 24 |
67498630 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.792156464 |
|
|
Oct 15 04:38:49 AM UTC 24 |
Oct 15 04:39:01 AM UTC 24 |
1233813276 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.4233547679 |
|
|
Oct 15 04:38:47 AM UTC 24 |
Oct 15 04:39:01 AM UTC 24 |
1886346662 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.1371972410 |
|
|
Oct 15 04:39:04 AM UTC 24 |
Oct 15 04:39:12 AM UTC 24 |
972900054 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.3206935976 |
|
|
Oct 15 04:38:28 AM UTC 24 |
Oct 15 04:39:02 AM UTC 24 |
3059660988 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1872452660 |
|
|
Oct 15 04:38:49 AM UTC 24 |
Oct 15 04:39:03 AM UTC 24 |
1119976511 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.1786046270 |
|
|
Oct 15 04:38:47 AM UTC 24 |
Oct 15 04:39:03 AM UTC 24 |
1230199913 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.4239573992 |
|
|
Oct 15 04:38:29 AM UTC 24 |
Oct 15 04:39:05 AM UTC 24 |
1588589142 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.3000593923 |
|
|
Oct 15 04:39:00 AM UTC 24 |
Oct 15 04:39:05 AM UTC 24 |
131684571 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.2959032416 |
|
|
Oct 15 04:39:02 AM UTC 24 |
Oct 15 04:39:07 AM UTC 24 |
293649933 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.11603222 |
|
|
Oct 15 04:38:38 AM UTC 24 |
Oct 15 04:39:08 AM UTC 24 |
590671904 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.648571671 |
|
|
Oct 15 04:38:59 AM UTC 24 |
Oct 15 04:39:09 AM UTC 24 |
296239603 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.421424573 |
|
|
Oct 15 04:38:51 AM UTC 24 |
Oct 15 04:39:09 AM UTC 24 |
758957130 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.3529584175 |
|
|
Oct 15 04:35:59 AM UTC 24 |
Oct 15 04:39:12 AM UTC 24 |
4121510079 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.3529544665 |
|
|
Oct 15 04:39:10 AM UTC 24 |
Oct 15 04:39:13 AM UTC 24 |
125978796 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.926168659 |
|
|
Oct 15 04:39:00 AM UTC 24 |
Oct 15 04:39:13 AM UTC 24 |
155025758 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.89537859 |
|
|
Oct 15 04:39:12 AM UTC 24 |
Oct 15 04:39:14 AM UTC 24 |
56401569 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.398826379 |
|
|
Oct 15 04:39:10 AM UTC 24 |
Oct 15 04:39:14 AM UTC 24 |
131457362 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1858483470 |
|
|
Oct 15 04:38:20 AM UTC 24 |
Oct 15 04:39:15 AM UTC 24 |
1435930815 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.253787873 |
|
|
Oct 15 04:38:15 AM UTC 24 |
Oct 15 04:39:17 AM UTC 24 |
1437577928 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.125165245 |
|
|
Oct 15 04:38:01 AM UTC 24 |
Oct 15 04:39:17 AM UTC 24 |
3872654426 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.3969790671 |
|
|
Oct 15 04:38:04 AM UTC 24 |
Oct 15 04:39:18 AM UTC 24 |
3455584197 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.2291255134 |
|
|
Oct 15 04:39:06 AM UTC 24 |
Oct 15 04:39:19 AM UTC 24 |
242349389 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.176123463 |
|
|
Oct 15 04:39:14 AM UTC 24 |
Oct 15 04:39:20 AM UTC 24 |
147554171 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.1194461931 |
|
|
Oct 15 04:40:06 AM UTC 24 |
Oct 15 04:40:21 AM UTC 24 |
390878300 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.982364268 |
|
|
Oct 15 04:39:05 AM UTC 24 |
Oct 15 04:39:21 AM UTC 24 |
1583232136 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.2087293792 |
|
|
Oct 15 04:39:06 AM UTC 24 |
Oct 15 04:39:21 AM UTC 24 |
370731569 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1021749719 |
|
|
Oct 15 04:39:13 AM UTC 24 |
Oct 15 04:39:22 AM UTC 24 |
183276690 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.3175597485 |
|
|
Oct 15 04:39:19 AM UTC 24 |
Oct 15 04:39:23 AM UTC 24 |
107951724 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.384286031 |
|
|
Oct 15 04:39:02 AM UTC 24 |
Oct 15 04:39:24 AM UTC 24 |
1162862408 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.1742740501 |
|
|
Oct 15 04:38:12 AM UTC 24 |
Oct 15 04:39:25 AM UTC 24 |
7320371070 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.3530593491 |
|
|
Oct 15 04:39:02 AM UTC 24 |
Oct 15 04:39:25 AM UTC 24 |
579576774 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.1645967936 |
|
|
Oct 15 04:39:23 AM UTC 24 |
Oct 15 04:39:25 AM UTC 24 |
29529486 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.3850895384 |
|
|
Oct 15 04:39:14 AM UTC 24 |
Oct 15 04:39:26 AM UTC 24 |
222664880 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.2152541876 |
|
|
Oct 15 04:39:18 AM UTC 24 |
Oct 15 04:39:27 AM UTC 24 |
1206642114 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.2689720997 |
|
|
Oct 15 04:39:14 AM UTC 24 |
Oct 15 04:39:27 AM UTC 24 |
1220165207 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3033629141 |
|
|
Oct 15 04:39:25 AM UTC 24 |
Oct 15 04:39:28 AM UTC 24 |
42250053 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.105470981 |
|
|
Oct 15 04:39:25 AM UTC 24 |
Oct 15 04:39:29 AM UTC 24 |
157408402 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.4018358656 |
|
|
Oct 15 04:38:46 AM UTC 24 |
Oct 15 04:39:31 AM UTC 24 |
3576548008 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.3951864904 |
|
|
Oct 15 04:39:27 AM UTC 24 |
Oct 15 04:39:32 AM UTC 24 |
396855397 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.4114126280 |
|
|
Oct 15 04:40:15 AM UTC 24 |
Oct 15 04:40:20 AM UTC 24 |
58148261 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.3840187870 |
|
|
Oct 15 04:38:59 AM UTC 24 |
Oct 15 04:39:32 AM UTC 24 |
350755925 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.4015265874 |
|
|
Oct 15 04:39:27 AM UTC 24 |
Oct 15 04:39:33 AM UTC 24 |
54345661 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.3712418438 |
|
|
Oct 15 04:39:22 AM UTC 24 |
Oct 15 04:39:33 AM UTC 24 |
730503359 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2512063914 |
|
|
Oct 15 04:39:15 AM UTC 24 |
Oct 15 04:39:33 AM UTC 24 |
632959179 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.3321507607 |
|
|
Oct 15 04:39:21 AM UTC 24 |
Oct 15 04:39:34 AM UTC 24 |
1193217615 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.2903709562 |
|
|
Oct 15 04:39:29 AM UTC 24 |
Oct 15 04:39:35 AM UTC 24 |
379223322 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3338580915 |
|
|
Oct 15 04:39:21 AM UTC 24 |
Oct 15 04:39:37 AM UTC 24 |
429367124 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.349973413 |
|
|
Oct 15 04:39:17 AM UTC 24 |
Oct 15 04:39:38 AM UTC 24 |
995824746 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.1222222815 |
|
|
Oct 15 04:39:28 AM UTC 24 |
Oct 15 04:39:40 AM UTC 24 |
1138549323 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.3960284137 |
|
|
Oct 15 04:40:06 AM UTC 24 |
Oct 15 04:40:17 AM UTC 24 |
230126386 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.1861963998 |
|
|
Oct 15 04:39:02 AM UTC 24 |
Oct 15 04:39:41 AM UTC 24 |
23133961668 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.383629021 |
|
|
Oct 15 04:39:39 AM UTC 24 |
Oct 15 04:39:42 AM UTC 24 |
86375497 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3959776057 |
|
|
Oct 15 04:39:13 AM UTC 24 |
Oct 15 04:39:43 AM UTC 24 |
1168737808 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2851922765 |
|
|
Oct 15 04:39:42 AM UTC 24 |
Oct 15 04:39:44 AM UTC 24 |
19021102 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.2009591697 |
|
|
Oct 15 04:38:33 AM UTC 24 |
Oct 15 04:39:44 AM UTC 24 |
6914191343 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.2131446530 |
|
|
Oct 15 04:39:28 AM UTC 24 |
Oct 15 04:39:44 AM UTC 24 |
1218275922 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.3820386675 |
|
|
Oct 15 04:39:42 AM UTC 24 |
Oct 15 04:39:44 AM UTC 24 |
29441540 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.1030034311 |
|
|
Oct 15 04:39:35 AM UTC 24 |
Oct 15 04:39:45 AM UTC 24 |
897917494 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.4244999462 |
|
|
Oct 15 04:39:32 AM UTC 24 |
Oct 15 04:39:47 AM UTC 24 |
812232934 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.3311163106 |
|
|
Oct 15 04:39:34 AM UTC 24 |
Oct 15 04:39:48 AM UTC 24 |
3906959660 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.2213887599 |
|
|
Oct 15 04:39:34 AM UTC 24 |
Oct 15 04:39:48 AM UTC 24 |
245100768 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.2613143670 |
|
|
Oct 15 04:39:45 AM UTC 24 |
Oct 15 04:39:49 AM UTC 24 |
75144499 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.2094475605 |
|
|
Oct 15 04:40:04 AM UTC 24 |
Oct 15 04:40:19 AM UTC 24 |
1025414187 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.2102177469 |
|
|
Oct 15 04:39:44 AM UTC 24 |
Oct 15 04:39:49 AM UTC 24 |
60296022 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.2058577020 |
|
|
Oct 15 04:39:31 AM UTC 24 |
Oct 15 04:39:53 AM UTC 24 |
2119481424 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2076985951 |
|
|
Oct 15 04:39:43 AM UTC 24 |
Oct 15 04:39:54 AM UTC 24 |
193663134 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.4212160224 |
|
|
Oct 15 04:39:34 AM UTC 24 |
Oct 15 04:39:54 AM UTC 24 |
705230754 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.1032642378 |
|
|
Oct 15 04:39:19 AM UTC 24 |
Oct 15 04:39:54 AM UTC 24 |
4329909192 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.419568119 |
|
|
Oct 15 04:39:27 AM UTC 24 |
Oct 15 04:39:55 AM UTC 24 |
687646454 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.788149122 |
|
|
Oct 15 04:39:45 AM UTC 24 |
Oct 15 04:39:56 AM UTC 24 |
217574023 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.4291156586 |
|
|
Oct 15 04:39:15 AM UTC 24 |
Oct 15 04:39:57 AM UTC 24 |
1994897538 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.2953502474 |
|
|
Oct 15 04:39:44 AM UTC 24 |
Oct 15 04:39:57 AM UTC 24 |
745217633 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.901533897 |
|
|
Oct 15 04:39:56 AM UTC 24 |
Oct 15 04:39:58 AM UTC 24 |
27147478 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2273135748 |
|
|
Oct 15 04:39:56 AM UTC 24 |
Oct 15 04:39:58 AM UTC 24 |
18397723 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.81183226 |
|
|
Oct 15 04:39:49 AM UTC 24 |
Oct 15 04:39:59 AM UTC 24 |
1092225998 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.179605283 |
|
|
Oct 15 04:39:48 AM UTC 24 |
Oct 15 04:40:01 AM UTC 24 |
331741567 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.2397445933 |
|
|
Oct 15 04:39:50 AM UTC 24 |
Oct 15 04:40:02 AM UTC 24 |
247875412 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.4158445925 |
|
|
Oct 15 04:39:56 AM UTC 24 |
Oct 15 04:40:02 AM UTC 24 |
62674002 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.4232636444 |
|
|
Oct 15 04:40:14 AM UTC 24 |
Oct 15 04:40:18 AM UTC 24 |
208377589 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.961633407 |
|
|
Oct 15 04:39:58 AM UTC 24 |
Oct 15 04:40:03 AM UTC 24 |
129091705 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.3086885058 |
|
|
Oct 15 04:39:02 AM UTC 24 |
Oct 15 04:40:04 AM UTC 24 |
5999152749 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2357335095 |
|
|
Oct 15 04:39:50 AM UTC 24 |
Oct 15 04:40:04 AM UTC 24 |
295877209 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.228632585 |
|
|
Oct 15 04:40:00 AM UTC 24 |
Oct 15 04:40:07 AM UTC 24 |
699572107 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3768971688 |
|
|
Oct 15 04:39:52 AM UTC 24 |
Oct 15 04:40:09 AM UTC 24 |
423707632 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.822238709 |
|
|
Oct 15 04:37:47 AM UTC 24 |
Oct 15 04:40:10 AM UTC 24 |
3295684995 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.3490167063 |
|
|
Oct 15 04:39:58 AM UTC 24 |
Oct 15 04:40:12 AM UTC 24 |
73712353 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.3560290754 |
|
|
Oct 15 04:39:43 AM UTC 24 |
Oct 15 04:40:13 AM UTC 24 |
453651912 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.1441123068 |
|
|
Oct 15 04:40:03 AM UTC 24 |
Oct 15 04:40:14 AM UTC 24 |
1323836374 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3562312324 |
|
|
Oct 15 04:40:11 AM UTC 24 |
Oct 15 04:40:14 AM UTC 24 |
76997108 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.1454834511 |
|
|
Oct 15 04:40:03 AM UTC 24 |
Oct 15 04:40:19 AM UTC 24 |
1361881160 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.397216048 |
|
|
Oct 15 04:40:00 AM UTC 24 |
Oct 15 04:40:14 AM UTC 24 |
409655143 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1169782040 |
|
|
Oct 15 04:40:14 AM UTC 24 |
Oct 15 04:40:16 AM UTC 24 |
131285928 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1088899181 |
|
|
Oct 15 04:40:00 AM UTC 24 |
Oct 15 04:40:24 AM UTC 24 |
2761511342 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.4037257858 |
|
|
Oct 15 04:39:47 AM UTC 24 |
Oct 15 04:40:20 AM UTC 24 |
1090548914 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.3302017163 |
|
|
Oct 15 04:38:48 AM UTC 24 |
Oct 15 04:40:22 AM UTC 24 |
19583131149 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.3989638287 |
|
|
Oct 15 04:40:21 AM UTC 24 |
Oct 15 04:40:23 AM UTC 24 |
30280128 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.1145172878 |
|
|
Oct 15 04:39:49 AM UTC 24 |
Oct 15 04:40:24 AM UTC 24 |
8733854226 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.4272707954 |
|
|
Oct 15 04:40:06 AM UTC 24 |
Oct 15 04:40:24 AM UTC 24 |
399777860 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1002858146 |
|
|
Oct 15 04:40:23 AM UTC 24 |
Oct 15 04:40:26 AM UTC 24 |
19225773 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.1826754387 |
|
|
Oct 15 04:40:15 AM UTC 24 |
Oct 15 04:40:26 AM UTC 24 |
80289895 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.65624943 |
|
|
Oct 15 04:40:22 AM UTC 24 |
Oct 15 04:40:26 AM UTC 24 |
99743359 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.2654705375 |
|
|
Oct 15 04:40:19 AM UTC 24 |
Oct 15 04:40:27 AM UTC 24 |
961999757 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.1412100836 |
|
|
Oct 15 04:39:57 AM UTC 24 |
Oct 15 04:40:27 AM UTC 24 |
1246758641 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3856896720 |
|
|
Oct 15 04:40:15 AM UTC 24 |
Oct 15 04:40:27 AM UTC 24 |
1648427335 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1754880236 |
|
|
Oct 15 04:40:17 AM UTC 24 |
Oct 15 04:40:28 AM UTC 24 |
555210561 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.3723200829 |
|
|
Oct 15 04:40:26 AM UTC 24 |
Oct 15 04:40:31 AM UTC 24 |
578650159 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.3858206746 |
|
|
Oct 15 04:40:29 AM UTC 24 |
Oct 15 04:40:32 AM UTC 24 |
46595230 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.2196974688 |
|
|
Oct 15 04:40:25 AM UTC 24 |
Oct 15 04:40:34 AM UTC 24 |
151761145 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1785427349 |
|
|
Oct 15 04:40:20 AM UTC 24 |
Oct 15 04:40:34 AM UTC 24 |
333701411 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.3502355682 |
|
|
Oct 15 04:40:19 AM UTC 24 |
Oct 15 04:40:35 AM UTC 24 |
492302170 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.2737686226 |
|
|
Oct 15 04:39:30 AM UTC 24 |
Oct 15 04:40:35 AM UTC 24 |
2868197280 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.108064787 |
|
|
Oct 15 04:40:33 AM UTC 24 |
Oct 15 04:40:36 AM UTC 24 |
48858324 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.652609792 |
|
|
Oct 15 04:40:32 AM UTC 24 |
Oct 15 04:40:37 AM UTC 24 |
61412913 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.1812737040 |
|
|
Oct 15 04:40:35 AM UTC 24 |
Oct 15 04:40:39 AM UTC 24 |
75255208 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.2406325405 |
|
|
Oct 15 04:40:27 AM UTC 24 |
Oct 15 04:40:40 AM UTC 24 |
336792158 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1332095540 |
|
|
Oct 15 04:40:26 AM UTC 24 |
Oct 15 04:40:41 AM UTC 24 |
1496300706 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.839497500 |
|
|
Oct 15 04:40:39 AM UTC 24 |
Oct 15 04:40:42 AM UTC 24 |
1468384057 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.138813792 |
|
|
Oct 15 04:40:19 AM UTC 24 |
Oct 15 04:40:42 AM UTC 24 |
554525474 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2463832384 |
|
|
Oct 15 04:40:27 AM UTC 24 |
Oct 15 04:40:43 AM UTC 24 |
698942240 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2900473793 |
|
|
Oct 15 04:39:09 AM UTC 24 |
Oct 15 04:40:43 AM UTC 24 |
5342232753 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.3834510799 |
|
|
Oct 15 04:40:15 AM UTC 24 |
Oct 15 04:40:44 AM UTC 24 |
202985406 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.2900213315 |
|
|
Oct 15 04:40:27 AM UTC 24 |
Oct 15 04:40:44 AM UTC 24 |
1054703645 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3602530622 |
|
|
Oct 15 04:40:36 AM UTC 24 |
Oct 15 04:40:44 AM UTC 24 |
186460591 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.432372153 |
|
|
Oct 15 04:40:45 AM UTC 24 |
Oct 15 04:40:47 AM UTC 24 |
56763262 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3210786141 |
|
|
Oct 15 04:40:45 AM UTC 24 |
Oct 15 04:40:47 AM UTC 24 |
26287373 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.4109501255 |
|
|
Oct 15 04:40:35 AM UTC 24 |
Oct 15 04:40:47 AM UTC 24 |
56814905 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.2252720228 |
|
|
Oct 15 04:40:45 AM UTC 24 |
Oct 15 04:40:47 AM UTC 24 |
35390023 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3593911357 |
|
|
Oct 15 04:39:33 AM UTC 24 |
Oct 15 04:40:47 AM UTC 24 |
14130328798 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2516656604 |
|
|
Oct 15 04:40:29 AM UTC 24 |
Oct 15 04:40:48 AM UTC 24 |
3000798890 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1996381874 |
|
|
Oct 15 04:40:27 AM UTC 24 |
Oct 15 04:40:49 AM UTC 24 |
14454826608 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.4012834610 |
|
|
Oct 15 04:40:02 AM UTC 24 |
Oct 15 04:40:49 AM UTC 24 |
30119556076 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.617914965 |
|
|
Oct 15 04:40:41 AM UTC 24 |
Oct 15 04:40:50 AM UTC 24 |
344849506 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.3606012512 |
|
|
Oct 15 04:40:48 AM UTC 24 |
Oct 15 04:40:52 AM UTC 24 |
74421373 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2753088061 |
|
|
Oct 15 04:40:48 AM UTC 24 |
Oct 15 04:40:52 AM UTC 24 |
142456382 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.4094118172 |
|
|
Oct 15 04:40:46 AM UTC 24 |
Oct 15 04:40:55 AM UTC 24 |
64545947 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.2418188057 |
|
|
Oct 15 04:40:53 AM UTC 24 |
Oct 15 04:40:55 AM UTC 24 |
52746798 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.94768570 |
|
|
Oct 15 04:40:42 AM UTC 24 |
Oct 15 04:40:55 AM UTC 24 |
564240182 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3664635386 |
|
|
Oct 15 04:40:53 AM UTC 24 |
Oct 15 04:40:56 AM UTC 24 |
76527117 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.1862725027 |
|
|
Oct 15 04:40:40 AM UTC 24 |
Oct 15 04:40:58 AM UTC 24 |
357876699 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.835387704 |
|
|
Oct 15 04:40:56 AM UTC 24 |
Oct 15 04:40:59 AM UTC 24 |
34842260 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.1365215430 |
|
|
Oct 15 04:40:24 AM UTC 24 |
Oct 15 04:41:00 AM UTC 24 |
244001417 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.4024095663 |
|
|
Oct 15 04:40:50 AM UTC 24 |
Oct 15 04:41:01 AM UTC 24 |
268628901 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.3549941662 |
|
|
Oct 15 04:40:50 AM UTC 24 |
Oct 15 04:41:01 AM UTC 24 |
317887490 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2156844756 |
|
|
Oct 15 04:40:57 AM UTC 24 |
Oct 15 04:41:03 AM UTC 24 |
520348491 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.3727884369 |
|
|
Oct 15 04:40:56 AM UTC 24 |
Oct 15 04:41:04 AM UTC 24 |
115607467 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2427506340 |
|
|
Oct 15 04:40:48 AM UTC 24 |
Oct 15 04:41:04 AM UTC 24 |
427388556 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2286767806 |
|
|
Oct 15 04:40:36 AM UTC 24 |
Oct 15 04:41:05 AM UTC 24 |
709870368 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.3581999674 |
|
|
Oct 15 04:41:00 AM UTC 24 |
Oct 15 04:41:06 AM UTC 24 |
649616381 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.1603858943 |
|
|
Oct 15 04:41:06 AM UTC 24 |
Oct 15 04:41:08 AM UTC 24 |
29233260 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.717823832 |
|
|
Oct 15 04:40:35 AM UTC 24 |
Oct 15 04:41:09 AM UTC 24 |
2414852843 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.68954023 |
|
|
Oct 15 04:41:07 AM UTC 24 |
Oct 15 04:41:09 AM UTC 24 |
15323493 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.498597483 |
|
|
Oct 15 04:41:06 AM UTC 24 |
Oct 15 04:41:10 AM UTC 24 |
337183177 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.2844198162 |
|
|
Oct 15 04:40:48 AM UTC 24 |
Oct 15 04:41:10 AM UTC 24 |
890608772 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.1556372447 |
|
|
Oct 15 04:40:59 AM UTC 24 |
Oct 15 04:41:11 AM UTC 24 |
1459798792 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.3974492604 |
|
|
Oct 15 04:40:45 AM UTC 24 |
Oct 15 04:41:11 AM UTC 24 |
222574454 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.767196681 |
|
|
Oct 15 04:40:48 AM UTC 24 |
Oct 15 04:41:12 AM UTC 24 |
957790039 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2425131894 |
|
|
Oct 15 04:40:29 AM UTC 24 |
Oct 15 04:41:12 AM UTC 24 |
1778416264 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.4226407937 |
|
|
Oct 15 04:40:59 AM UTC 24 |
Oct 15 04:41:14 AM UTC 24 |
392218765 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.3979678803 |
|
|
Oct 15 04:41:10 AM UTC 24 |
Oct 15 04:41:14 AM UTC 24 |
284316031 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.82297076 |
|
|
Oct 15 04:40:56 AM UTC 24 |
Oct 15 04:41:14 AM UTC 24 |
553115389 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.3048519932 |
|
|
Oct 15 04:41:02 AM UTC 24 |
Oct 15 04:41:17 AM UTC 24 |
894797245 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.2921092011 |
|
|
Oct 15 04:40:20 AM UTC 24 |
Oct 15 04:41:18 AM UTC 24 |
2240081752 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.547809993 |
|
|
Oct 15 04:41:15 AM UTC 24 |
Oct 15 04:41:18 AM UTC 24 |
138643274 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.896943864 |
|
|
Oct 15 04:41:02 AM UTC 24 |
Oct 15 04:41:19 AM UTC 24 |
6102850270 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1953299583 |
|
|
Oct 15 04:41:19 AM UTC 24 |
Oct 15 04:41:21 AM UTC 24 |
32626342 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1026351687 |
|
|
Oct 15 04:41:10 AM UTC 24 |
Oct 15 04:41:21 AM UTC 24 |
87170198 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.3030993687 |
|
|
Oct 15 04:41:01 AM UTC 24 |
Oct 15 04:41:22 AM UTC 24 |
734101471 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.726542664 |
|
|
Oct 15 04:41:12 AM UTC 24 |
Oct 15 04:41:22 AM UTC 24 |
2831722394 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3977227944 |
|
|
Oct 15 04:41:18 AM UTC 24 |
Oct 15 04:41:23 AM UTC 24 |
149403071 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.312296236 |
|
|
Oct 15 04:41:10 AM UTC 24 |
Oct 15 04:41:25 AM UTC 24 |
1342751439 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.3469594171 |
|
|
Oct 15 04:41:12 AM UTC 24 |
Oct 15 04:41:26 AM UTC 24 |
1415515855 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.299461199 |
|
|
Oct 15 04:41:22 AM UTC 24 |
Oct 15 04:41:27 AM UTC 24 |
95367184 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.201808690 |
|
|
Oct 15 04:41:14 AM UTC 24 |
Oct 15 04:41:29 AM UTC 24 |
1891828832 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.433014861 |
|
|
Oct 15 04:41:14 AM UTC 24 |
Oct 15 04:41:31 AM UTC 24 |
1657483329 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.789042370 |
|
|
Oct 15 04:41:20 AM UTC 24 |
Oct 15 04:41:31 AM UTC 24 |
59088828 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.3292668155 |
|
|
Oct 15 04:41:11 AM UTC 24 |
Oct 15 04:41:32 AM UTC 24 |
1237289809 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.2878595135 |
|
|
Oct 15 04:41:23 AM UTC 24 |
Oct 15 04:41:33 AM UTC 24 |
348925144 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2964403740 |
|
|
Oct 15 04:39:53 AM UTC 24 |
Oct 15 04:41:33 AM UTC 24 |
3331678299 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1363331506 |
|
|
Oct 15 04:41:23 AM UTC 24 |
Oct 15 04:41:34 AM UTC 24 |
5924415438 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3609689499 |
|
|
Oct 15 04:41:32 AM UTC 24 |
Oct 15 04:41:35 AM UTC 24 |
19818748 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.4198127275 |
|
|
Oct 15 04:41:22 AM UTC 24 |
Oct 15 04:41:35 AM UTC 24 |
1766932173 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1399686790 |
|
|
Oct 15 04:41:34 AM UTC 24 |
Oct 15 04:41:36 AM UTC 24 |
28923794 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1716801313 |
|
|
Oct 15 04:40:51 AM UTC 24 |
Oct 15 04:41:37 AM UTC 24 |
2506493541 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.1275371263 |
|
|
Oct 15 04:41:27 AM UTC 24 |
Oct 15 04:41:37 AM UTC 24 |
844131386 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.2584431405 |
|
|
Oct 15 04:41:32 AM UTC 24 |
Oct 15 04:41:38 AM UTC 24 |
49811765 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1499378617 |
|
|
Oct 15 04:41:09 AM UTC 24 |
Oct 15 04:41:39 AM UTC 24 |
350643810 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.2202196663 |
|
|
Oct 15 04:41:35 AM UTC 24 |
Oct 15 04:41:40 AM UTC 24 |
70990240 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.1192122427 |
|
|
Oct 15 04:41:23 AM UTC 24 |
Oct 15 04:41:41 AM UTC 24 |
243172003 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.557787296 |
|
|
Oct 15 04:41:26 AM UTC 24 |
Oct 15 04:41:43 AM UTC 24 |
658476826 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.3842337380 |
|
|
Oct 15 04:41:35 AM UTC 24 |
Oct 15 04:41:44 AM UTC 24 |
64317347 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.1663728161 |
|
|
Oct 15 04:41:42 AM UTC 24 |
Oct 15 04:41:44 AM UTC 24 |
18167308 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2428281738 |
|
|
Oct 15 04:40:04 AM UTC 24 |
Oct 15 04:41:46 AM UTC 24 |
14244950717 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2795824062 |
|
|
Oct 15 04:41:44 AM UTC 24 |
Oct 15 04:41:47 AM UTC 24 |
21458791 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.1886679342 |
|
|
Oct 15 04:41:38 AM UTC 24 |
Oct 15 04:41:48 AM UTC 24 |
250906428 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3026922232 |
|
|
Oct 15 04:42:27 AM UTC 24 |
Oct 15 04:42:47 AM UTC 24 |
272749636 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.1022650615 |
|
|
Oct 15 04:41:44 AM UTC 24 |
Oct 15 04:41:49 AM UTC 24 |
289594296 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.2620316727 |
|
|
Oct 15 04:41:48 AM UTC 24 |
Oct 15 04:41:51 AM UTC 24 |
38335644 ps |