| T367 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.790232974 |
|
|
Feb 09 02:12:04 PM UTC 25 |
Feb 09 02:12:34 PM UTC 25 |
2634916453 ps |
| T368 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.751640501 |
|
|
Feb 09 02:12:31 PM UTC 25 |
Feb 09 02:12:36 PM UTC 25 |
783785633 ps |
| T369 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2732195404 |
|
|
Feb 09 02:12:32 PM UTC 25 |
Feb 09 02:12:39 PM UTC 25 |
348057603 ps |
| T370 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1780997345 |
|
|
Feb 09 02:12:33 PM UTC 25 |
Feb 09 02:12:40 PM UTC 25 |
2235924547 ps |
| T371 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4110181920 |
|
|
Feb 09 02:13:48 PM UTC 25 |
Feb 09 02:13:51 PM UTC 25 |
42977894 ps |
| T372 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.3995787647 |
|
|
Feb 09 02:12:26 PM UTC 25 |
Feb 09 02:12:43 PM UTC 25 |
134165317 ps |
| T373 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.1577514771 |
|
|
Feb 09 02:12:30 PM UTC 25 |
Feb 09 02:12:45 PM UTC 25 |
498403624 ps |
| T374 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.2259989153 |
|
|
Feb 09 02:11:42 PM UTC 25 |
Feb 09 02:12:46 PM UTC 25 |
1288473491 ps |
| T375 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.3555053420 |
|
|
Feb 09 02:12:44 PM UTC 25 |
Feb 09 02:12:47 PM UTC 25 |
39866542 ps |
| T376 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1150194981 |
|
|
Feb 09 02:12:29 PM UTC 25 |
Feb 09 02:12:49 PM UTC 25 |
325579587 ps |
| T377 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2515387963 |
|
|
Feb 09 02:12:47 PM UTC 25 |
Feb 09 02:12:50 PM UTC 25 |
18619235 ps |
| T378 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.3834848777 |
|
|
Feb 09 02:12:34 PM UTC 25 |
Feb 09 02:12:52 PM UTC 25 |
456643295 ps |
| T56 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.2059747793 |
|
|
Feb 09 02:11:12 PM UTC 25 |
Feb 09 02:12:53 PM UTC 25 |
11870345746 ps |
| T83 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3617579715 |
|
|
Feb 09 02:12:46 PM UTC 25 |
Feb 09 02:12:53 PM UTC 25 |
466051911 ps |
| T379 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.3981786186 |
|
|
Feb 09 02:12:31 PM UTC 25 |
Feb 09 02:12:53 PM UTC 25 |
1940466644 ps |
| T59 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.1186581199 |
|
|
Feb 09 02:11:35 PM UTC 25 |
Feb 09 02:12:53 PM UTC 25 |
3948985172 ps |
| T380 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2604261122 |
|
|
Feb 09 02:12:33 PM UTC 25 |
Feb 09 02:12:55 PM UTC 25 |
4497052014 ps |
| T381 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2020095368 |
|
|
Feb 09 02:12:50 PM UTC 25 |
Feb 09 02:12:55 PM UTC 25 |
65114111 ps |
| T382 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.1514373612 |
|
|
Feb 09 02:12:50 PM UTC 25 |
Feb 09 02:12:56 PM UTC 25 |
93427745 ps |
| T383 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.3834912559 |
|
|
Feb 09 02:12:37 PM UTC 25 |
Feb 09 02:12:57 PM UTC 25 |
629596502 ps |
| T384 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1267917618 |
|
|
Feb 09 02:12:01 PM UTC 25 |
Feb 09 02:13:01 PM UTC 25 |
293482478 ps |
| T385 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.823565425 |
|
|
Feb 09 02:12:57 PM UTC 25 |
Feb 09 02:13:01 PM UTC 25 |
123835917 ps |
| T60 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.4052131688 |
|
|
Feb 09 02:09:28 PM UTC 25 |
Feb 09 02:13:01 PM UTC 25 |
33413914384 ps |
| T386 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.4046299182 |
|
|
Feb 09 02:12:25 PM UTC 25 |
Feb 09 02:13:02 PM UTC 25 |
470331796 ps |
| T387 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2409987514 |
|
|
Feb 09 02:12:54 PM UTC 25 |
Feb 09 02:13:03 PM UTC 25 |
254423893 ps |
| T388 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.1084002861 |
|
|
Feb 09 02:12:54 PM UTC 25 |
Feb 09 02:13:06 PM UTC 25 |
664141637 ps |
| T389 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.1308376844 |
|
|
Feb 09 02:13:03 PM UTC 25 |
Feb 09 02:13:06 PM UTC 25 |
327988841 ps |
| T390 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3046882319 |
|
|
Feb 09 02:13:04 PM UTC 25 |
Feb 09 02:13:06 PM UTC 25 |
17996081 ps |
| T391 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.3825660106 |
|
|
Feb 09 02:12:54 PM UTC 25 |
Feb 09 02:13:08 PM UTC 25 |
638316567 ps |
| T392 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.215322814 |
|
|
Feb 09 02:12:53 PM UTC 25 |
Feb 09 02:13:08 PM UTC 25 |
994243873 ps |
| T393 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.1924776986 |
|
|
Feb 09 02:13:03 PM UTC 25 |
Feb 09 02:13:09 PM UTC 25 |
208301906 ps |
| T394 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.2716377740 |
|
|
Feb 09 02:12:57 PM UTC 25 |
Feb 09 02:13:10 PM UTC 25 |
2440178397 ps |
| T395 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.1240004609 |
|
|
Feb 09 02:12:58 PM UTC 25 |
Feb 09 02:13:11 PM UTC 25 |
361663332 ps |
| T396 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.1406534190 |
|
|
Feb 09 02:12:58 PM UTC 25 |
Feb 09 02:13:11 PM UTC 25 |
1235044311 ps |
| T397 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.967801123 |
|
|
Feb 09 02:13:07 PM UTC 25 |
Feb 09 02:13:13 PM UTC 25 |
216666950 ps |
| T398 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.2517505523 |
|
|
Feb 09 02:11:46 PM UTC 25 |
Feb 09 02:13:15 PM UTC 25 |
2370813601 ps |
| T399 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.4108964636 |
|
|
Feb 09 02:13:07 PM UTC 25 |
Feb 09 02:13:15 PM UTC 25 |
105977409 ps |
| T114 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.103555199 |
|
|
Feb 09 02:12:31 PM UTC 25 |
Feb 09 02:13:52 PM UTC 25 |
1579956987 ps |
| T400 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.1828198031 |
|
|
Feb 09 02:12:47 PM UTC 25 |
Feb 09 02:13:17 PM UTC 25 |
238884416 ps |
| T401 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3601318017 |
|
|
Feb 09 02:12:57 PM UTC 25 |
Feb 09 02:13:17 PM UTC 25 |
4767134393 ps |
| T215 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.4231649198 |
|
|
Feb 09 02:13:09 PM UTC 25 |
Feb 09 02:13:19 PM UTC 25 |
999300670 ps |
| T79 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3001104327 |
|
|
Feb 09 02:13:10 PM UTC 25 |
Feb 09 02:13:22 PM UTC 25 |
492451187 ps |
| T402 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.1062457693 |
|
|
Feb 09 02:12:08 PM UTC 25 |
Feb 09 02:13:22 PM UTC 25 |
1307231869 ps |
| T403 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.1610748 |
|
|
Feb 09 02:13:09 PM UTC 25 |
Feb 09 02:13:22 PM UTC 25 |
947073939 ps |
| T404 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.127456239 |
|
|
Feb 09 02:13:23 PM UTC 25 |
Feb 09 02:13:25 PM UTC 25 |
32457182 ps |
| T405 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.2030087557 |
|
|
Feb 09 02:13:12 PM UTC 25 |
Feb 09 02:13:25 PM UTC 25 |
1376211571 ps |
| T406 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.1486305053 |
|
|
Feb 09 02:13:23 PM UTC 25 |
Feb 09 02:13:25 PM UTC 25 |
285663740 ps |
| T407 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3192812909 |
|
|
Feb 09 02:13:12 PM UTC 25 |
Feb 09 02:13:26 PM UTC 25 |
779776910 ps |
| T408 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.2427630032 |
|
|
Feb 09 02:13:16 PM UTC 25 |
Feb 09 02:13:27 PM UTC 25 |
447971860 ps |
| T409 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.2382847224 |
|
|
Feb 09 02:13:23 PM UTC 25 |
Feb 09 02:13:28 PM UTC 25 |
56185410 ps |
| T410 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.4063614705 |
|
|
Feb 09 02:13:26 PM UTC 25 |
Feb 09 02:13:30 PM UTC 25 |
143344922 ps |
| T411 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.3344045254 |
|
|
Feb 09 02:13:16 PM UTC 25 |
Feb 09 02:13:35 PM UTC 25 |
428108705 ps |
| T100 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1848351944 |
|
|
Feb 09 02:09:05 PM UTC 25 |
Feb 09 02:13:35 PM UTC 25 |
14610989233 ps |
| T412 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.1320470348 |
|
|
Feb 09 02:13:18 PM UTC 25 |
Feb 09 02:13:36 PM UTC 25 |
583281591 ps |
| T413 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.2477639217 |
|
|
Feb 09 02:13:18 PM UTC 25 |
Feb 09 02:13:37 PM UTC 25 |
371251510 ps |
| T414 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3544152771 |
|
|
Feb 09 02:13:29 PM UTC 25 |
Feb 09 02:13:40 PM UTC 25 |
1730455925 ps |
| T415 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.412680023 |
|
|
Feb 09 02:13:36 PM UTC 25 |
Feb 09 02:13:41 PM UTC 25 |
1015024976 ps |
| T416 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.1798203659 |
|
|
Feb 09 02:09:42 PM UTC 25 |
Feb 09 02:13:44 PM UTC 25 |
7118093407 ps |
| T417 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.957014216 |
|
|
Feb 09 02:13:27 PM UTC 25 |
Feb 09 02:13:44 PM UTC 25 |
1088023014 ps |
| T418 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.342593964 |
|
|
Feb 09 02:13:26 PM UTC 25 |
Feb 09 02:13:44 PM UTC 25 |
117343080 ps |
| T419 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.257678220 |
|
|
Feb 09 02:13:28 PM UTC 25 |
Feb 09 02:13:47 PM UTC 25 |
626251197 ps |
| T420 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.4018092797 |
|
|
Feb 09 02:13:45 PM UTC 25 |
Feb 09 02:13:48 PM UTC 25 |
11855504 ps |
| T421 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.142417186 |
|
|
Feb 09 02:13:35 PM UTC 25 |
Feb 09 02:13:48 PM UTC 25 |
567841652 ps |
| T422 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.454872615 |
|
|
Feb 09 02:13:36 PM UTC 25 |
Feb 09 02:13:49 PM UTC 25 |
2177419984 ps |
| T423 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.3379296168 |
|
|
Feb 09 02:12:57 PM UTC 25 |
Feb 09 02:13:49 PM UTC 25 |
2430509244 ps |
| T424 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.4172533063 |
|
|
Feb 09 02:13:38 PM UTC 25 |
Feb 09 02:13:49 PM UTC 25 |
460535632 ps |
| T425 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.3347377663 |
|
|
Feb 09 02:13:45 PM UTC 25 |
Feb 09 02:13:50 PM UTC 25 |
43236407 ps |
| T426 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.827701160 |
|
|
Feb 09 02:12:33 PM UTC 25 |
Feb 09 02:13:55 PM UTC 25 |
8412174946 ps |
| T427 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.729127862 |
|
|
Feb 09 02:13:49 PM UTC 25 |
Feb 09 02:13:55 PM UTC 25 |
67057210 ps |
| T428 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.2822278116 |
|
|
Feb 09 02:13:30 PM UTC 25 |
Feb 09 02:14:00 PM UTC 25 |
2476407261 ps |
| T429 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1383858213 |
|
|
Feb 09 02:10:37 PM UTC 25 |
Feb 09 02:14:01 PM UTC 25 |
18263551839 ps |
| T430 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3313909668 |
|
|
Feb 09 02:13:52 PM UTC 25 |
Feb 09 02:14:01 PM UTC 25 |
2850071798 ps |
| T431 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.128379338 |
|
|
Feb 09 02:12:54 PM UTC 25 |
Feb 09 02:14:01 PM UTC 25 |
17757217416 ps |
| T432 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.1816138889 |
|
|
Feb 09 02:13:50 PM UTC 25 |
Feb 09 02:14:02 PM UTC 25 |
1031529295 ps |
| T433 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.2002177051 |
|
|
Feb 09 02:13:56 PM UTC 25 |
Feb 09 02:14:02 PM UTC 25 |
278534877 ps |
| T434 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.3135485755 |
|
|
Feb 09 02:13:53 PM UTC 25 |
Feb 09 02:14:05 PM UTC 25 |
988096498 ps |
| T435 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.3854388430 |
|
|
Feb 09 02:14:03 PM UTC 25 |
Feb 09 02:14:05 PM UTC 25 |
36113444 ps |
| T436 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1758400707 |
|
|
Feb 09 02:14:03 PM UTC 25 |
Feb 09 02:14:05 PM UTC 25 |
41714560 ps |
| T437 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1916212029 |
|
|
Feb 09 02:13:50 PM UTC 25 |
Feb 09 02:14:06 PM UTC 25 |
560236269 ps |
| T438 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.1855319306 |
|
|
Feb 09 02:10:15 PM UTC 25 |
Feb 09 02:14:06 PM UTC 25 |
105929579025 ps |
| T439 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3128669842 |
|
|
Feb 09 02:13:41 PM UTC 25 |
Feb 09 02:14:07 PM UTC 25 |
2974091910 ps |
| T440 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.3792154882 |
|
|
Feb 09 02:13:26 PM UTC 25 |
Feb 09 02:14:09 PM UTC 25 |
265062717 ps |
| T441 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2657646547 |
|
|
Feb 09 02:14:03 PM UTC 25 |
Feb 09 02:14:09 PM UTC 25 |
183600316 ps |
| T442 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.3691017810 |
|
|
Feb 09 02:13:36 PM UTC 25 |
Feb 09 02:14:10 PM UTC 25 |
9140103425 ps |
| T443 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.3786154884 |
|
|
Feb 09 02:13:56 PM UTC 25 |
Feb 09 02:14:10 PM UTC 25 |
365039168 ps |
| T444 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.2469001280 |
|
|
Feb 09 02:14:06 PM UTC 25 |
Feb 09 02:14:11 PM UTC 25 |
243146740 ps |
| T445 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.4036070293 |
|
|
Feb 09 02:13:06 PM UTC 25 |
Feb 09 02:14:14 PM UTC 25 |
334455709 ps |
| T446 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.2792041000 |
|
|
Feb 09 02:13:53 PM UTC 25 |
Feb 09 02:14:15 PM UTC 25 |
1573282793 ps |
| T447 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.3246060781 |
|
|
Feb 09 02:14:12 PM UTC 25 |
Feb 09 02:14:15 PM UTC 25 |
73279052 ps |
| T448 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.1107018765 |
|
|
Feb 09 02:14:06 PM UTC 25 |
Feb 09 02:14:17 PM UTC 25 |
57668974 ps |
| T449 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.51800868 |
|
|
Feb 09 02:13:13 PM UTC 25 |
Feb 09 02:14:18 PM UTC 25 |
16224005438 ps |
| T450 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.211439243 |
|
|
Feb 09 02:14:02 PM UTC 25 |
Feb 09 02:14:20 PM UTC 25 |
2011248071 ps |
| T451 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3771466532 |
|
|
Feb 09 02:14:00 PM UTC 25 |
Feb 09 02:14:20 PM UTC 25 |
4495741829 ps |
| T452 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.1277179582 |
|
|
Feb 09 02:14:08 PM UTC 25 |
Feb 09 02:14:22 PM UTC 25 |
203559928 ps |
| T453 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.2674153191 |
|
|
Feb 09 02:13:11 PM UTC 25 |
Feb 09 02:14:22 PM UTC 25 |
1592937993 ps |
| T454 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.4238715928 |
|
|
Feb 09 02:14:10 PM UTC 25 |
Feb 09 02:14:23 PM UTC 25 |
367841820 ps |
| T455 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.2415897197 |
|
|
Feb 09 02:14:08 PM UTC 25 |
Feb 09 02:14:23 PM UTC 25 |
597929673 ps |
| T456 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.2483791574 |
|
|
Feb 09 02:14:08 PM UTC 25 |
Feb 09 02:14:23 PM UTC 25 |
1426961489 ps |
| T457 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.3753611460 |
|
|
Feb 09 02:14:22 PM UTC 25 |
Feb 09 02:14:24 PM UTC 25 |
20706605 ps |
| T458 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.2547896412 |
|
|
Feb 09 02:14:16 PM UTC 25 |
Feb 09 02:14:25 PM UTC 25 |
200429075 ps |
| T459 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.2153338763 |
|
|
Feb 09 02:14:22 PM UTC 25 |
Feb 09 02:14:25 PM UTC 25 |
46733850 ps |
| T460 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.868729660 |
|
|
Feb 09 02:14:23 PM UTC 25 |
Feb 09 02:14:25 PM UTC 25 |
41625151 ps |
| T461 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.3778005888 |
|
|
Feb 09 02:14:16 PM UTC 25 |
Feb 09 02:14:27 PM UTC 25 |
440061439 ps |
| T462 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.394617131 |
|
|
Feb 09 02:14:15 PM UTC 25 |
Feb 09 02:14:28 PM UTC 25 |
475380849 ps |
| T463 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.4043497027 |
|
|
Feb 09 02:14:24 PM UTC 25 |
Feb 09 02:14:29 PM UTC 25 |
171673734 ps |
| T464 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3014450792 |
|
|
Feb 09 02:14:10 PM UTC 25 |
Feb 09 02:14:31 PM UTC 25 |
425502752 ps |
| T465 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.219661596 |
|
|
Feb 09 02:14:25 PM UTC 25 |
Feb 09 02:14:34 PM UTC 25 |
1056482709 ps |
| T466 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2784022876 |
|
|
Feb 09 02:14:24 PM UTC 25 |
Feb 09 02:14:35 PM UTC 25 |
256094009 ps |
| T467 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.1412523914 |
|
|
Feb 09 02:14:27 PM UTC 25 |
Feb 09 02:14:35 PM UTC 25 |
304893682 ps |
| T468 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.291044137 |
|
|
Feb 09 02:14:12 PM UTC 25 |
Feb 09 02:14:36 PM UTC 25 |
1026914916 ps |
| T469 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.2523475022 |
|
|
Feb 09 02:14:29 PM UTC 25 |
Feb 09 02:14:36 PM UTC 25 |
501248705 ps |
| T470 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.4057334260 |
|
|
Feb 09 02:13:49 PM UTC 25 |
Feb 09 02:14:40 PM UTC 25 |
245611513 ps |
| T471 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.4053985993 |
|
|
Feb 09 02:14:38 PM UTC 25 |
Feb 09 02:14:40 PM UTC 25 |
119059769 ps |
| T472 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.362710929 |
|
|
Feb 09 02:14:24 PM UTC 25 |
Feb 09 02:14:41 PM UTC 25 |
500039688 ps |
| T473 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.406575816 |
|
|
Feb 09 02:14:32 PM UTC 25 |
Feb 09 02:14:41 PM UTC 25 |
1120268963 ps |
| T474 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3252003554 |
|
|
Feb 09 02:14:41 PM UTC 25 |
Feb 09 02:14:43 PM UTC 25 |
12756459 ps |
| T475 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.1336718770 |
|
|
Feb 09 02:14:38 PM UTC 25 |
Feb 09 02:14:44 PM UTC 25 |
1039099975 ps |
| T476 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.2710608785 |
|
|
Feb 09 02:14:25 PM UTC 25 |
Feb 09 02:14:44 PM UTC 25 |
320650739 ps |
| T477 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.1204986974 |
|
|
Feb 09 02:13:55 PM UTC 25 |
Feb 09 02:14:47 PM UTC 25 |
1496233093 ps |
| T478 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.4178161937 |
|
|
Feb 09 02:14:42 PM UTC 25 |
Feb 09 02:14:47 PM UTC 25 |
355289558 ps |
| T479 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2660106270 |
|
|
Feb 09 02:14:30 PM UTC 25 |
Feb 09 02:14:48 PM UTC 25 |
291411992 ps |
| T480 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2288858889 |
|
|
Feb 09 02:13:29 PM UTC 25 |
Feb 09 02:14:49 PM UTC 25 |
6507475295 ps |
| T481 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.3581608739 |
|
|
Feb 09 02:14:27 PM UTC 25 |
Feb 09 02:14:50 PM UTC 25 |
3228054983 ps |
| T482 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.2575736862 |
|
|
Feb 09 02:14:48 PM UTC 25 |
Feb 09 02:14:52 PM UTC 25 |
56734240 ps |
| T483 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2595905409 |
|
|
Feb 09 02:14:06 PM UTC 25 |
Feb 09 02:14:53 PM UTC 25 |
376067281 ps |
| T484 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.4270515070 |
|
|
Feb 09 02:14:10 PM UTC 25 |
Feb 09 02:14:53 PM UTC 25 |
816278603 ps |
| T485 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3927907471 |
|
|
Feb 09 02:14:50 PM UTC 25 |
Feb 09 02:14:54 PM UTC 25 |
94652833 ps |
| T486 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.1914358076 |
|
|
Feb 09 02:14:42 PM UTC 25 |
Feb 09 02:14:54 PM UTC 25 |
87961393 ps |
| T487 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.491585841 |
|
|
Feb 09 02:14:44 PM UTC 25 |
Feb 09 02:14:57 PM UTC 25 |
443713038 ps |
| T488 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.1136167738 |
|
|
Feb 09 02:14:35 PM UTC 25 |
Feb 09 02:14:58 PM UTC 25 |
775242691 ps |
| T489 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.955457390 |
|
|
Feb 09 02:14:56 PM UTC 25 |
Feb 09 02:14:59 PM UTC 25 |
39311783 ps |
| T490 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.997041433 |
|
|
Feb 09 02:14:18 PM UTC 25 |
Feb 09 02:14:59 PM UTC 25 |
1808982627 ps |
| T491 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.2146835574 |
|
|
Feb 09 02:14:44 PM UTC 25 |
Feb 09 02:14:59 PM UTC 25 |
340516357 ps |
| T492 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.2487817091 |
|
|
Feb 09 02:14:45 PM UTC 25 |
Feb 09 02:15:01 PM UTC 25 |
454812192 ps |
| T493 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3758157145 |
|
|
Feb 09 02:14:59 PM UTC 25 |
Feb 09 02:15:02 PM UTC 25 |
18777907 ps |
| T494 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1591139956 |
|
|
Feb 09 02:15:11 PM UTC 25 |
Feb 09 02:15:13 PM UTC 25 |
13556945 ps |
| T495 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.1817555490 |
|
|
Feb 09 02:12:40 PM UTC 25 |
Feb 09 02:15:02 PM UTC 25 |
9864438111 ps |
| T496 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.3434141314 |
|
|
Feb 09 02:14:53 PM UTC 25 |
Feb 09 02:15:05 PM UTC 25 |
485336487 ps |
| T497 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.4136722708 |
|
|
Feb 09 02:14:28 PM UTC 25 |
Feb 09 02:15:05 PM UTC 25 |
3531062947 ps |
| T498 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.1978564143 |
|
|
Feb 09 02:14:41 PM UTC 25 |
Feb 09 02:15:06 PM UTC 25 |
696283051 ps |
| T499 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.1720788416 |
|
|
Feb 09 02:15:00 PM UTC 25 |
Feb 09 02:15:06 PM UTC 25 |
243392875 ps |
| T500 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.3312245340 |
|
|
Feb 09 02:15:00 PM UTC 25 |
Feb 09 02:15:07 PM UTC 25 |
78214444 ps |
| T501 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.132305178 |
|
|
Feb 09 02:14:58 PM UTC 25 |
Feb 09 02:15:08 PM UTC 25 |
154497755 ps |
| T502 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.429717876 |
|
|
Feb 09 02:14:23 PM UTC 25 |
Feb 09 02:15:09 PM UTC 25 |
324947794 ps |
| T503 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.3866966874 |
|
|
Feb 09 02:15:08 PM UTC 25 |
Feb 09 02:15:11 PM UTC 25 |
45115970 ps |
| T504 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.949049378 |
|
|
Feb 09 02:13:52 PM UTC 25 |
Feb 09 02:15:11 PM UTC 25 |
1631727877 ps |
| T505 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.2567496648 |
|
|
Feb 09 02:15:08 PM UTC 25 |
Feb 09 02:15:12 PM UTC 25 |
127037360 ps |
| T506 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.409194688 |
|
|
Feb 09 02:15:01 PM UTC 25 |
Feb 09 02:15:15 PM UTC 25 |
302443155 ps |
| T507 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.4055882149 |
|
|
Feb 09 02:14:50 PM UTC 25 |
Feb 09 02:15:15 PM UTC 25 |
688401192 ps |
| T508 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1007795535 |
|
|
Feb 09 02:15:02 PM UTC 25 |
Feb 09 02:15:15 PM UTC 25 |
410814719 ps |
| T509 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2708239881 |
|
|
Feb 09 02:15:12 PM UTC 25 |
Feb 09 02:15:16 PM UTC 25 |
99339629 ps |
| T510 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.2102746375 |
|
|
Feb 09 02:15:04 PM UTC 25 |
Feb 09 02:15:16 PM UTC 25 |
779896339 ps |
| T511 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.2906784005 |
|
|
Feb 09 02:15:12 PM UTC 25 |
Feb 09 02:15:17 PM UTC 25 |
158335499 ps |
| T61 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.181576878 |
|
|
Feb 09 02:12:18 PM UTC 25 |
Feb 09 02:15:17 PM UTC 25 |
23040851472 ps |
| T512 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.3179382466 |
|
|
Feb 09 02:15:04 PM UTC 25 |
Feb 09 02:15:18 PM UTC 25 |
572690660 ps |
| T513 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.4031476793 |
|
|
Feb 09 02:14:48 PM UTC 25 |
Feb 09 02:15:18 PM UTC 25 |
854909157 ps |
| T514 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1293305949 |
|
|
Feb 09 02:15:06 PM UTC 25 |
Feb 09 02:15:19 PM UTC 25 |
1005372830 ps |
| T515 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3079054056 |
|
|
Feb 09 02:15:06 PM UTC 25 |
Feb 09 02:15:19 PM UTC 25 |
241360155 ps |
| T516 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.998222776 |
|
|
Feb 09 02:14:55 PM UTC 25 |
Feb 09 02:15:22 PM UTC 25 |
482371393 ps |
| T517 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2035613388 |
|
|
Feb 09 02:15:19 PM UTC 25 |
Feb 09 02:15:22 PM UTC 25 |
12529355 ps |
| T518 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.85215021 |
|
|
Feb 09 02:15:19 PM UTC 25 |
Feb 09 02:15:22 PM UTC 25 |
19706493 ps |
| T519 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.390712815 |
|
|
Feb 09 02:15:19 PM UTC 25 |
Feb 09 02:15:25 PM UTC 25 |
67705931 ps |
| T520 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.2045378392 |
|
|
Feb 09 02:10:53 PM UTC 25 |
Feb 09 02:15:25 PM UTC 25 |
36650706016 ps |
| T521 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.3166967938 |
|
|
Feb 09 02:11:51 PM UTC 25 |
Feb 09 02:15:27 PM UTC 25 |
4858872040 ps |
| T522 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.968130690 |
|
|
Feb 09 02:15:23 PM UTC 25 |
Feb 09 02:15:28 PM UTC 25 |
295289796 ps |
| T523 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.366311351 |
|
|
Feb 09 02:15:16 PM UTC 25 |
Feb 09 02:15:30 PM UTC 25 |
306336463 ps |
| T524 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.4057594799 |
|
|
Feb 09 02:15:25 PM UTC 25 |
Feb 09 02:15:30 PM UTC 25 |
344067249 ps |
| T525 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.3727700757 |
|
|
Feb 09 02:15:16 PM UTC 25 |
Feb 09 02:15:30 PM UTC 25 |
564336305 ps |
| T526 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3897697066 |
|
|
Feb 09 02:15:14 PM UTC 25 |
Feb 09 02:15:31 PM UTC 25 |
267920959 ps |
| T527 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2160484768 |
|
|
Feb 09 02:15:16 PM UTC 25 |
Feb 09 02:15:31 PM UTC 25 |
916243847 ps |
| T528 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.101488578 |
|
|
Feb 09 02:15:23 PM UTC 25 |
Feb 09 02:15:34 PM UTC 25 |
1183051427 ps |
| T529 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.3074719129 |
|
|
Feb 09 02:15:31 PM UTC 25 |
Feb 09 02:15:34 PM UTC 25 |
415479395 ps |
| T530 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3075907183 |
|
|
Feb 09 02:15:32 PM UTC 25 |
Feb 09 02:15:35 PM UTC 25 |
22725171 ps |
| T531 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1049331774 |
|
|
Feb 09 02:15:21 PM UTC 25 |
Feb 09 02:15:36 PM UTC 25 |
147278367 ps |
| T532 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1685727392 |
|
|
Feb 09 02:16:07 PM UTC 25 |
Feb 09 02:16:26 PM UTC 25 |
2712031306 ps |
| T533 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.1365975240 |
|
|
Feb 09 02:15:32 PM UTC 25 |
Feb 09 02:15:37 PM UTC 25 |
41093015 ps |
| T534 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.137700702 |
|
|
Feb 09 02:15:23 PM UTC 25 |
Feb 09 02:15:37 PM UTC 25 |
228907944 ps |
| T535 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.2261906861 |
|
|
Feb 09 02:15:16 PM UTC 25 |
Feb 09 02:15:38 PM UTC 25 |
326552525 ps |
| T536 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.904417270 |
|
|
Feb 09 02:15:29 PM UTC 25 |
Feb 09 02:15:39 PM UTC 25 |
639636778 ps |
| T537 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.2477026812 |
|
|
Feb 09 02:15:13 PM UTC 25 |
Feb 09 02:15:39 PM UTC 25 |
1205234805 ps |
| T538 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.1418038643 |
|
|
Feb 09 02:14:49 PM UTC 25 |
Feb 09 02:15:39 PM UTC 25 |
2597596416 ps |
| T539 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2952201792 |
|
|
Feb 09 02:14:36 PM UTC 25 |
Feb 09 02:16:27 PM UTC 25 |
24134602739 ps |
| T540 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.2377096160 |
|
|
Feb 09 02:15:34 PM UTC 25 |
Feb 09 02:15:40 PM UTC 25 |
201823520 ps |
| T541 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.3615530537 |
|
|
Feb 09 02:15:35 PM UTC 25 |
Feb 09 02:15:41 PM UTC 25 |
74767281 ps |
| T542 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.2717612594 |
|
|
Feb 09 02:15:29 PM UTC 25 |
Feb 09 02:15:43 PM UTC 25 |
371124584 ps |
| T543 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3207000589 |
|
|
Feb 09 02:15:41 PM UTC 25 |
Feb 09 02:15:43 PM UTC 25 |
18428128 ps |
| T544 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2420043502 |
|
|
Feb 09 02:15:25 PM UTC 25 |
Feb 09 02:15:44 PM UTC 25 |
436704998 ps |
| T545 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.112952162 |
|
|
Feb 09 02:13:42 PM UTC 25 |
Feb 09 02:15:46 PM UTC 25 |
2034834979 ps |
| T546 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1887126859 |
|
|
Feb 09 02:15:44 PM UTC 25 |
Feb 09 02:15:46 PM UTC 25 |
11991463 ps |
| T547 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1171489679 |
|
|
Feb 09 02:15:38 PM UTC 25 |
Feb 09 02:15:46 PM UTC 25 |
430704791 ps |
| T548 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.4186240562 |
|
|
Feb 09 02:15:19 PM UTC 25 |
Feb 09 02:15:47 PM UTC 25 |
1019091138 ps |
| T549 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.3542670665 |
|
|
Feb 09 02:14:59 PM UTC 25 |
Feb 09 02:15:49 PM UTC 25 |
255174041 ps |
| T550 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.3038618378 |
|
|
Feb 09 02:16:14 PM UTC 25 |
Feb 09 02:16:27 PM UTC 25 |
407921556 ps |
| T84 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.2471311862 |
|
|
Feb 09 02:15:43 PM UTC 25 |
Feb 09 02:15:49 PM UTC 25 |
134154105 ps |
| T551 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.313926107 |
|
|
Feb 09 02:15:45 PM UTC 25 |
Feb 09 02:15:50 PM UTC 25 |
77424617 ps |
| T552 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.3906535403 |
|
|
Feb 09 02:15:47 PM UTC 25 |
Feb 09 02:15:52 PM UTC 25 |
172941379 ps |
| T553 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.3365630539 |
|
|
Feb 09 02:15:39 PM UTC 25 |
Feb 09 02:15:54 PM UTC 25 |
465446209 ps |
| T554 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3883934526 |
|
|
Feb 09 02:15:38 PM UTC 25 |
Feb 09 02:15:58 PM UTC 25 |
1871835612 ps |
| T555 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2599867482 |
|
|
Feb 09 02:15:50 PM UTC 25 |
Feb 09 02:15:59 PM UTC 25 |
403513487 ps |
| T556 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.261947645 |
|
|
Feb 09 02:15:47 PM UTC 25 |
Feb 09 02:16:00 PM UTC 25 |
262520735 ps |
| T557 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2765507271 |
|
|
Feb 09 02:15:11 PM UTC 25 |
Feb 09 02:16:01 PM UTC 25 |
251264523 ps |
| T558 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.4217120071 |
|
|
Feb 09 02:15:51 PM UTC 25 |
Feb 09 02:16:01 PM UTC 25 |
397586539 ps |
| T559 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.3270906034 |
|
|
Feb 09 02:15:48 PM UTC 25 |
Feb 09 02:16:01 PM UTC 25 |
2172783040 ps |
| T560 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.3650378051 |
|
|
Feb 09 02:15:59 PM UTC 25 |
Feb 09 02:16:02 PM UTC 25 |
44516678 ps |
| T561 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.3712669723 |
|
|
Feb 09 02:15:39 PM UTC 25 |
Feb 09 02:16:02 PM UTC 25 |
2492081545 ps |
| T562 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1434409284 |
|
|
Feb 09 02:16:00 PM UTC 25 |
Feb 09 02:16:03 PM UTC 25 |
13097823 ps |
| T563 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3925883968 |
|
|
Feb 09 02:15:38 PM UTC 25 |
Feb 09 02:16:04 PM UTC 25 |
2416598139 ps |
| T564 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.1759044195 |
|
|
Feb 09 02:15:39 PM UTC 25 |
Feb 09 02:16:05 PM UTC 25 |
915722344 ps |
| T565 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.492452039 |
|
|
Feb 09 02:16:00 PM UTC 25 |
Feb 09 02:16:05 PM UTC 25 |
38670068 ps |
| T566 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.2024623594 |
|
|
Feb 09 02:15:47 PM UTC 25 |
Feb 09 02:16:06 PM UTC 25 |
1747918928 ps |
| T115 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.3971680808 |
|
|
Feb 09 02:14:25 PM UTC 25 |
Feb 09 02:16:06 PM UTC 25 |
8543831178 ps |
| T567 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.2002439660 |
|
|
Feb 09 02:15:50 PM UTC 25 |
Feb 09 02:16:07 PM UTC 25 |
346265644 ps |
| T568 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.1292877985 |
|
|
Feb 09 02:16:02 PM UTC 25 |
Feb 09 02:16:08 PM UTC 25 |
444244489 ps |
| T569 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.33019313 |
|
|
Feb 09 02:16:04 PM UTC 25 |
Feb 09 02:16:09 PM UTC 25 |
257869326 ps |
| T85 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.792905809 |
|
|
Feb 09 02:15:07 PM UTC 25 |
Feb 09 02:16:09 PM UTC 25 |
1974180518 ps |
| T570 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.596208540 |
|
|
Feb 09 02:16:03 PM UTC 25 |
Feb 09 02:16:10 PM UTC 25 |
868688430 ps |
| T571 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1280279363 |
|
|
Feb 09 02:16:08 PM UTC 25 |
Feb 09 02:16:11 PM UTC 25 |
55788151 ps |
| T572 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.34131098 |
|
|
Feb 09 02:16:10 PM UTC 25 |
Feb 09 02:16:13 PM UTC 25 |
12128043 ps |
| T573 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.291245527 |
|
|
Feb 09 02:16:09 PM UTC 25 |
Feb 09 02:16:13 PM UTC 25 |
25649013 ps |
| T574 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3887638933 |
|
|
Feb 09 02:16:02 PM UTC 25 |
Feb 09 02:16:13 PM UTC 25 |
78128653 ps |
| T575 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.4041830234 |
|
|
Feb 09 02:16:12 PM UTC 25 |
Feb 09 02:16:15 PM UTC 25 |
152144196 ps |
| T576 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2589216422 |
|
|
Feb 09 02:15:34 PM UTC 25 |
Feb 09 02:16:17 PM UTC 25 |
241409377 ps |
| T577 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3690332861 |
|
|
Feb 09 02:16:12 PM UTC 25 |
Feb 09 02:16:18 PM UTC 25 |
71858706 ps |
| T578 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1630264278 |
|
|
Feb 09 02:16:07 PM UTC 25 |
Feb 09 02:16:20 PM UTC 25 |
1459188446 ps |
| T579 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.4039112378 |
|
|
Feb 09 02:16:14 PM UTC 25 |
Feb 09 02:16:21 PM UTC 25 |
567084934 ps |
| T580 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.2048438705 |
|
|
Feb 09 02:16:03 PM UTC 25 |
Feb 09 02:16:22 PM UTC 25 |
331812538 ps |
| T581 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.1281257833 |
|
|
Feb 09 02:16:05 PM UTC 25 |
Feb 09 02:16:23 PM UTC 25 |
2311826925 ps |
| T582 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1582488638 |
|
|
Feb 09 02:16:14 PM UTC 25 |
Feb 09 02:16:24 PM UTC 25 |
1092318048 ps |
| T583 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3227583372 |
|
|
Feb 09 02:16:22 PM UTC 25 |
Feb 09 02:16:25 PM UTC 25 |
55275365 ps |
| T584 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.74076590 |
|
|
Feb 09 02:16:25 PM UTC 25 |
Feb 09 02:16:27 PM UTC 25 |
46354270 ps |
| T585 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.3391150106 |
|
|
Feb 09 02:16:02 PM UTC 25 |
Feb 09 02:16:27 PM UTC 25 |
819879771 ps |
| T586 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3380966171 |
|
|
Feb 09 02:16:25 PM UTC 25 |
Feb 09 02:16:28 PM UTC 25 |
23465084 ps |
| T587 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2387715781 |
|
|
Feb 09 02:16:19 PM UTC 25 |
Feb 09 02:16:29 PM UTC 25 |
932391108 ps |
| T588 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.731316354 |
|
|
Feb 09 02:16:27 PM UTC 25 |
Feb 09 02:16:33 PM UTC 25 |
54306617 ps |
| T589 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.2633275283 |
|
|
Feb 09 02:16:18 PM UTC 25 |
Feb 09 02:16:34 PM UTC 25 |
1231792930 ps |
| T590 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.1805554076 |
|
|
Feb 09 02:16:16 PM UTC 25 |
Feb 09 02:16:37 PM UTC 25 |
1585132946 ps |
| T591 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.974193944 |
|
|
Feb 09 02:16:29 PM UTC 25 |
Feb 09 02:16:39 PM UTC 25 |
1079445418 ps |
| T592 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.4119169599 |
|
|
Feb 09 02:15:44 PM UTC 25 |
Feb 09 02:16:39 PM UTC 25 |
198246165 ps |
| T593 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.2143887520 |
|
|
Feb 09 02:16:39 PM UTC 25 |
Feb 09 02:16:42 PM UTC 25 |
45616051 ps |
| T594 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2831892741 |
|
|
Feb 09 02:16:30 PM UTC 25 |
Feb 09 02:16:44 PM UTC 25 |
1527829592 ps |
| T595 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.4182409654 |
|
|
Feb 09 02:16:40 PM UTC 25 |
Feb 09 02:16:44 PM UTC 25 |
19135632 ps |
| T596 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.1409967091 |
|
|
Feb 09 02:16:29 PM UTC 25 |
Feb 09 02:16:44 PM UTC 25 |
458861005 ps |
| T597 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.633624602 |
|
|
Feb 09 02:16:27 PM UTC 25 |
Feb 09 02:16:44 PM UTC 25 |
93985223 ps |
| T598 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2248033668 |
|
|
Feb 09 02:16:42 PM UTC 25 |
Feb 09 02:16:45 PM UTC 25 |
13394031 ps |
| T599 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.1960170587 |
|
|
Feb 09 02:16:29 PM UTC 25 |
Feb 09 02:16:46 PM UTC 25 |
298067474 ps |
| T600 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3575759929 |
|
|
Feb 09 02:16:45 PM UTC 25 |
Feb 09 02:16:49 PM UTC 25 |
46349397 ps |
| T601 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.3849344971 |
|
|
Feb 09 02:16:34 PM UTC 25 |
Feb 09 02:16:54 PM UTC 25 |
373237504 ps |
| T602 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.39545428 |
|
|
Feb 09 02:14:46 PM UTC 25 |
Feb 09 02:16:55 PM UTC 25 |
15623830740 ps |
| T603 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.246461931 |
|
|
Feb 09 02:16:10 PM UTC 25 |
Feb 09 02:16:58 PM UTC 25 |
905021903 ps |
| T116 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.68053230 |
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Feb 09 02:16:26 PM UTC 25 |
Feb 09 02:16:59 PM UTC 25 |
709319538 ps |